Search results for "GALs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
140	Milos Krstic, Eckhard Grass, Frank K. Gürkaynak, Pascal Vivet	Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	asynchronous/synchronous operation, VLSI, interfaces, GALS
114	Xin Jia, Ranga Vemuri	Using GALS architecture to reduce the impact of long wire delay on FPGA performance.	ASP-DAC	2005	DBLP DOI BibTeX RDF
100	Ari Kulmala, Timo D. Hämäläinen, Marko Hännikäinen	Comparison of GALS and Synchronous Architectures with MPEG-4 Video Encoder on Multiprocessor System-on-Chip FPGA.	DSD	2006	DBLP DOI BibTeX RDF
87	Michael Kishinevsky, Sandeep K. Shukla, Ken S. Stevens	Guest Editors' Introduction: GALS Design and Validation.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	design, synchronous, validation, asynchronous
87	Frank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner	GALS at ETH Zurich: Success or Failure.	ASYNC	2006	DBLP DOI BibTeX RDF
87	Milos Krstic, Eckhard Grass, Christian Stahl	Request-Driven GALS Technique for Wireless Communication System.	ASYNC	2005	DBLP DOI BibTeX RDF
81	Mehrdad Najibi, Kamran Saleh, Mohsen Naderi, Hossein Pedram, Mehdi Sedighi	Prototyping globally asynchronous locally synchronous circuits on commercial synchronous FPGAs (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
81	Mehrdad Najibi, Kamran Saleh, Mohsen Naderi, Hossein Pedram, Mehdi Sedighi	Prototyping Globally Asynchronous Locally Synchronous Circuits on Commercial Synchronous FPGAs.	IEEE International Workshop on Rapid System Prototyping	2005	DBLP DOI BibTeX RDF
79	Paul Teehan, Mark R. Greenstreet, Guy G. Lemieux	A Survey and Taxonomy of GALS Design Styles.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	globally asynchronous, locally synchronous (GALS), clock domains, pausible clocks, loosely synchronous, synchronization, asynchronous
79	Matthew W. Heath, Wayne P. Burleson, Ian G. Harris	Synchro-Tokens: A Deterministic GALS Methodology for Chip-Level Debug and Test.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	test, debug, SoC, nondeterminism, GALS, globally asynchronous locally synchronous
74	Eckhard Grass, Frank Winkler 0001, Milos Krstic, Alexandra Julius, Christian Stahl, Maxim Piz	Enhanced GALS Techniques for Datapath Applications.	PATMOS	2005	DBLP DOI BibTeX RDF
73	Kamran Saleh, Mehrdad Najibi, Mohsen Naderi, Hossein Pedram, Mehdi Sedighi	A novel clock generation scheme for globally asynchronous locally synchronous systems: an FPGA-validated approach.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	on-chip clock generation, FPGA, GALS
73	Diana Marculescu, Emil Talpes	Variability and energy awareness: a microarchitecture-level perspective.	DAC	2005	DBLP DOI BibTeX RDF	GALS design, power consumption, variability
73	Alain Girault, Clément Ménier	Automatic Production of Globally Asynchronous Locally Synchronous Systems.	EMSOFT	2002	DBLP DOI BibTeX RDF	Globally synchronous-locally asynchronous (GALS), asynchronous communications, hardware/software codesign, distributed architectures, synchronous circuits, automatic distribution
67	Anoop Iyer, Diana Marculescu	Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors.	ISCA	2002	DBLP DOI BibTeX RDF
66	Edith Beigné, Fabien Clermidy, Sylvain Miermont, Pascal Vivet	Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC.	NOCS	2008	DBLP DOI BibTeX RDF	Pausable clock, Vdd Hopping, Network-on-Chip, power, DVFS, GALS
60	Rostislav (Reuven) Dobkin, Ran Ginosar, Christos P. Sotiriou	High Rate Data Synchronization in GALS SoCs.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
60	Sandeep K. Shukla, Michael Theobald	Special issue on formal methods for globally asynchronous and locally synchronous (GALS) systems.	Formal Methods Syst. Des.	2006	DBLP DOI BibTeX RDF
60	Ari Kulmala, Timo D. Hämäläinen, Marko Hännikäinen	Reliable GALS Implementation of MPEG-4 Encoder with Mixed Clock FIFO on Standard FPGA.	FPL	2006	DBLP DOI BibTeX RDF
60	Milos Krstic, Eckhard Grass	BIST Technique for GALS Systems.	DSD	2005	DBLP DOI BibTeX RDF
59	Avinash Malik, Zoran A. Salcic, Alain Girault, Adam Walker, Sung Chul Lee	A customizable multiprocessor for Globally Asynchronous Locally Synchronous execution.	JTRES	2009	DBLP DOI BibTeX RDF	synchronous and asynchronous concurrency, multiprocessor, GALS, reactivity
59	Adhir Upadhyay, Syed Rafay Hasan, Mohamed Nekili	Optimal partitioning of globally asychronous locally synchronous processor arrays.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	VLSI, partitioning, power optimization, GALS
54	Zhiyi Yu, Bevan M. Baas	Performance and Power Analysis of Globally Asynchronous Locally Synchronous Multi-Processor Systems.	ISVLSI	2006	DBLP DOI BibTeX RDF
54	Matthew W. Heath, Wayne P. Burleson, Ian G. Harris	Synchro-Tokens: Eliminating Nondeterminism to Enable Chip-Level Test of Globally-Asynchronous Locally-Synchronous SoC?s.	DATE	2004	DBLP DOI BibTeX RDF
54	Thomas Villiger, Stephan Oetiker, Frank K. Gürkaynak, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner	A Functional Test Methodology for Globally-Asynchronous Locally-Synchronous Systems.	ASYNC	2002	DBLP DOI BibTeX RDF
52	Luis A. Plana, Stephen B. Furber, Steve Temple, Muhammad Mukaram Khan, Yebin Shi, Jian Wu, Shufan Yang	A GALS Infrastructure for a Massively Parallel Multiprocessor.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	massively parallel multiprocessor, Spinnaker, self-timed interconnect, GALS, neural modeling
52	Carlos Fernández, Rajkumar K. Raval, Chris J. Bleakley	GALS SoC interconnect bus for wireless sensor network processor platforms.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	SoC bus, application specific bus, system on chip bus, WSN, wireless sensor network, low power, GALS
52	Supratik Chakraborty, Joycee Mekie, Dinesh K. Sharma	Reasoning about synchronization in GALS systems.	Formal Methods Syst. Des.	2006	DBLP DOI BibTeX RDF	Symbolic timing analysis, GALS systems, Multi-clocked systems, Symbolic delay constraints, Synchronization constraints, Sequencing constraints
52	Grigorios Magklis, Pedro Chaparro, José González 0002, Antonio González 0001	Independent front-end and back-end dynamic voltage scaling for a GALS microarchitecture.	ISLPED	2006	DBLP DOI BibTeX RDF	MCD, energy efficiency, DVS, microarchitecture, GALS
47	Nicolas Coste, Holger Hermanns, Etienne Lantreibecq, Wendelin Serwe	Towards Performance Prediction of Compositional Models in Industrial GALS Designs.	CAV	2009	DBLP DOI BibTeX RDF
47	Hubert Garavel, Damien Thivolle	Verification of GALS Systems by Combining Synchronous Languages and Process Calculi.	SPIN	2009	DBLP DOI BibTeX RDF
47	Abbas Sheibanyrad, Alain Greiner, Ivan Miro Panades	Multisynchronous and Fully Asynchronous NoCs for GALS Architectures.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF
47	Ryo Watanabe, Masaaki Kondo, Masashi Imai, Hiroshi Nakamura, Takashi Nanya	Interactive presentation: Task scheduling under performance constraints for reducing the energy consumption of the GALS multi-processor SoC.	DATE	2007	DBLP DOI BibTeX RDF
47	Hiroshi Sasaki 0001, Masaaki Kondo, Hiroshi Nakamura	Dynamic Instruction Cascading on GALS Microprocessors.	PATMOS	2005	DBLP DOI BibTeX RDF
47	Jerome Quartana, Laurent Fesquet, Marc Renaudin	Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
47	Christian Stahl, Wolfgang Reisig, Milos Krstic	Hazard Detection in a GALS Wrapper: A Case Study.	ACSD	2005	DBLP DOI BibTeX RDF
47	S. Ramesh, Sampada Sonalkar, Vijay D'Silva, Naveen Chandra, B. Vijayalakshmi	A Toolset for Modelling and Verification of GALS Systems.	CAV	2004	DBLP DOI BibTeX RDF
47	Sonia López, Oscar Garnica, José Manuel Colmenar	Enhancing GALS Processor Performance Using Data Classification Based on Data Latency.	PATMOS	2004	DBLP DOI BibTeX RDF
47	Steven G. Dropsho, Greg Semeraro, David H. Albonesi, Grigorios Magklis, Michael L. Scott	Dynamically Trading Frequency for Complexity in a GALS Microprocessor.	MICRO	2004	DBLP DOI BibTeX RDF
47	Milos Krstic, Eckhard Grass	New GALS Technique for Datapath Architectures.	PATMOS	2003	DBLP DOI BibTeX RDF
46	Jean-Michel Chabloz, Ahmed Hemani	Distributed DVFS using rationally-related frequencies and discrete voltage levels.	ISLPED	2010	DBLP DOI BibTeX RDF	GRLS, DVFS, GALS
46	Tomi Westerlund, Juha Plosila	Time Aware Modelling and Analysis of Multiclocked VLSI Systems.	ICFEM	2006	DBLP DOI BibTeX RDF	Timed Action Systems, formal methods, time, GALS
46	Venkata Syam P. Rapaka, Diana Marculescu	A mixed-clock issue queue design for globally asynchronous, locally synchronous processor cores.	ISLPED	2003	DBLP DOI BibTeX RDF	issue window design, mixed-clock circuits, GALS
46	Joep L. W. Kessels, Suk-Jin Kim, Ad M. G. Peeters, Paul Wielage	Clock Synchronization through Handshake Signalling.	ASYNC	2002	DBLP DOI BibTeX RDF	GALS systems, pausible clocks, asynchronous crossbar/bus, processor/memory architectures
40	Avinash Malik, Zoran A. Salcic, Partha S. Roop	SystemJ compilation using the tandem virtual machine approach.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	SystemJ, compilation, virtual machines, System-level design, esterel
40	Kwang-Ting (Tim) Cheng	Combining synchronous and asynchronous timing schemes for high-performance systems.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	high-performance systems, synchronous, asynchronous, DAC, ITC
40	Daniele Mangano, G. Falconeri, Carlo Pistritto, Alberto Scandurra	Effective full-duplex Mesochronous Link Architecture for Network-on-Chip Data-Link layer.	DSD	2007	DBLP DOI BibTeX RDF
40	Julian J. H. Pontes, Rafael Soares, Ewerson Carvalho, Fernando Moraes 0001, Ney Calazans	SCAFFI: An intrachip FPGA asynchronous interface based on hard macros.	ICCD	2007	DBLP DOI BibTeX RDF
40	Milos Krstic, Eckhard Grass	GALSification of IEEE 802.11a Baseband Processor.	PATMOS	2004	DBLP DOI BibTeX RDF
40	Chia-Chih Kuo, Kuan-Yu Chen	GALs: 基於對抗式學習之整列式摘要法 (GALs: A GAN-based Listwise Summarizer).	ROCLING	2019	DBLP BibTeX RDF
40	Lina Marsso	On Model-based Testing of GALS Systems. (Etude de génération de tests à partir d'un modèle pour les systèmes GALS).		2019	RDF
40	Muhammad Nadeem, HeeJong Park 0001, Zhenmin Li, Morteza Biglari-Abhari, Zoran Salcic	GALS-CMP: Chip-Multiprocessor for GALS Embedded Systems.	ARCS	2013	DBLP DOI BibTeX RDF
40	Wei-Tsun Sun, Zoran Salcic	GALS-Designer: A design framework for GALS software systems.	ACM Trans. Design Autom. Electr. Syst.	2011	DBLP DOI BibTeX RDF
40	Muhammad Nadeem, Morteza Biglari-Abhari, Zoran Salcic	GALS-JOP: A Java Embedded Processor for GALS Reactive Programs.	DASC	2011	DBLP DOI BibTeX RDF
40	Nicolas Coste	Towards Performance Prediction of Compositional Models in GALS Designs. (Vers la prédiction de performance de modèles compositionnels dans les architectures GALS).		2010	RDF
40	Yue Ma 0004	Compositional modeling of globally asynchronous locally synchronous (GALS) architectures in a polychronous model of compotation. (Modélisation compositionnelle d'architectures globalement asynchrones - localement synchrones (GALS) dans un modèle de calcul polychrone).		2010	RDF
39	Rafael Iankowski Soares, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Philippe Maurine, Lionel Torres	A Robust Architectural Approach for Cryptographic Algorithms Using GALS Pipelines.	IEEE Des. Test Comput.	2011	DBLP DOI BibTeX RDF	cryptography attacks, DPA, asynchronous, SCA, GALS, design and test, DEMA
39	Peter Zipf, Heiko Hinkelmann, Adeel Ashraf, Manfred Glesner	A switch architecture and signal synchronization for GALS system-on-chips.	SBCCI	2004	DBLP DOI BibTeX RDF	NoC switch, clock stretching, synchronization, GALS
33	Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla	A Trace-Based Framework for Verifiable GALS Composition of IPs.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
33	Artur L. Sobczyk, Arkadiusz W. Luczyk, Witold A. Pleskacz	Controllable Local Clock Signal Generator for Deep Submicron GALS Architectures.	DDECS	2008	DBLP DOI BibTeX RDF
33	Prashant Dubey, Akhil Garg 0001, Sravan Kumar Bhaskarani	GALS Based Shared Test Architecture for Embedded Memories.	ISCAS	2007	DBLP DOI BibTeX RDF
33	Ümit Y. Ogras, Radu Marculescu, Puru Choudhary, Diana Marculescu	Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip.	DAC	2007	DBLP DOI BibTeX RDF
33	Abbas Sheibanyrad, Alain Greiner	Two Efficient Synchronous Û Asynchronous Converters Well-Suited for Network on Chip in GALS Architectures.	PATMOS	2006	DBLP DOI BibTeX RDF
33	Edith Beigné, Pascal Vivet	Design of On-chip and Off-chip Interfaces for a GALS NoC Architecture.	ASYNC	2006	DBLP DOI BibTeX RDF
33	Joycee Mekie, Supratik Chakraborty, Dinesh K. Sharma, Girish Venkataramani, P. S. Thiagarajan	Interface Design for Rationally Clocked GALS Systems.	ASYNC	2006	DBLP DOI BibTeX RDF
33	Xin Jia, Ranga Vemuri	Studying a GALS FPGA architecture using a parameterized automatic design flow.	ICCAD	2006	DBLP DOI BibTeX RDF
33	Yongkang Zhu, David H. Albonesi	Synergistic temperature and energy management in GALS processor architectures.	ISLPED	2006	DBLP DOI BibTeX RDF	dynamic temperature management (DTM), dynamic voltage scaling (DVS)
33	Swarup Bhunia, Animesh Datta, Nilanjan Banerjee, Kaushik Roy 0001	GAARP: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Asynchronous/synchronous operations, fault tolerance, energy-aware systems, algorithms implemented in hardware
33	Animesh Datta, Swarup Bhunia, Nilanjan Banerjee, Kaushik Roy 0001	A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks.	ISQED	2005	DBLP DOI BibTeX RDF
33	Rostislav (Reuven) Dobkin, Ran Ginosar, Christos P. Sotiriou	Data Synchronization Issues in GALS SoCs.	ASYNC	2004	DBLP DOI BibTeX RDF
33	Greg Semeraro, David H. Albonesi, Grigorios Magklis, Michael L. Scott, Steven G. Dropsho, Sandhya Dwarkadas	Hiding Synchronization Delays in a GALS Processor Microarchitecture.	ASYNC	2004	DBLP DOI BibTeX RDF
33	Joycee Mekie, Supratik Chakraborty, Dinesh K. Sharma	Evaluation of pausible clocking for interfacing high speed IP cores in GALS Framework.	VLSI Design	2004	DBLP DOI BibTeX RDF
33	George S. Taylor, Simon W. Moore, Robert D. Mullins, Peter Robinson 0001	Point to Point GALS Interconnect.	ASYNC	2002	DBLP DOI BibTeX RDF
32	Zhiyi Yu, Michael J. Meeuwsen, Ryan W. Apperson, Omar Sattari, Michael A. Lai, Jeremy W. Webb, Eric W. Work, Tinoosh Mohsenin, Bevan M. Baas	Architecture and Evaluation of an Asynchronous Array of Simple Processors.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	programmable DSP, digital signal processing, DSP, multi-core, array processor, GALS, many-core, chip multi-processor, globally asynchronous locally synchronous
32	Eun-Gu Jung, Jeong-Gun Lee, Kyoung-Son Jhang, Jeong-A Lee, Dong-Soo Har	Asynchronous Layered Interface of Multimedia SoCs for Multiple Outstanding Transactions.	J. VLSI Signal Process.	2007	DBLP DOI BibTeX RDF	multiple outstanding transactions, in-order/out-of-order transaction completion, asynchronous on-chip bus, GALS
32	Dumitru Potop-Butucaru, Benoît Caillaud, Albert Benveniste	Concurrency in Synchronous Systems.	Formal Methods Syst. Des.	2006	DBLP DOI BibTeX RDF	Globally asynchronous locally synchronous (GALS), Concurrency, Synchronous, Distribution, Desynchronization, Trace theory
32	Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli	A Framework for Modeling the Distributed Deployment of Synchronous Designs.	Formal Methods Syst. Des.	2006	DBLP DOI BibTeX RDF	Distributed systems, GALS, Desynchronization, Latency-insensitive design
32	Eun-Gu Jung, Jeong-Gun Lee, Sanghoon Kwak, Kyoung-Sun Jhang, Jeong-A Lee, Dong-Soo Har	High performance asynchronous on-chip bus with multiple issue and out-of-order/in-order completion.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	asynchronous on-chip bus, in-order completion, multiple issue, out-of-order completion, SoC, GALS
27	Sanghamitra Bandyopadhyay, Sriparna Saha 0001	A New Principal Axis Based Line Symmetry Measurement and Its Application to Clustering.	ICONIP (2)	2008	DBLP DOI BibTeX RDF
27	Xin Wang, Tapani Ahonen, Jari Nurmi	Applying CDMA Technique to Network-on-Chip.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
27	Cedric Koch-Hofer, Marc Renaudin, Yvain Thonnart, Pascal Vivet	ASC, a SystemC Extension for Modeling Asynchronous Systems, and Its Application to an Asynchronous NoC.	NOCS	2007	DBLP DOI BibTeX RDF
27	Jhao-Ji Ye, You-Gang Chen, I-Chyn Wey, An-Yeu Wu	Low-Latency Quasi-Synchronous Transmission Technique for Multiple-Clock-Domain IP Modules.	ISCAS	2007	DBLP DOI BibTeX RDF
27	Sonia López, Steve Dropsho, David H. Albonesi, Oscar Garnica, Juan Lanchares	Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches.	HiPEAC	2007	DBLP DOI BibTeX RDF
27	Mahdi Nazm Bojnordi, Nariman Moezzi Madani, Mehdi Semsarzadeh, Ali Afzali-Kusha	An Efficient Clocking Scheme for On-Chip Communications.	APCCAS	2006	DBLP DOI BibTeX RDF
27	Andrew Royal, Peter Y. K. Cheung	Globally Asynchronous Locally Synchronous FPGA Architectures.	FPL	2003	DBLP DOI BibTeX RDF
27	Anoop Iyer, Diana Marculescu	Power efficiency of voltage scaling in multiple clock, multiple voltage cores.	ICCAD	2002	DBLP DOI BibTeX RDF
20	Weiyi Zhang 0003, Zoran Salcic, Avinash Malik	Designing, Modeling and Analysis of GALS Software Systems.	IEEE Trans. Software Eng.	2023	DBLP DOI BibTeX RDF
20	Hitesh Ahuja, Rajkumar Kubendran	High-resolution Extreme-throughput Event-based Cameras using GALS Data-scanning Architecture.	ICONS	2023	DBLP DOI BibTeX RDF
20	Dalta Imam Maulana, Wanyeong Jung	An Energy-Efficient Delay Insensitive Asynchronous Interface for Globally Asynchronous Locally Synchronous (GALS) System.	ISCAS	2023	DBLP DOI BibTeX RDF
20	Alberto Abelló, Panos Vassiliadis, Oscar Romero 0001, Robert Wrembel, Francesca Bugiotti, Johann Gamper, Genoveva Vargas-Solar, Ester Zumpano (eds.)	New Trends in Database and Information Systems - ADBIS 2023 Short Papers, Doctoral Consortium and Workshops: AIDMA, DOING, K-Gals, MADEISD, PeRS, Barcelona, Spain, September 4-7, 2023, Proceedings	ADBIS (Short Papers)	2023	DBLP DOI BibTeX RDF
20	Alexandros Karakasidis 0001, Georgia Koloniari	Exploring Biases for Privacy-Preserving Phonetic Matching.	ADBIS (Short Papers)	2023	DBLP DOI BibTeX RDF
20	Mariella Bonomo, Francesco Ippolito, Salvatore Morfea	A Knowledge Graph to Analyze Clinical Patient Data.	ADBIS (Short Papers)	2023	DBLP DOI BibTeX RDF
20	Sandro Bimonte, Patrick Marcel, Stefano Rizzi	Be High on Emotion: Coping with Emotions and Emotional Intelligence when Querying Data.	ADBIS (Short Papers)	2023	DBLP DOI BibTeX RDF
20	Elodie Escriva, Emmanuel Doumard, Jean-Baptiste Excoffier, Julien Aligon, Paul Monsarrat, Chantal Soulé-Dupuy	Data Exploration Based on Local Attribution Explanation: A Medical Use Case.	ADBIS (Short Papers)	2023	DBLP DOI BibTeX RDF
20	Heloisa Fernanda Rocha, Lorena Silva Nascimento, Leonardo Camargo, Mauricio Noernberg, Carmem S. Hara	Labeling Portuguese Man-of-War Posts Collected from Instagram.	ADBIS (Short Papers)	2023	DBLP DOI BibTeX RDF
20	Hacene Belhadef, Hala Benchiheb, Lynda Lebdjiri	Exploring the Capabilities and Limitations of VQC and QSVC for Sentiment Analysis on Real-World and Synthetic Datasets.	ADBIS (Short Papers)	2023	DBLP DOI BibTeX RDF
20	Quim Motger, Xavier Franch, Jordi Marco	Mobile Feature-Oriented Knowledge Base Generation Using Knowledge Graphs.	ADBIS (Short Papers)	2023	DBLP DOI BibTeX RDF
20	Yousra Bouakba, Hacene Belhadef	Ensemble Learning Based Quantum Text Classifiers.	ADBIS (Short Papers)	2023	DBLP DOI BibTeX RDF
20	Joakim Lindén, Håkan Forsberg, Masoud Daneshtalab, Ingemar Söderquist	Evaluating the Robustness of ML Models to Out-of-Distribution Data Through Similarity Analysis.	ADBIS (Short Papers)	2023	DBLP DOI BibTeX RDF
20	Søren Kejser Jensen, Christian Thomsen 0001	Holistic Analytics of Sensor Data from Renewable Energy Sources: A Vision Paper.	ADBIS (Short Papers)	2023	DBLP DOI BibTeX RDF