Search results for "Guardband"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
237	Kwangok Jeong, Andrew B. Kahng, Kambiz Samadi	Quantified Impacts of Guardband Reduction on Design Process Outcomes.	ISQED	2008	DBLP DOI BibTeX RDF	Guardband, chip size, yield, runtime, wirelength, design iterations
84	Chin-Te Kao, Sam Wu, Jwu E. Chen	A case study of failure analysis and guardband determination for a 64M-bit DRAM.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	guardband determination, prevention strategy, test derivation, test cost, 64 Mbit, integrated circuit testing, yield, DRAM, failure analysis, failure analysis, test selection, DRAM chips, product quality, integrated circuit yield, integrated circuit economics
73	Mill-Jer Wang, R.-L. Jiang, J.-W. Hsia, Chih-Hu Wang, Jwu E. Chen	Guardband Determination for the Detection of Off-State and Junction Leakages in DRAM Testing.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
65	Taniya Siddiqua, Sudhanva Gurumurthi	A multi-level approach to reduce the impact of NBTI on processor functional units.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	reliability, NBTI
44	Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De	Resilient microprocessor design for high performance & energy efficiency.	ISLPED	2010	DBLP DOI BibTeX RDF	resilient design
30	Natalia Lylina, Stefan Holst, Hanieh Jafarzadeh, Alexandra Kourfali, Hans-Joachim Wunderlich	Guardband Optimization for the Preconditioned Conjugate Gradient Algorithm.	DSN-W	2023	DBLP DOI BibTeX RDF
30	Xi Chen, Jiaxiang Feng, Aly Shoukry, Xin Zhang, Raveesh Magod, Nachiket V. Desai, Jie Gu 0001	Proactive Power Regulation with Real-time Prediction and Fast Response Guardband for Fine-grained Dynamic Voltage Droop Mitigation on Digital SoCs.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
30	Johannes W. Farias, Diego V. Cirilo do Nascimento, Tiago Barros, Samuel Xavier de Souza	Speculative guardband: exploiting critical-delay variations across cached instructions.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
30	Heba Khdr, Hussam Amrouch, Jörg Henkel	Dynamic Guardband Selection: Thermal-Aware Optimization for Unreliable Multi-Core Systems.	IEEE Trans. Computers	2019	DBLP DOI BibTeX RDF
30	Andres F. Gomez, Víctor H. Champac	An Efficient Metric-Guided Gate Sizing Methodology for Guardband Reduction Under Process Variations and Aging Effects.	J. Electron. Test.	2019	DBLP DOI BibTeX RDF
30	Ioannis Stratakos, Konstantinos Maragos 0001, George Lentaris	Voltage Scaling and Guardband Customization of Multiple Constituent Components in SoC-FPGA.	PATMOS	2019	DBLP DOI BibTeX RDF
30	Hyungjin Kim, Seong Chul Cho, Youngha Lee	Interference Analysis of Guardband NB-IoT System.	ICTC	2018	DBLP DOI BibTeX RDF
30	Andres F. Gomez, Roberto Gómez 0001, Víctor H. Champac	A metric-guided gate-sizing methodology for aging guardband reduction.	LATS	2018	DBLP DOI BibTeX RDF
30	Hitoshi Takeshita, Takefumi Oguma, Shinsuke Fujisawa, Baku Yatabe, Yuta Suzuki, Akio Tajima, Emmanuel Le Taillandier de Gabory	Optical Node with Passband Overlapped Filter and Impairment Aware Least Slot Count Path First Algorithm for Guardband-Less Elastic Optical Network.	ECOC	2017	DBLP DOI BibTeX RDF
30	Po-Hao Wang, Wei-Chung Cheng, Yung-Hui Yu, Tang-Chieh Kao, Chi-Lun Tsai, Pei-Yao Chang, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen	Zero-Counting and Adaptive-Latency Cache Using a Voltage-Guardband Breakthrough for Energy-Efficient Operations.	IEEE Trans. Circuits Syst. II Express Briefs	2016	DBLP DOI BibTeX RDF
30	Samantak Gangopadhyay, Saad Bin Nasir, A. Subramanian, Visvesh Sathe 0001, Arijit Raychowdhury	UVFR: A Unified Voltage and Frequency Regulator with 500MHz/0.84V to 100KHz/0.27V operating range, 99.4% current efficiency and 27% supply guardband reduction.	ESSCIRC	2016	DBLP DOI BibTeX RDF
30	Jiansong Zhang, Jin Zhang 0001, Kun Tan, Lin Yang 0009, Qian Zhang 0001, Yongguang Zhang	Turning Waste into Wealth: Enabling Communication in Guardband Whitespace.	MobiHoc	2015	DBLP DOI BibTeX RDF
30	Yazhou Zu, Charles R. Lefurgy, Jingwen Leng, Matthew Halpern, Michael S. Floyd, Vijay Janapa Reddi	Adaptive guardband scheduling to improve system-level efficiency of the POWER7+.	MICRO	2015	DBLP DOI BibTeX RDF
30	Mohammad Saber Golanbari, Saman Kiamehr, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori	Aging guardband reduction through selective flip-flop optimization.	ETS	2015	DBLP DOI BibTeX RDF
30	Jian Luo 0001, Andreas Kortke, Wilhelm Keusgen	Guardband Optimization for Cellular Systems Applying Raised Cosine Windowed OFDM.	Wirel. Pers. Commun.	2014	DBLP DOI BibTeX RDF
30	Charles Lefurgy, Alan J. Drake, Michael S. Floyd, Malcolm Allen-Ware, Bishop Brock, José A. Tierno, John B. Carter, Robert W. Berry	Active Guardband Management in Power7+ to Save Energy and Maintain Reliability.	IEEE Micro	2013	DBLP DOI BibTeX RDF
30	Charles Lefurgy, Alan J. Drake, Michael S. Floyd, Malcolm Allen-Ware, Bishop Brock, José A. Tierno, John B. Carter	Active management of timing guardband to save energy in POWER7.	MICRO	2011	DBLP DOI BibTeX RDF
30	Michitarou Yabuuchi, Kazutoshi Kobayashi	Evaluation of FPGA design guardband caused by inhomogeneous NBTI degradation considering process variations.	FPT	2010	DBLP DOI BibTeX RDF
30	Jian Luo 0001, Wilhelm Keusgen, Andreas Kortke	Optimization of Time Domain Windowing and Guardband Size for Cellular OFDM Systems.	VTC Fall	2008	DBLP DOI BibTeX RDF
30	Henry H. Y. Chan, Zeljko Zilic	A practical substrate modeling algorithm with active guardband macromodel for mixed-signal substrate coupling verification.	ICECS	2001	DBLP DOI BibTeX RDF
30	Richard H. Williams, Charles F. Hawkins	The Economics of Guardband Placement.	ITC	1993	DBLP DOI BibTeX RDF
22	Kwangok Jeong, Andrew B. Kahng	Timing analysis and optimization implications of bimodal CD distribution in double patterning lithography.	ASP-DAC	2009	DBLP DOI BibTeX RDF
22	Wei Hou, Lei Yang 0020, Lin Zhang 0001, Xiuming Shan, Heather Zheng	Understanding cross-band interference in unsynchronized spectrum access.	CoRoNet@MobiCom	2009	DBLP DOI BibTeX RDF	spectrum access, interference, cognitive radios
22	Keith A. Bowman, James W. Tschanz, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek De, Shekhar Y. Borkar	Circuit techniques for dynamic variation tolerance.	DAC	2009	DBLP DOI BibTeX RDF	dynamic variations, error-detection sequential, replica paths, resilient circuits, variation sensors, variation-tolerant circuits, error detection, error correction, error recovery, parameter variations, timing errors
22	Andrew B. Kahng	How to get real mad.	ISPD	2008	DBLP DOI BibTeX RDF	design-aware manufacturing, integrated circuit physical design, manufacturing-aware design, performance analysis, design for manufacturability
22	Wenping Wang, Zile Wei, Shengqi Yang, Yu Cao 0001	An efficient method to identify critical gates under circuit aging.	ICCAD	2007	DBLP DOI BibTeX RDF
22	Steven M. Burns, Mahesh Ketkar, Noel Menezes, Keith A. Bowman, James W. Tschanz, Vivek De	Comparative Analysis of Conventional and Statistical Design Techniques.	DAC	2007	DBLP DOI BibTeX RDF
22	Kenta Yamada, Noriaki Oda	Statistical corner conditions of interconnect delay (corner LPE specifications).	ASP-DAC	2006	DBLP DOI BibTeX RDF