Search results for "Handel-C"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
80	Andrew Butterfield, Jim Woodcock 0001	prialt in Handel-C: an operational semantics.	Int. J. Softw. Tools Technol. Transf.	2005	DBLP DOI BibTeX RDF	Operational semantics, Priority, Handel-C
68	Ali E. Abdallah, John Hawkins	Formal Behavioural Synthesis of Handel-C Parallel Hardware Implementations from Functional Specifications.	HICSS	2003	DBLP DOI BibTeX RDF
61	Tomas Dedek, Tomas Marek, Tomás Martínek	High Level Abstraction Language as an Alternative to Embedded Processors for Internet Packet Processing in FPGA.	FPL	2007	DBLP DOI BibTeX RDF
61	Salvatore Vitabile, Antonio Gentile, Sabato Marco Siniscalchi, Filippo Sorbello	Efficient Rapid Prototyping of Image and Video Processing Algorithms.	DSD	2004	DBLP DOI BibTeX RDF
53	Kasra G. Nezami, Peter W. Stephens, Stuart D. Walker	Handel-C Implementation of Early-Access Partial-Reconfiguration for Software Defined Radio.	WCNC	2008	DBLP DOI BibTeX RDF
53	Andrew Butterfield	A Denotational Semantics for Handel-C.	Formal Methods and Hybrid Real-Time Systems	2007	DBLP DOI BibTeX RDF
53	Slawomir Cichon, Marek Gorgon, Miroslaw Pac	Handel-C Design Enhancement for FPGA-Based DV Decoder.	ARC	2006	DBLP DOI BibTeX RDF	video decompression, field programmable gate array, Parallel algorithm, high level languages
46	Ould-cheikh Mourad, Si-Mohamed Lotfy, Noureddine Mehallegue, Ahmed Bouridane, Camel Tanougast	AES Embedded Hardware Implementation.	AHS	2007	DBLP DOI BibTeX RDF
46	Tim Todman, Wayne Luk	Real-time Extensions to a C-like Hardware Description Language.	FCCM	2003	DBLP DOI BibTeX RDF
42	Server Kasap, Khaled Benkrid, Ying Liu 0003	A high performance fpga-based implementation of position specific iterated blast.	FPGA	2009	DBLP DOI BibTeX RDF	psi-blast, fpga, blast, handel c
42	Marcel Oliveira, Jim Woodcock 0001	Automatic Generation of Verified Concurrent Hardware.	ICFEM	2007	DBLP DOI BibTeX RDF	FPGA, concurrency, refinement, CSP, tool support, program development, Handel-C, automatic compilation
38	Joseph C. Libby, Farnaz Gharibian, Kenneth B. Kent	Automatic Identification of Parallelism in Handel-C.	DSD	2008	DBLP DOI BibTeX RDF
38	Farnaz Gharibian, Kenneth B. Kent	An embedded decryption/decompression engine using Handel-C.	SIES	2008	DBLP DOI BibTeX RDF
38	Juan Ignacio Perna, Jim Woodcock 0001	A Denotational Semantics for Handel-C Hardware Compilation.	ICFEM	2007	DBLP DOI BibTeX RDF
38	Miroslaw Jablonski, Marek Gorgon	Handel-C implementation of Classical Component Labelling Algorithm.	DSD	2004	DBLP DOI BibTeX RDF
38	Klaus Buchenrieder, Andreas Pyttel, Alexander Sedlmeier	A Powerful System Design Methodology Combining OCAPI and Handel-C for Concept Engineering.	DATE	2002	DBLP DOI BibTeX RDF
38	Peter Martin	A Pipelined Hardware Implementation of Genetic Programming Using FPGAs and Handel-C.	EuroGP	2002	DBLP DOI BibTeX RDF
30	Timothy F. Beatty, Eric E. Aubanel, Kenneth B. Kent	Customizable bit-width in an OpenMP-based circuit design tool.	FPGA	2009	DBLP DOI BibTeX RDF	handelc, hardware specification, openmp
30	Issam W. Damaj	Higher-Level Hardware Synthesis of the KASUMI Algorithm.	J. Comput. Sci. Technol.	2007	DBLP DOI BibTeX RDF	parallel algorithms, methodology, formal models, data encryption, gate array
30	Iouliia Skliarova	Intelligent Systems Engineering with Reconfigurable Computing.	IFIP PPAI	2006	DBLP DOI BibTeX RDF
30	Kieron Turkington, Konstantinos Masselos, George A. Constantinides, Philip Heng Wai Leong	FPGA Based Acceleration of the Linpack Benchmark: A High Level Code Transformation Approach.	FPL	2006	DBLP DOI BibTeX RDF
30	Miguel Morales-Sandoval, Claudia Feregrino Uribe	On the Hardware Design of an Elliptic Curve Cryptosystem.	ENC	2004	DBLP DOI BibTeX RDF
27	Shrutisagar Chandrasekaran, Abbes Amira	High Performance FPGA Implementation of the Mersenne Twister.	DELTA	2008	DBLP DOI BibTeX RDF	RC1000, FPGA, Mersenne Twister, Handel C
27	Justin L. Tripp, Maya B. Gokhale, Kristopher D. Peterson	Trident: From High-Level Language to Hardware Circuitry.	Computer	2007	DBLP DOI BibTeX RDF	Trident compiler, Impulse C, Mitrion-C, SRC Carte, RC Toolbox, FPGAs, reconfigurable computing, Supercomputing, Handel-C
23	Ahmed B. Ablak, Issam W. Damaj	HTCC: Haskell to Handel-C Compiler.	CoRR	2019	DBLP BibTeX RDF
23	Ahmed B. Ablak, Issam W. Damaj	HTCC: Haskell to Handel-C Hardware Compiler.	DSD	2016	DBLP DOI BibTeX RDF
23	David J. Greaves	Layering RTL, SAFL, Handel-C and Bluespec constructs on Chisel HCL.	MEMOCODE	2015	DBLP DOI BibTeX RDF
23	Yujian Fu, Jeffery Kulick, Lok K. Yan, Steven Drager 0001	Formal Modeling and Verification of Security Property in Handel C Program.	Int. J. Secur. Softw. Eng.	2012	DBLP DOI BibTeX RDF
23	Maxwell Walton, Omar Ahmed, Gary William Grewal, Shawki Areibi	An Empirical Investigation on System and Statement Level Parallelism Strategies for Accelerating Scatter Search Using Handel-C and Impulse-C.	VLSI Design	2012	DBLP DOI BibTeX RDF
23	Juan Ignacio Perna, Jim Woodcock 0001	Mechanised wire-wise verification of Handel-C synthesis.	Sci. Comput. Program.	2012	DBLP DOI BibTeX RDF
23	Alex Cole	Handel-C++ - Adding Syntactic Support to C++.	CPA	2012	DBLP BibTeX RDF
23	Andrew Butterfield	A denotational semantics for Handel-C.	Formal Aspects Comput.	2011	DBLP DOI BibTeX RDF
23	Jia Jan Ong, Li-Minn Ang, Kah Phooi Seng, Fong Tien Ong	Implementation of (255, 251) Reed Solomon Minimal Instruction Set Computing using Handel-C.	ICOIN	2011	DBLP DOI BibTeX RDF
23	Dan Slipper, Alistair A. McEwan	A Systems Re-engineering Case Study: Programming Robots with occam and Handel-C.	CPA	2011	DBLP DOI BibTeX RDF
23	Wilson Ifill, Steve A. Schneider	A step towards refining and translating B control annotations to Handel-C.	Concurr. Comput. Pract. Exp.	2010	DBLP DOI BibTeX RDF
23	Lars Middendorf, Christophe Bobda	Declarative Programming with Handel-C.	ERSA	2010	DBLP BibTeX RDF
23	Juan Ignacio Perna	A verified compiler for Handel-C.		2010	RDF
23	Cherrad Benbouchama, Mohamed Tadjine, Ahmed Bouridane	A Parameterizable Handel-C Neural Network Implementation for FPGA.	ICINCO-ICSO	2009	DBLP BibTeX RDF
23	Yi Yang, Qian-Sheng Fang	The improved genetic algorithm for solving knapsack problem based on Handel-C.	GrC	2009	DBLP DOI BibTeX RDF
23	Juan Ignacio Perna, Jim Woodcock 0001	Mechanised Wire-wise Verification of Handel-C Synthesis.	SBMF	2008	DBLP DOI BibTeX RDF
23	Juan Ignacio Perna, Jim Woodcock 0001	UTP Semantics for Handel-C.	UTP	2008	DBLP DOI BibTeX RDF
23	Steve A. Schneider, Helen Treharne, Alistair A. McEwan, Wilson Ifill	Experiments in Translating CSP \|\| B to Handel-C.	CPA	2008	DBLP DOI BibTeX RDF
23	José M. Granado Criado, Miguel A. Vega-Rodríguez, Juan Manuel Sánchez-Pérez, Juan Antonio Gómez Pulido	A Dynamically and Partially Reconfigurable Implementation of the IDEA Algorithm Using FPGAs and Handel-C.	J. Univers. Comput. Sci.	2007	DBLP DOI BibTeX RDF
23	Qian-Sheng Fang, Yi Yang, Wan-Li Chen, Li-jun Wang	Implementation and Research on EHW-based Digital Chip Using Handel-C Language.	ICNC (5)	2007	DBLP DOI BibTeX RDF
23	Wilson Ifill, Steve A. Schneider	A Step Towards Refining and Translating B Control Annotations to Handel-C.	CPA	2007	DBLP BibTeX RDF
23	Vijay Pandya, Shawki Areibi, Medhat Moussa	A Handel-C implementation of the back-propagation algorithm on field programmable gate arrays.	ReConFig	2005	DBLP DOI BibTeX RDF
23	Marek Gorgon, Slawomir Cichon, Miroslaw Pac	Real-time Handel-C Based Implementation of DV Decoder.	FPL	2005	DBLP DOI BibTeX RDF
23	Bart Rem, Ajeesh Gopalakrishnan, Tom J. H. Geelen, Herman W. Roebbers	Automatic Handel-C Generation from MATLAB.	CPA	2005	DBLP BibTeX RDF
23	Andrew Butterfield, Jim Woodcock 0001	A "Hardware Compiler" Semantics for Handel-C.	MFCSIT	2004	DBLP DOI BibTeX RDF
23	Robert P. Self, Martin Fleury, Andy C. Downton	Design methodology for construction of asynchronous pipelines with Handel-C.	IEE Proc. Softw.	2003	DBLP DOI BibTeX RDF
23	Andrew Butterfield, Jim Woodcock 0001	An Operational Semantics for Handel-C.	FMICS	2003	DBLP DOI BibTeX RDF
23	Andrew Butterfield, Jim Woodcock 0001	Semantic domains for Handel-C.	MFCSIT	2002	DBLP DOI BibTeX RDF
23	Peter Martin, Riccardo Poli	Crossover Operators For A Hardware Implementation Of GP Using FPGAs And Handel-C.	GECCO	2002	DBLP BibTeX RDF
23	Peter Martin	An Analysis Of Random Number Generators For A Hardware Implementation Of Genetic Programming Using FPGAs And Handel-C.	GECCO	2002	DBLP BibTeX RDF
23	Peter Martin	A Hardware Implementation of a Genetic Programming System Using FPGAs and Handel-C.	Genet. Program. Evolvable Mach.	2001	DBLP DOI BibTeX RDF
23	Kjell Torkelsson, Johan Ditmar	Header Compression in Handel-C - An Internet Application and a New Design Language.	DSD	2001	DBLP DOI BibTeX RDF
15	Maxwell Walton, Gary Gréwal, Gerarda A. Darlington	Parallel FPGA-based implementation of scatter search.	GECCO	2010	DBLP DOI BibTeX RDF	0-1 knapsack problem, field programmable gate arrays, pipelining, hardware acceleration, data parallelism, scatter search
15	Raúl Martínez, Francisco José Alfaro, José L. Sánchez 0002, José M. Claver	Hardware Implementation Study of the SCFQ-CA and DRR-CA Scheduling Algorithms.	Euro-Par	2009	DBLP DOI BibTeX RDF
15	Pramod Kumar Meher, Shrutisagar Chandrasekaran, Abbes Amira	FPGA Realization of FIR Filters by Efficient and Flexible Systolization Using Distributed Arithmetic.	IEEE Trans. Signal Process.	2008	DBLP DOI BibTeX RDF
15	Markus Koester, Wayne Luk, Geoffrey Brown	A hardware compilation flow for instance-specific VLIW cores.	FPL	2008	DBLP DOI BibTeX RDF
15	Amir Hormati, Manjunath Kudlur, Scott A. Mahlke, David F. Bacon, Rodric M. Rabbah	Optimus: efficient realization of streaming applications on FPGAs.	CASES	2008	DBLP DOI BibTeX RDF	optimization, FPGA, embedded systems, compiler, streaming, heterogeneous
15	Fernando Pardo, Paula López Martinez 0001, Diego Cabello	FPGA-based hardware accelerator of the heat equation with applications on infrared thermography.	ASAP	2008	DBLP DOI BibTeX RDF
15	Issam W. Damaj	Parallel Algorithms Development for Programmable Devices with Application from Cryptography.	Int. J. Parallel Program.	2007	DBLP DOI BibTeX RDF	Parallel algorithms, methodologies, formal models, data encryption, gate array
15	Takamasa Kanamori, Hideharu Amano, Masatoshi Arai, Daisuke Konno, Tomomichi Nanba, Yoshiaki Ajioka	Implementation and Evaluation of a High Speed License Plate Recognition System on an FPGA.	CIT	2007	DBLP DOI BibTeX RDF
15	Fernando Pardo, Paula López 0001, Diego Cabello	Soft-Hard 3D FD-TD Solver for Non Destructive Evaluation.	FPL	2007	DBLP DOI BibTeX RDF
15	Gareth W. Morris, Matthew Aubury	Design Space Exploration of the European Option Benchmark Using HyperStreams.	FPL	2007	DBLP DOI BibTeX RDF
15	Takamasa Kanamori, Hideharu Amano, Masatoshi Arai, Daisuke Konno, Tomomichi Nanba, Yoshiaki Ajioka	A High Speed License Plate Recognition System on an FPGA.	FPL	2007	DBLP DOI BibTeX RDF
15	Khaled Benkrid, Ying Liu 0003, Abdsamad Benkrid	Design and Implementation of a Highly Parameterised FPGA-Based Skeleton for Pairwise Biological Sequence Alignment.	FCCM	2007	DBLP DOI BibTeX RDF
15	J. Javier Martínez-Álvarez, F. Javier Toledo-Moreo, José Manuel Ferrández de Vicente	Discrete-Time Cellular Neural Networks in FPGA.	FCCM	2007	DBLP DOI BibTeX RDF
15	Juan Antonio Gómez Pulido, Juan M. Matas-Santiago, Francisco Pérez-Rodríguez, Miguel A. Vega-Rodríguez, Juan Manuel Sánchez-Pérez, Francisco Fernández de Vega	Hardware Modelling of Cellular Automata: The Game of Life Case.	EUROCAST	2007	DBLP DOI BibTeX RDF	FPGA, Cellular Automata, Reconfigurable Computing
15	Alistair A. McEwan, Steve A. Schneider	A verified development of hardware using CSP∥B.	MEMOCODE	2006	DBLP DOI BibTeX RDF
15	Shrutisagar Chandrasekaran, Abbes Amira	FPGA Implementation and Power Modelling of the Fast Walsh Transform.	FPL	2006	DBLP DOI BibTeX RDF
15	David Rodríguez 0001, Juan M. Sánchez, Arturo Duran	Mobile Fingerprint Identification Using a Hardware Accelerated Biometric Service Provider.	ARC	2006	DBLP DOI BibTeX RDF
15	Neil C. Audsley, Michael Ward	Syntax-driven implementation of software programming language control constructs and expressions on FPGAs.	CASES	2006	DBLP DOI BibTeX RDF	fpga, compilation, language
15	Tim Schattkowsky, Jan Hendrik Hausmann, Gregor Engels	Using UML Activities for System-on-Chip Design and Synthesis.	MoDELS	2006	DBLP DOI BibTeX RDF
15	Sergio A. Cuenca, António S. Câmara, Juan Suardíaz Muro, Ana Toledo Moreo	Domain-Specific Codesign for Automated Visual Inspection Systems.	IbPRIA (1)	2005	DBLP DOI BibTeX RDF
15	Khaled Benkrid, Samir Belkacemi	An integrated framework for the high level design of high performance signal processing circuits on FPGAs (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
15	Owen Callanan, Andy Nisbet, Emre Özer 0001, James Sexton, David Gregg	FPGA Implementation of a Lattice Quantum Chromodynamics Algorithm Using Logarithmic Arithmetic.	IPDPS	2005	DBLP DOI BibTeX RDF
15	Aziz Ahmedsaid, Abbes Amira	Accelerating svd on reconficurable hardware for image denoising.	ICIP	2004	DBLP DOI BibTeX RDF
15	S. Sukhsawas, Khaled Benkrid	A High-Level Implementation of a High Performance Pipeline FFT on Virtex-E FPGAs.	ISVLSI	2004	DBLP DOI BibTeX RDF
15	Aziz Ahmedsaid, Abbes Amira, Ahmed Bouridane	Accelerating MUSIC method on reconfigurable hardware for source localisation.	ISCAS (3)	2004	DBLP DOI BibTeX RDF
15	Khaled Benkrid, S. Sukhsawas, Danny Crookes, Samir Belkacemi	A single-FPGA implementation of image connected component labelling.	FPGA	2003	DBLP DOI BibTeX RDF
15	Khaled Benkrid, S. Sukhsawas, Danny Crookes, Abdsamad Benkrid	An FPGA-Based Image Connected Component Labeller.	FPL	2003	DBLP DOI BibTeX RDF
15	Jun Jiang, Wayne Luk, Daniel Rueckert	FPGA-Based Computation of Free-Form Deformations.	FPL	2003	DBLP DOI BibTeX RDF
15	Miroslav Lícko, Jan Schier, Milan Tichý, Markus Kühl	MATLAB/Simulink Based Methodology for Rapid-FPGA-Prototyping.	FPL	2003	DBLP DOI BibTeX RDF
15	Eva M. Ortigosa, Pilar Martínez Ortigosa, Antonio Cañas, Eduardo Ros 0001, Rodrigo Agís, Julio Ortega 0001	FPGA Implemenation of Multi-layer Perceptrons for Speech Recognition.	FPL	2003	DBLP DOI BibTeX RDF
15	David Rodríguez Lozano, Juan Manuel Sánchez-Pérez, Juan Antonio Gómez Pulido	Reconfigurable Hybrid Architecture for Web Applications.	FPL	2003	DBLP DOI BibTeX RDF
15	Tim Todman, Wayne Luk	Combining Imperative and Declarative Hardware Descriptions.	HICSS	2003	DBLP DOI BibTeX RDF
15	Martyn Edwards, Benjamin Fozard	Rapid Prototyping of Mixed Hardware and Software Systems.	DSD	2002	DBLP DOI BibTeX RDF
15	Klaus Buchenrieder, Ulrich Nageldinger, Andreas Pyttel, Alexander Sedlmeier	Integration of Reconfigurable Hardware into System-Level Design.	FPL	2002	DBLP DOI BibTeX RDF
15	John Hawkins, Ali E. Abdallah	An Overview of Systematic Development of Parallel Systems for Reconfigurable Hardware (Research Note).	Euro-Par	2002	DBLP DOI BibTeX RDF
15	Henry Styles, Wayne Luk	Accelerating Radiosity Calculations Using Reconfigurable Platforms.	FCCM	2002	DBLP DOI BibTeX RDF
15	Klaus Buchenrieder, Ulrich Nageldinger, Andreas Pyttel, Alexander Sedlmeier	System Prototyping by Integration of Reconfigurable Hardware into a Heterogeneous System Model.	IEEE International Workshop on Rapid System Prototyping	2002	DBLP DOI BibTeX RDF
15	Peter McCurry, Fearghal Morgan, Liam Kilmartin	Xilinx FPGA implementation of an image classifier for object detection applications.	ICIP (3)	2001	DBLP DOI BibTeX RDF
15	Jim Woodcock 0001, Ana Cavalcanti 0001	The Steam Boiler in a Unified Theory of Z and CSP.	APSEC	2001	DBLP DOI BibTeX RDF
15	Milan Vasilko, Lukas Machácek, Marek Matej, Piotr Stepien, Steve Holloway	A Rapid Prototyping Methodology and Platform for Seamless Communication Systems.	IEEE International Workshop on Rapid System Prototyping	2001	DBLP DOI BibTeX RDF
15	Henry Styles, Wayne Luk	Customizing Graphics Applications: Techniques and Programming Interface.	FCCM	2000	DBLP DOI BibTeX RDF