|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 2160 occurrences of 1221 keywords
|
|
|
Results
Found 3233 publication records. Showing 3231 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
89 | James A. Lupo |
Benchmarking UHGROMOS. |
HICSS (5) |
1995 |
DBLP DOI BibTeX RDF |
GROMOS, parallel Fortran preprocessor, Pfortran, Intel Corporation, IBM Corporation, massively parallel processor machines, Intel iPSC/860, Caltech Intel DELTA, IBM SP1, UHGROMOS molecular dynamics program, test application, parallel performance analysis, parallel programming, benchmarking, FORTRAN, parallel machines, parallel machines, software performance evaluation, physics, parallel languages, software portability, physics computing, porting, Intel Paragon, program processors, molecular dynamics method |
60 | Subhash Saini, Andrey Naraikin, Rupak Biswas, David Barkai, Timothy Sandstrom |
Early performance evaluation of a "Nehalem" cluster using scientific and engineering applications. |
SC |
2009 |
DBLP DOI BibTeX RDF |
|
59 | Corporate Intel |
The Intel iPSC/2 system: the concurrent supercomputer for production applications. |
C³P |
1988 |
DBLP DOI BibTeX RDF |
|
53 | Alexander Kalinkin, Yuri M. Laevsky, Sergey Gololobov |
2D Fast Poisson Solver for High-Performance Computing. |
PaCT |
2009 |
DBLP DOI BibTeX RDF |
|
52 | Ken Wagner, Patrick P. Gelsinger |
Driving the $5 Billion Innovation Engine at Intel: An Interview with Patrick P. Gelsinger, Digital Enterprise Group Senior Vice President and General Manager, Intel. |
IEEE Des. Test Comput. |
2005 |
DBLP DOI BibTeX RDF |
|
50 | Alan R. Shealy, Brian A. Malloy, David A. Sykes |
SIMx86: An extensible simulator for the Intel 80×86 processor family. |
Annual Simulation Symposium |
1997 |
DBLP DOI BibTeX RDF |
SIMx86, extensible simulator, Intel 80/spl times/86, Intel 8088 processor, 8086 processor, debugging facilities, simulator construction, virtual machines, domain model, performance gains, processor simulators |
48 | Zbigniew Stachniak |
Intel SIM8-01: A Proto-PC. |
IEEE Ann. Hist. Comput. |
2007 |
DBLP DOI BibTeX RDF |
microprocessor development system, Intel 8008, personal computer, microcomputer |
47 | Intel Corporation |
Pioneering and continuing contributions to the semiconductor industry. The Franklin Institute's 2002 Bower Award for business leadership presented to Gordon E. Moore. |
J. Frankl. Inst. |
2003 |
DBLP DOI BibTeX RDF |
|
46 | Pawel Gepner, David L. Fraser, Michal Filip Kowalik |
Second Generation Quad-Core Intel Xeon Processors Bring 45 nm Technology and a New Level of Performance to HPC Applications. |
ICCS (1) |
2008 |
DBLP DOI BibTeX RDF |
quad-core processors, parallel processing, benchmarks, HPC, multi-core processors |
46 | Michael Wolfe |
Software tools I - AMD versus Intel: the compiler as referee. |
SC |
2006 |
DBLP DOI BibTeX RDF |
|
46 | Dana Plautz |
A look at Intel's research council funding in sensor networks for feature film production and interactive drama. |
Comput. Entertain. |
2004 |
DBLP DOI BibTeX RDF |
film production, networks, artificial intelligence, arts, digital media, interactive drama, theatre |
46 | Xinmin Tian, Yen-Kuang Chen, Milind Girkar, Steven Ge, Rainer Lienhart, Sanjiv Shah |
Exploring the Use of Hyper-Threading Technology for Multimedia Applications with Intel® OpenMP* Compiler. |
IPDPS |
2003 |
DBLP DOI BibTeX RDF |
Hyper-Threading technology, multimedia algorithm, parallelization, OpenMP, compiler optimization |
45 | Chih Jeng Kenneth Tan, David Hagan, Matthew F. Dixon |
A Performance Comparison of Matrix Solvers on Compaq Alpha, Intel Itanium, and Intel Itanium II Processors. |
ICCSA (1) |
2003 |
DBLP DOI BibTeX RDF |
Systems of linear algebraic equations, Architecture specific tuning, Linear solver |
44 | Zhiwei Xu, Kai Hwang 0001 |
MPPs and clusters for scalable computing. |
ISPAN |
1996 |
DBLP DOI BibTeX RDF |
scalable parallel computing, Cray T3D/T3E, ASCI TeraFLOPS, performance evaluation, scalability, parallel architectures, reconfigurable architectures, clusters of workstations, Intel Paragon, Intel, massively parallel processors, performance attributes, scalable computing, MPPs, IBM SP2 |
44 | Philip J. Hatcher, Michael J. Quinn, Anthony J. Lapadula, Bradley K. Seevers, Ray J. Anderson, Robert R. Jones |
Data-Parallel Programming on MIMD Computers. |
IEEE Trans. Parallel Distributed Syst. |
1991 |
DBLP DOI BibTeX RDF |
data-parallel programming language Dataparallel C, nCUBE hypercubemulticomputers, Sequent multiprocessors, Dataparallel C programs, Intel iPSC/2, nCUBE 3200, Sequent Symmetry, hypercubenetworks, parallel programming, compilers, program compilers, parallel languages, speedups, execution times, C language, Intel |
41 | Graham Schelle, Jamison D. Collins, Ethan Schuchman, Perry H. Wang, Xiang Zou, Gautham N. Chinya, Ralf Plate, Thorsten Mattner, Franz Olbrich, Per Hammarlund, Ronak Singhal, Jim Brayton, Sebastian Steibl, Hong Wang 0003 |
Intel nehalem processor core made FPGA synthesizable. |
FPGA |
2010 |
DBLP DOI BibTeX RDF |
intel nehalem, synthesizable core, fpga, emulator |
41 | Matthew Henricksen, Ed Dawson |
Ensuring Fast Implementations of Symmetric Ciphers on the Intel Pentium 4 and Beyond. |
ACISP |
2006 |
DBLP DOI BibTeX RDF |
Intel Pentium 4, Dragon, HC-256, MAG, Mir-1, Py, Implementation, Stream cipher, RC4 |
41 | Soon Myoung Chung, Arindam Chatterjee |
Parallel Distributive Join Algorithm on the Intel Paragon. |
J. Supercomput. |
1999 |
DBLP DOI BibTeX RDF |
Hybrid-hash join, Performance analysis, Parallel processing, Intel Paragon, Distributive join |
41 | Soon Myoung Chung, Arindam Chatterjee |
Performance Analysis of a Parallel Distributive Join Algorithm on the Intel Paragon. |
ICPADS |
1997 |
DBLP DOI BibTeX RDF |
Hybrid Hash join, Parallel Processing, Intel Paragon, Distributive join |
40 | Shreekant (Ticky) Thakkar |
Battery life challenges on future mobile notebook platforms. |
ISLPED |
2004 |
DBLP DOI BibTeX RDF |
|
40 | Xinmin Tian, Milind Girkar, Sanjiv Shah, Douglas Armstrong, Ernesto Su, Paul Petersen |
Compiler and Runtime Support for Running OpenMP Programs on Pentium-and Itanium-Architectures. |
HIPS |
2003 |
DBLP DOI BibTeX RDF |
Hyper-Threading technology, Parallelization, OpenMP, compiler optimization, shared-memory multiprocessor, thread-level parallelism |
40 | Xinmin Tian, Milind Girkar, Sanjiv Shah, Douglas Armstrong, Ernesto Su, Paul Petersen |
Compiler and Runtime Support for Running OpenMP Programs on Pentium- and Itanium-Architectures. |
IPDPS |
2003 |
DBLP DOI BibTeX RDF |
Hyper-Threading technology, Parallelization, OpenMP, compiler optimization, shared-memory multiprocessor, thread-level parallelism |
39 | Lama Nachman, Ralph Kling, Robert Adler, Jonathan Huang, Vincent Hummel |
The Intel Mote platform: a bluetooth-based sensor network for industrial monitoring. |
IPSN |
2005 |
DBLP DOI BibTeX RDF |
|
39 | Ralph Kling, Robert Adler, Jonathan Huang, Vincent Hummel, Lama Nachman |
Intel Mote: using bluetooth in sensor networks. |
SenSys |
2004 |
DBLP DOI BibTeX RDF |
|
39 | Rob Gerth |
Model Checking if Your Life Depends on It a View from Intel's Trenches. |
SPIN |
2001 |
DBLP DOI BibTeX RDF |
|
38 | Ernst D. Dickmanns, Birger D. Mysliwetz |
Recursive 3-D Road and Relative Ego-State Recognition. |
IEEE Trans. Pattern Anal. Mach. Intell. |
1992 |
DBLP DOI BibTeX RDF |
recursive 3D road curvature recognition, Intel 386, ego-state recognition, differential geometry representation, Intel 80286, VaMoRs, pattern recognition, computer vision, computer vision, computational geometry, computerised pattern recognition, temporal constraints, computerised navigation, computerised navigation, spatio-temporal model, spatial constraints, road vehicles |
35 | Perry H. Wang, Jamison D. Collins, Christopher T. Weaver, Belliappa Kuttanna, Shahram Salamian, Gautham N. Chinya, Ethan Schuchman, Oliver Schilling, Thorsten Doil, Sebastian Steibl, Hong Wang 0003 |
Intel® atomTM processor core made FPGA-synthesizable. |
FPGA |
2009 |
DBLP DOI BibTeX RDF |
intel atom, synthesizable core, fpga, emulator |
35 | Stanley Mazor |
Intel 8080 CPU Chip Development. |
IEEE Ann. Hist. Comput. |
2007 |
DBLP DOI BibTeX RDF |
Intel 8080, microchip, microprocessor, history, CPU, microcomputer |
35 | Gilberto Contreras, Margaret Martonosi, Jinzhang Peng, Guei-Yuan Lueh, Roy Ju |
The XTREM power and performance simulator for the Intel XScale core: Design and experiences. |
ACM Trans. Embed. Comput. Syst. |
2007 |
DBLP DOI BibTeX RDF |
Intel XScale technology, Java, Power modeling, power measurements |
35 | Janusz Sosnowski, A. Kusmierczyk |
Pseudorandom versus Deterministic Testing of Intel 80x86 Processors. |
EUROMICRO |
1996 |
DBLP DOI BibTeX RDF |
Intel 80/spl times/86 processors, computer testing, pseudorandom testing, microprocessor testing, deterministic testing |
35 | Anthony-Trung Nguyen, Maged M. Michael, Arun Sharma, Josep Torrellas |
The Augmint multiprocessor simulation toolkit for Intel x86 architectures. |
ICCD |
1996 |
DBLP DOI BibTeX RDF |
Augmint multiprocessor simulation toolkit, Intel x86 architectures, publicly available simulation tools, instruction mix, memory reference patterns, CISC architectures, execution driven multiprocessor simulation toolkit, m4 macro extended C, C++ applications, SPLASH-2 benchmark suites, thread based programming model, shared global address space, private stack space, simulator interface, MINT simulation toolkit, x8d based uniprocessor systems, multiprocessing systems, trace driven simulation, architecture simulators, uniprocessors |
35 | Tong-Yee Lee, Cauligi S. Raghavendra, John B. Nicholas |
Parallel implementation of ray-tracing algorithm on the Intel Delta parallel computer. |
IPPS |
1995 |
DBLP DOI BibTeX RDF |
ray-tracing algorithm, Intel Delta parallel computer, computer graphics techniques, high quality image rendering, memory storage, database distribution, distributed subimages, previous workload requests, parallel algorithms, load balancing, resource allocation, ray tracing, parallel machines, processor, cache storage, parallel implementation, rendering (computer graphics), CPU time, complex scenes |
35 | Allen D. Malony, Daniel A. Reed |
A hardware-based performance monitor for the Intel iPSC/2 hypercube. |
ICS |
1990 |
DBLP DOI BibTeX RDF |
Intel iPSC/ |
35 | Neal S. Coulter |
Information hiding, the Intel iAPX 432, and Ada. |
ACM Southeast Regional Conference |
1982 |
DBLP DOI BibTeX RDF |
Intel iAPX 432, Ada, information hiding, object-oriented software, access rights |
33 | Håkon Ording Bugge |
An evaluation of Intel's core i7 architecture using a comparative approach. |
Comput. Sci. Res. Dev. |
2009 |
DBLP DOI BibTeX RDF |
SPEC MPI2007, Nehalem, iCore7, Harpertown, Quad-Core, QuickPath Interconnect, Moore’s Law, Benchmarking, Stream, Micro-benchmarks |
33 | Jeanna N. Matthews, Sanjeev N. Trika, Debra Hensgen, Rick Coulson, Knut Grimsrud |
Intel Turbo Memory: Nonvolatile disk caches in the storage hierarchy of mainstream computer systems. |
ACM Trans. Storage |
2008 |
DBLP DOI BibTeX RDF |
NAND, write-back, solid-state disk, disk cache, Nonvolatile memory |
33 | Limor Fix |
Fifteen Years of Formal Property Verification in Intel. |
25 Years of Model Checking |
2008 |
DBLP DOI BibTeX RDF |
formal property verification, Model checking, formal specification |
33 | Lu Peng 0001, Jih-Kwon Peir, Tribuvan K. Prakash, Yen-Kuang Chen, David M. Koppelman |
Memory Performance and Scalability of Intel's and AMD's Dual-Core Processors: A Case Study. |
IPCCC |
2007 |
DBLP DOI BibTeX RDF |
|
33 | Alexey Ershov, Andrey Naraikin, Sergey Maidanov |
Quad and correctly rounded double precision math functions: portable and optimized for Intel architectures. |
SAC |
2006 |
DBLP DOI BibTeX RDF |
correct rounding, elementaly functions, quad precision, IEEE 754 |
33 | Swathi Tanjore Gurumani, Aleksandar Milenkovic |
Execution characteristics of SPEC CPU2000 benchmarks: Intel C++ vs. Microsoft VC++. |
ACM Southeast Regional Conference |
2004 |
DBLP DOI BibTeX RDF |
SPEC CPU2000 benchmarks, event-based sampling, performance evaluation, compiler optimizations |
33 | Yen-Kuang Chen, Xinmin Tian, Steven Ge, Milind Girkar |
Towards Efficient Multi-Level Threading of H.264 Encoder on Intel Hyper-Threading Architectures. |
IPDPS |
2004 |
DBLP DOI BibTeX RDF |
H.264 standard, Hyper-Threading Technology, multimedia, OpenMP, thread-level parallelism |
33 | John F. Palmer |
The INTEL® 8087 numeric data processor. |
AFIPS National Computer Conference |
1980 |
DBLP DOI BibTeX RDF |
|
32 | R. Asbury, M. Wrinn |
MPI tuning with Intel© Trace Analyzer and Intel Trace Collector. |
CLUSTER |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Carol Currie Sobczak, James Kessler, David Eldridge |
The dual os classroom: if you build it, will they come? |
SIGUCCS |
2007 |
DBLP DOI BibTeX RDF |
boot camp, deep freeze, intel dual core, winbatch, parallels, imaging, deployment, support, classroom technology |
29 | Linda Dailey Paulson |
News Briefs. |
Computer |
2006 |
DBLP DOI BibTeX RDF |
AMD, chip-making technology, sports technology, Subdue program, Data mining, optical networks, microprocessors, pattern analysis, Intel, sensor technology |
29 | Sharad Garg, Jens Mache |
Performance Evaluation of Parallel File Systems for PC Clusters and ASCI Red. |
CLUSTER |
2001 |
DBLP DOI BibTeX RDF |
Intel PFS, performance evaluation, parallel I/O, parallel file system, Beowulf cluster, PVFS |
29 | Miriam Leeser, John W. O'Leary |
Verification of a subtractive radix-2 square root algorithm and implementation. |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
subtractive radix-2 square root, floating point square root hardware, Intel Pentium, radix-2 square root, MIPS R4400, RTL level, verification, formal verification, theorem proving, theorem proving, floating point arithmetic, optimizing transformations |
28 | Martin Curley, Jim Kenneally |
Using the IT Capability Maturity Framework to Improve IT Capability and Value Creation: An Intel IT Case Study. |
EDOC |
2011 |
DBLP DOI BibTeX RDF |
IT-CMF, IT Capability Maturity Framework, Intel Corporation, Design Pattern, Information Technology, Business Value, Design Science |
28 | Stanley Mazor |
Intel's 8086. |
IEEE Ann. Hist. Comput. |
2010 |
DBLP DOI BibTeX RDF |
8086, Pentium, Bill Davidow, Steve Morse, CPU, Intel |
28 | Stanley Mazor, Peter Salmon |
Anecdotes: Magnavox and Intel: An Odyssey. |
IEEE Ann. Hist. Comput. |
2009 |
DBLP DOI BibTeX RDF |
Anecdotes, Magnavox, Intel |
28 | Alexander Wolfe |
Toolkit: Intel's Heavy-Duty Dev Tools. |
ACM Queue |
2004 |
DBLP DOI BibTeX RDF |
Intel |
28 | Ville Lappalainen |
Performance Analysis of Intel MMX Technology for an H.263 Video H.263 Video Encoder. |
ACM Multimedia |
1998 |
DBLP DOI BibTeX RDF |
Intel MMX, performance, video encoder, H.263 |
28 | Jean Scholtz, Paul G. Sorenson |
Interface evaluation, design and research at Intel. |
CHI 95 Conference Companion |
1995 |
DBLP DOI BibTeX RDF |
Intel |
28 | Jhy-Chun Wang, Sanjay Ranka |
Scheduling of unstructured communication on the Intel iPSC/860. |
SC |
1994 |
DBLP DOI BibTeX RDF |
Intel iPSC/ |
27 | Jorge Guerra, Wendy Belluomini, Joseph S. Glider, Karan Gupta, Himabindu Pucha |
Energy proportionality for storage: impact and feasibility. |
ACM SIGOPS Oper. Syst. Rev. |
2010 |
DBLP DOI BibTeX RDF |
|
27 | Chad D. DeJong, Seth A. Fischbein |
Semiconductor manufacturing material handling systems: integrating dynamic fab capacity and automation models for 300mm semiconductor manufacturing. |
WSC |
2000 |
DBLP DOI BibTeX RDF |
|
26 | Roope Kaivola, Rajnish Ghughal, Naren Narasimhan, Amber Telfer, Jesse Whittemore, Sudhindra Pandav, Anna Slobodová, Christopher Taylor, Vladimir A. Frolov, Erik Reeber, Armaghan Naik |
Replacing Testing with Formal Verification in Intel CoreTM i7 Processor Execution Engine Validation. |
CAV |
2009 |
DBLP DOI BibTeX RDF |
|
26 | Ryad Benadjila, Olivier Billet, Shay Gueron, Matthew J. B. Robshaw |
The Intel AES Instructions Set and the SHA-3 Candidates. |
ASIACRYPT |
2009 |
DBLP DOI BibTeX RDF |
|
26 | Aart J. C. Bik, David L. Kreitzer, Xinmin Tian |
A Case Study on Compiler Optimizations for the Intel® CoreTM 2 Duo Processor. |
Int. J. Parallel Program. |
2008 |
DBLP DOI BibTeX RDF |
Optimization, Parallelization, Compilers, Code generation, Vectorization |
26 | Michael Buettner, Richa Prasad, Alanson P. Sample, Daniel J. Yeager, Ben Greenstein, Joshua R. Smith 0001, David Wetherall |
RFID sensor networks with the intel WISP. |
SenSys |
2008 |
DBLP DOI BibTeX RDF |
sensor networks, rfid |
26 | Christian Terboven, Dieter an Mey, Dirk Schmidl, Marcus Wagner |
First Experiences with Intel Cluster OpenMP. |
IWOMP |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Pawel Gepner |
Intel's Technology Vision and Products for HPC. |
ICCS (1) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Sivakumar Radhakrishnan, Sundaram Chinthamani, Kai Cheng |
The Blackford Northbridge Chipset for the Intel 5000. |
IEEE Micro |
2007 |
DBLP DOI BibTeX RDF |
platform architecture, dual-processor system, northbridge chipset, I/O bridges, FB-DIMM memory technology, low-power design, shared memory |
26 | Robert Ennals, Eric A. Brewer, Minos N. Garofalakis, Michael Shadle, Prashant Gandhi |
Intel Mash Maker: join the web. |
SIGMOD Rec. |
2007 |
DBLP DOI BibTeX RDF |
visualization, personalization, data integration, mashup |
26 | Tommy Bojan, Igor Frumkin, Robert Mauri |
Intel First Ever Converged Core Functional Validation Experience: Methodologies, Challenges, Results and Learning. |
MTV |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Andrew M. Scott, Mark E. Schuelein, Marly Roncken, Jin-Jer Hwan, John Bainbridge, John R. Mawer, David L. Jackson, Andrew Bardsley |
Asynchronous on-Chip Communication: Explorations on the Intel PXA27x Processor Peripheral Bus. |
ASYNC |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Daniel A. Orozco, Liping Xue, Murat Bolat, Xiaoming Li, Guang R. Gao |
Experience of Optimizing FFT on Intel Architectures. |
IPDPS |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Pawel Gepner, David L. Fraser, Michal Filip Kowalik |
Performance Evolution and Power Benefits of Cluster System Utilizing Quad-Core and Dual-Core Intel Xeon Processors. |
PPAM |
2007 |
DBLP DOI BibTeX RDF |
dual-core processors, quad-core processors, parallel processing, benchmarks, HPC, multi-core processors |
26 | Alon Flaisher, Alon Gluska, Eli Singerman |
Case study: Integrating FV and DV in the Verification of the Intel CoreTM 2 Duo Microprocessor. |
FMCAD |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Mitsuru Matsui, Junko Nakajima |
On the Power of Bitslice Implementation on Intel Core2 Processor. |
CHES |
2007 |
DBLP DOI BibTeX RDF |
Fast Software Encryption, Bitslice, KASUMI, Core2, AES |
26 | Jiangjiang Liu 0002, Brian Bell, Tan Truong |
Analysis and Characterization of Intel Itanium Instruction Bundles for Improving VLIW Processor Performance. |
IMSCCS (1) |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Stephen Wheat, Bob Jones |
Grids and network applications - Addressing high performance and grid challenges: Intel and CERN. |
SC |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Richard Uhlig, Gil Neiger, Dion Rodgers, Amy L. Santoni, Fernando C. M. Martins, Andrew V. Anderson, Steven M. Bennett, Alain Kägi, Felix H. Leung, Larry Smith 0001 |
Intel Virtualization Technology. |
Computer |
2005 |
DBLP DOI BibTeX RDF |
Itanium architecture, IA-32 architecture, virtual machines, computer architectures, software systems, virtualization technology |
26 | Vikram A. Saletore, Paul M. Stillwell Jr., John A. Wiegert, Phil Cayton, Jeff Gray 0001, Greg J. Regnier |
Efficient Direct User Level Sockets for an Intel XeonTM Processor Based TCP On-Load Engin. |
IPDPS |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Greg J. Regnier, Dave B. Minturn, Gary L. McAlpine, Vikram A. Saletore, Annie P. Foong |
ETA: Experience with an Intel Xeon Processor as a Packet Processing Engine. |
IEEE Micro |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Gilberto Contreras, Margaret Martonosi, Jinzhan Peng, Roy Ju, Guei-Yuan Lueh |
XTREM: a power simulator for the Intel XScale® core. |
LCTES |
2004 |
DBLP DOI BibTeX RDF |
XORP, XScale, Java, power modeling, hardware performance counters, power measurements |
26 | Jasmeet Chhabra, Nandakishore Kushalnagar, Benjamin Metzler, Allen Sampson |
Sensor networks in intel fabrication plants. |
SenSys |
2004 |
DBLP DOI BibTeX RDF |
predictive maintenance, sensor networks, vibration analysis |
26 | Faye A. Briggs, Suresh Chittor, Kai Cheng |
Micro-architecture techniques in the intel E8870 scalable memory controller. |
WMPI |
2004 |
DBLP DOI BibTeX RDF |
distributed coherency, transaction flows, scalability, memory latency |
26 | Chi-Keung Luk, Robert Muth, Harish Patil, Robert S. Cohn, P. Geoffrey Lowney |
Ispike: A Post-link Optimizer for the Intel®Itanium®Architecture. |
CGO |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Karl Solchenbach |
From Science to Enterprise - Intel's Grid Activities. |
GCC |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Ramesh Radhakrishnan, Rizwan Ali, Garima Kochhar, Kalyana Chadalavada, Ramesh Rajagopalan, Jenwei Hsieh, Onur Celebioglu |
Evaluating Performance of BLAST on Intel Xeon and Itanium2 Processors. |
ISPA |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Scott Hamilton |
Intel Research Extends Moore's Law. |
Computer |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Wan-Chun Ma, Chia-Lin Yang |
Using Intel Streaming SIMD Extensions for 3D Geometry Processing. |
IEEE Pacific Rim Conference on Multimedia |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Robert P. Colwell, Gary Brown, Frank See |
Intel's College Hiring Methods and Recent Results. |
MSE |
1999 |
DBLP DOI BibTeX RDF |
|
26 | Aaron B. Brown, Margo I. Seltzer |
Operating System Benchmarking in the Wake of Lmbench: A Case Study of the Performance of NetBSD on Intel x86 Architecture. |
SIGMETRICS |
1997 |
DBLP DOI BibTeX RDF |
|
26 | Meenakshi Arunachalam, Alok N. Choudhary, Brad Rullman |
Implementation and Evaluation of Prefetching in the Intel Paragon Parallel File System. |
IPPS |
1996 |
DBLP DOI BibTeX RDF |
|
26 | John N. Shadid, Scott A. Hutchinson, Harry Moffat, Gary L. Hennigan, Bruce Hendrickson, Robert W. Leland |
A 65+ Gflops/s unstructured finite element simulation of chemically reacting flows on the Intel Paragon. |
SC |
1994 |
DBLP DOI BibTeX RDF |
|
26 | David E. Womble, David S. Greenberg, Stephen R. Wheat, Robert E. Benner, Marc S. Ingber, Greg Henry, Satya Gupta |
Applications of boundary element methods on the Intel Paragon. |
SC |
1994 |
DBLP DOI BibTeX RDF |
|
26 | James C. French, Terrence W. Pratt, Mriganka Das |
Performance Measurement of a Parallel Input/Output System for the Intel iPSC/2 Hypercube. |
SIGMETRICS |
1991 |
DBLP DOI BibTeX RDF |
|
26 | Robert P. Colwell, Edward F. Gehringer, E. Douglas Jensen |
Performance Effects of Architectural Complexity in the Intel 432. |
ACM Trans. Comput. Syst. |
1988 |
DBLP DOI BibTeX RDF |
|
25 | Azalea Raad, Luc Maranget, Viktor Vafeiadis |
Extending Intel-x86 consistency and persistency: formalising the semantics of Intel-x86 memory types and non-temporal stores. |
Proc. ACM Program. Lang. |
2022 |
DBLP DOI BibTeX RDF |
|
25 | Galen M. Shipman, Sriram Swaminarayan, Gary Grider, Jim Lujan, R. Joseph Zerr |
Early Performance Results on 4th Gen Intel(R) Xeon (R) Scalable Processors with DDR and Intel(R) Xeon(R) processors, codenamed Sapphire Rapids with HBM. |
CoRR |
2022 |
DBLP DOI BibTeX RDF |
|
25 | Fabian Boemer, Sejun Kim, Gelila Seifu, Fillipe D. M. de Souza, Vinodh Gopal |
Intel HEXL: Accelerating Homomorphic Encryption with Intel AVX512-IFMA52. |
CoRR |
2021 |
DBLP BibTeX RDF |
|
25 | Fabian Boemer, Sejun Kim, Gelila Seifu, Fillipe D. M. de Souza, Vinodh Gopal |
Intel HEXL: Accelerating Homomorphic Encryption with Intel AVX512-IFMA52. |
IACR Cryptol. ePrint Arch. |
2021 |
DBLP BibTeX RDF |
|
25 | Fabian Boemer, Sejun Kim, Gelila Seifu, Fillipe D. M. de Souza, Vinodh Gopal |
Intel HEXL: Accelerating Homomorphic Encryption with Intel AVX512-IFMA52. |
WAHC@CCS |
2021 |
DBLP DOI BibTeX RDF |
|
25 | Dounia Khaldi, Yuanke Luo, Bing Yu, Alexey Sotkin, Bruno Morais, Milind Girkar |
Extending LLVM IR for DPC++ Matrix Support: A Case Study with Intel® Advanced Matrix Extensions (Intel® AMX). |
LLVM-HPC@SC |
2021 |
DBLP DOI BibTeX RDF |
|
25 | Roktaek Lim, Yeongha Lee, Raehyun Kim, Jaeyoung Choi, Myungho Lee |
Auto-tuning GEMM kernels on the Intel KNL and Intel Skylake-SP processors. |
J. Supercomput. |
2019 |
DBLP DOI BibTeX RDF |
|
25 | Gina Mathew, S. Sindhu Ramachandran, V. S. Suchithra |
Lung Nodule Detection from low dose CT scan using Optimization on Intel Xeon and Core processors with Intel Distribution of OpenVINO Toolkit. |
TENCON |
2019 |
DBLP DOI BibTeX RDF |
|
25 | Soyeon Park, Sangho Lee 0001, Wen Xu 0002, Hyungon Moon, Taesoo Kim |
libmpk: Software Abstraction for Intel Memory Protection Keys (Intel MPK). |
USENIX Annual Technical Conference |
2019 |
DBLP BibTeX RDF |
|
25 | Somnath Chakrabarti, Matthew Hoekstra, Dmitrii Kuvaiskii, Mona Vij |
Scaling Intel® Software Guard Extensions Applications with Intel® SGX Card. |
HASP@ISCA |
2019 |
DBLP DOI BibTeX RDF |
|
Displaying result #1 - #100 of 3231 (100 per page; Change: ) Pages: [ 1][ 2][ 3][ 4][ 5][ 6][ 7][ 8][ 9][ 10][ >>] |
|