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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 2160 occurrences of 1221 keywords
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Results
Found 3233 publication records. Showing 3231 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
89 | James A. Lupo |
Benchmarking UHGROMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (5) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 132-141, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
GROMOS, parallel Fortran preprocessor, Pfortran, Intel Corporation, IBM Corporation, massively parallel processor machines, Intel iPSC/860, Caltech Intel DELTA, IBM SP1, UHGROMOS molecular dynamics program, test application, parallel performance analysis, parallel programming, benchmarking, FORTRAN, parallel machines, parallel machines, software performance evaluation, physics, parallel languages, software portability, physics computing, porting, Intel Paragon, program processors, molecular dynamics method |
60 | Subhash Saini, Andrey Naraikin, Rupak Biswas, David Barkai, Timothy Sandstrom |
Early performance evaluation of a "Nehalem" cluster using scientific and engineering applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE Conference on High Performance Computing, SC 2009, November 14-20, 2009, Portland, Oregon, USA, 2009, ACM, 978-1-60558-744-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
59 | Corporate Intel |
The Intel iPSC/2 system: the concurrent supercomputer for production applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
C³P ![In: Proceedings of the Third Conference on Hypercube Concurrent Computers and Applications - Architecture, Software, Computer Systems, and General Issues, C³P, Pasadena, California, USA, January 19-20, 1988, pp. 843-846, 1988, ACM, 978-0-89791-278-5. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
53 | Alexander Kalinkin, Yuri M. Laevsky, Sergey Gololobov |
2D Fast Poisson Solver for High-Performance Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PaCT ![In: Parallel Computing Technologies, 10th International Conference, PaCT 2009, Novosibirsk, Russia, August 31-September 4, 2009. Proceedings, pp. 112-120, 2009, Springer, 978-3-642-03274-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
52 | Ken Wagner, Patrick P. Gelsinger |
Driving the $5 Billion Innovation Engine at Intel: An Interview with Patrick P. Gelsinger, Digital Enterprise Group Senior Vice President and General Manager, Intel. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 22(2), pp. 170-180, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
50 | Alan R. Shealy, Brian A. Malloy, David A. Sykes |
SIMx86: An extensible simulator for the Intel 80×86 processor family. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Annual Simulation Symposium ![In: Proceedings 30st Annual Simulation Symposium (SS '97), April 7-9, 1997, Atlanta, GA, USA, pp. 157-166, 1997, IEEE Computer Society, 0-8186-7934-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
SIMx86, extensible simulator, Intel 80/spl times/86, Intel 8088 processor, 8086 processor, debugging facilities, simulator construction, virtual machines, domain model, performance gains, processor simulators |
48 | Zbigniew Stachniak |
Intel SIM8-01: A Proto-PC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Ann. Hist. Comput. ![In: IEEE Ann. Hist. Comput. 29(1), pp. 34-48, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
microprocessor development system, Intel 8008, personal computer, microcomputer |
47 | Intel Corporation |
Pioneering and continuing contributions to the semiconductor industry. The Franklin Institute's 2002 Bower Award for business leadership presented to Gordon E. Moore. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Frankl. Inst. ![In: J. Frankl. Inst. 340(3-4), pp. 243-247, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
46 | Pawel Gepner, David L. Fraser, Michal Filip Kowalik |
Second Generation Quad-Core Intel Xeon Processors Bring 45 nm Technology and a New Level of Performance to HPC Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCS (1) ![In: Computational Science - ICCS 2008, 8th International Conference, Kraków, Poland, June 23-25, 2008, Proceedings, Part I, pp. 417-426, 2008, Springer, 978-3-540-69383-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
quad-core processors, parallel processing, benchmarks, HPC, multi-core processors |
46 | Michael Wolfe |
Software tools I - AMD versus Intel: the compiler as referee. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE SC2006 Conference on High Performance Networking and Computing, November 11-17, 2006, Tampa, FL, USA, pp. 275, 2006, ACM Press, 0-7695-2700-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
46 | Dana Plautz |
A look at Intel's research council funding in sensor networks for feature film production and interactive drama. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Entertain. ![In: Comput. Entertain. 2(4), pp. 17, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
film production, networks, artificial intelligence, arts, digital media, interactive drama, theatre |
46 | Xinmin Tian, Yen-Kuang Chen, Milind Girkar, Steven Ge, Rainer Lienhart, Sanjiv Shah |
Exploring the Use of Hyper-Threading Technology for Multimedia Applications with Intel® OpenMP* Compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 22-26 April 2003, Nice, France, CD-ROM/Abstracts Proceedings, pp. 36, 2003, IEEE Computer Society, 0-7695-1926-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Hyper-Threading technology, multimedia algorithm, parallelization, OpenMP, compiler optimization |
45 | Chih Jeng Kenneth Tan, David Hagan, Matthew F. Dixon |
A Performance Comparison of Matrix Solvers on Compaq Alpha, Intel Itanium, and Intel Itanium II Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCSA (1) ![In: Computational Science and Its Applications - ICCSA 2003, International Conference, Montreal, Canada, May 18-21, 2003, Proceedings, Part I, pp. 818-827, 2003, Springer, 3-540-40155-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Systems of linear algebraic equations, Architecture specific tuning, Linear solver |
44 | Zhiwei Xu, Kai Hwang 0001 |
MPPs and clusters for scalable computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 1996 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '96), June 12-14, 1996, Beijing, China, pp. 117-123, 1996, IEEE Computer Society, 0-8186-7460-1. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
scalable parallel computing, Cray T3D/T3E, ASCI TeraFLOPS, performance evaluation, scalability, parallel architectures, reconfigurable architectures, clusters of workstations, Intel Paragon, Intel, massively parallel processors, performance attributes, scalable computing, MPPs, IBM SP2 |
44 | Philip J. Hatcher, Michael J. Quinn, Anthony J. Lapadula, Bradley K. Seevers, Ray J. Anderson, Robert R. Jones |
Data-Parallel Programming on MIMD Computers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 2(3), pp. 377-383, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
data-parallel programming language Dataparallel C, nCUBE hypercubemulticomputers, Sequent multiprocessors, Dataparallel C programs, Intel iPSC/2, nCUBE 3200, Sequent Symmetry, hypercubenetworks, parallel programming, compilers, program compilers, parallel languages, speedups, execution times, C language, Intel |
41 | Graham Schelle, Jamison D. Collins, Ethan Schuchman, Perry H. Wang, Xiang Zou, Gautham N. Chinya, Ralf Plate, Thorsten Mattner, Franz Olbrich, Per Hammarlund, Ronak Singhal, Jim Brayton, Sebastian Steibl, Hong Wang 0003 |
Intel nehalem processor core made FPGA synthesizable. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 3-12, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
intel nehalem, synthesizable core, fpga, emulator |
41 | Matthew Henricksen, Ed Dawson |
Ensuring Fast Implementations of Symmetric Ciphers on the Intel Pentium 4 and Beyond. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACISP ![In: Information Security and Privacy, 11th Australasian Conference, ACISP 2006, Melbourne, Australia, July 3-5, 2006, Proceedings, pp. 52-63, 2006, Springer, 3-540-35458-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Intel Pentium 4, Dragon, HC-256, MAG, Mir-1, Py, Implementation, Stream cipher, RC4 |
41 | Soon Myoung Chung, Arindam Chatterjee |
Parallel Distributive Join Algorithm on the Intel Paragon. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 13(2), pp. 151-169, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Hybrid-hash join, Performance analysis, Parallel processing, Intel Paragon, Distributive join |
41 | Soon Myoung Chung, Arindam Chatterjee |
Performance Analysis of a Parallel Distributive Join Algorithm on the Intel Paragon. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 1997 International Conference on Parallel and Distributed Systems (ICPADS '97), 11-13 December 1997, Seoul, Korea, Proceedings, pp. 714-, 1997, IEEE Computer Society, 0-8186-8227-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Hybrid Hash join, Parallel Processing, Intel Paragon, Distributive join |
40 | Shreekant (Ticky) Thakkar |
Battery life challenges on future mobile notebook platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 187, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
40 | Xinmin Tian, Milind Girkar, Sanjiv Shah, Douglas Armstrong, Ernesto Su, Paul Petersen |
Compiler and Runtime Support for Running OpenMP Programs on Pentium-and Itanium-Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HIPS ![In: Eighth International Workshop on High-Level Parallel Programming Models and Supportive Environments (HIPS'03), April 22-22, 2003, Nice, France, pp. 47-55, 2003, IEEE Computer Society, 0-7695-1880-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Hyper-Threading technology, Parallelization, OpenMP, compiler optimization, shared-memory multiprocessor, thread-level parallelism |
40 | Xinmin Tian, Milind Girkar, Sanjiv Shah, Douglas Armstrong, Ernesto Su, Paul Petersen |
Compiler and Runtime Support for Running OpenMP Programs on Pentium- and Itanium-Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 22-26 April 2003, Nice, France, CD-ROM/Abstracts Proceedings, pp. 130, 2003, IEEE Computer Society, 0-7695-1926-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Hyper-Threading technology, Parallelization, OpenMP, compiler optimization, shared-memory multiprocessor, thread-level parallelism |
39 | Lama Nachman, Ralph Kling, Robert Adler, Jonathan Huang, Vincent Hummel |
The Intel Mote platform: a bluetooth-based sensor network for industrial monitoring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPSN ![In: Proceedings of the Fourth International Symposium on Information Processing in Sensor Networks, IPSN 2005, April 25-27, 2005, UCLA, Los Angeles, California, USA, pp. 437-442, 2005, IEEE, 0-7803-9202-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
39 | Ralph Kling, Robert Adler, Jonathan Huang, Vincent Hummel, Lama Nachman |
Intel Mote: using bluetooth in sensor networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SenSys ![In: Proceedings of the 2nd International Conference on Embedded Networked Sensor Systems, SenSys 2004, Baltimore, MD, USA, November 3-5, 2004, pp. 318, 2004, ACM, 1-58113-879-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
39 | Rob Gerth |
Model Checking if Your Life Depends on It a View from Intel's Trenches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPIN ![In: Model Checking Software, 8th International SPIN Workshop, Toronto, Canada, May 19-20, 2001, Proceedings, pp. 15, 2001, Springer, 3-540-42124-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
38 | Ernst D. Dickmanns, Birger D. Mysliwetz |
Recursive 3-D Road and Relative Ego-State Recognition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Pattern Anal. Mach. Intell. ![In: IEEE Trans. Pattern Anal. Mach. Intell. 14(2), pp. 199-213, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
recursive 3D road curvature recognition, Intel 386, ego-state recognition, differential geometry representation, Intel 80286, VaMoRs, pattern recognition, computer vision, computer vision, computational geometry, computerised pattern recognition, temporal constraints, computerised navigation, computerised navigation, spatio-temporal model, spatial constraints, road vehicles |
35 | Perry H. Wang, Jamison D. Collins, Christopher T. Weaver, Belliappa Kuttanna, Shahram Salamian, Gautham N. Chinya, Ethan Schuchman, Oliver Schilling, Thorsten Doil, Sebastian Steibl, Hong Wang 0003 |
Intel® atomTM processor core made FPGA-synthesizable. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 209-218, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
intel atom, synthesizable core, fpga, emulator |
35 | Stanley Mazor |
Intel 8080 CPU Chip Development. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Ann. Hist. Comput. ![In: IEEE Ann. Hist. Comput. 29(2), pp. 70-73, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Intel 8080, microchip, microprocessor, history, CPU, microcomputer |
35 | Gilberto Contreras, Margaret Martonosi, Jinzhang Peng, Guei-Yuan Lueh, Roy Ju |
The XTREM power and performance simulator for the Intel XScale core: Design and experiences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 6(1), pp. 4, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Intel XScale technology, Java, Power modeling, power measurements |
35 | Janusz Sosnowski, A. Kusmierczyk |
Pseudorandom versus Deterministic Testing of Intel 80x86 Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 22rd EUROMICRO Conference '96, Beyond 2000: Hardware and Software Design Strategies, September 2-5, 1996, Prague, Czech Republic, pp. 329-336, 1996, IEEE Computer Society, 0-8186-7487-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Intel 80/spl times/86 processors, computer testing, pseudorandom testing, microprocessor testing, deterministic testing |
35 | Anthony-Trung Nguyen, Maged M. Michael, Arun Sharma, Josep Torrellas |
The Augmint multiprocessor simulation toolkit for Intel x86 architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 486-490, 1996, IEEE Computer Society, 0-8186-7554-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Augmint multiprocessor simulation toolkit, Intel x86 architectures, publicly available simulation tools, instruction mix, memory reference patterns, CISC architectures, execution driven multiprocessor simulation toolkit, m4 macro extended C, C++ applications, SPLASH-2 benchmark suites, thread based programming model, shared global address space, private stack space, simulator interface, MINT simulation toolkit, x8d based uniprocessor systems, multiprocessing systems, trace driven simulation, architecture simulators, uniprocessors |
35 | Tong-Yee Lee, Cauligi S. Raghavendra, John B. Nicholas |
Parallel implementation of ray-tracing algorithm on the Intel Delta parallel computer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '95, The 9th International Parallel Processing Symposium, April 25-28, 1995, Santa Barbara, California, USA, pp. 688-692, 1995, IEEE Computer Society, 0-8186-7074-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
ray-tracing algorithm, Intel Delta parallel computer, computer graphics techniques, high quality image rendering, memory storage, database distribution, distributed subimages, previous workload requests, parallel algorithms, load balancing, resource allocation, ray tracing, parallel machines, processor, cache storage, parallel implementation, rendering (computer graphics), CPU time, complex scenes |
35 | Allen D. Malony, Daniel A. Reed |
A hardware-based performance monitor for the Intel iPSC/2 hypercube. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 4th international conference on Supercomputing, ICS 1990, Amsterdam, The Netherlands, June 11-15, 1990, pp. 213-226, 1990, ACM, 0-89791-369-8. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
Intel iPSC/ |
35 | Neal S. Coulter |
Information hiding, the Intel iAPX 432, and Ada. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Southeast Regional Conference ![In: Proceedings of the 20th Annual Southeast Regional Conference, 1982, Knoxville, Tennessee, USA, April 1-3, 1982, pp. 160-167, 1982, ACM, 0-89791-071-0. The full citation details ...](Pics/full.jpeg) |
1982 |
DBLP DOI BibTeX RDF |
Intel iAPX 432, Ada, information hiding, object-oriented software, access rights |
33 | Håkon Ording Bugge |
An evaluation of Intel's core i7 architecture using a comparative approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Sci. Res. Dev. ![In: Comput. Sci. Res. Dev. 23(3-4), pp. 203-209, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
SPEC MPI2007, Nehalem, iCore7, Harpertown, Quad-Core, QuickPath Interconnect, Moore’s Law, Benchmarking, Stream, Micro-benchmarks |
33 | Jeanna N. Matthews, Sanjeev N. Trika, Debra Hensgen, Rick Coulson, Knut Grimsrud |
Intel Turbo Memory: Nonvolatile disk caches in the storage hierarchy of mainstream computer systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Storage ![In: ACM Trans. Storage 4(2), pp. 4:1-4:24, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
NAND, write-back, solid-state disk, disk cache, Nonvolatile memory |
33 | Limor Fix |
Fifteen Years of Formal Property Verification in Intel. ![Search on Bibsonomy](Pics/bibsonomy.png) |
25 Years of Model Checking ![In: 25 Years of Model Checking - History, Achievements, Perspectives, pp. 139-144, 2008, Springer, 978-3-540-69849-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
formal property verification, Model checking, formal specification |
33 | Lu Peng 0001, Jih-Kwon Peir, Tribuvan K. Prakash, Yen-Kuang Chen, David M. Koppelman |
Memory Performance and Scalability of Intel's and AMD's Dual-Core Processors: A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPCCC ![In: Proceedings of the 26th IEEE International Performance Computing and Communications Conference, IPCCC 2007, April 11-13, 2007, New Orleans, Louisiana, USA, pp. 55-64, 2007, IEEE Computer Society, 1-4244-1138-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
33 | Alexey Ershov, Andrey Naraikin, Sergey Maidanov |
Quad and correctly rounded double precision math functions: portable and optimized for Intel architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2006 ACM Symposium on Applied Computing (SAC), Dijon, France, April 23-27, 2006, pp. 1310-1317, 2006, ACM, 1-59593-108-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
correct rounding, elementaly functions, quad precision, IEEE 754 |
33 | Swathi Tanjore Gurumani, Aleksandar Milenkovic |
Execution characteristics of SPEC CPU2000 benchmarks: Intel C++ vs. Microsoft VC++. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Southeast Regional Conference ![In: Proceedings of the 42nd Annual Southeast Regional Conference, 2004, Huntsville, Alabama, USA, April 2-3, 2004, pp. 261-266, 2004, ACM, 1-58113-870-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
SPEC CPU2000 benchmarks, event-based sampling, performance evaluation, compiler optimizations |
33 | Yen-Kuang Chen, Xinmin Tian, Steven Ge, Milind Girkar |
Towards Efficient Multi-Level Threading of H.264 Encoder on Intel Hyper-Threading Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), CD-ROM / Abstracts Proceedings, 26-30 April 2004, Santa Fe, New Mexico, USA, 2004, IEEE Computer Society, 0-7695-2132-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
H.264 standard, Hyper-Threading Technology, multimedia, OpenMP, thread-level parallelism |
33 | John F. Palmer |
The INTEL® 8087 numeric data processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AFIPS National Computer Conference ![In: American Federation of Information Processing Societies: 1980 National Computer Conference, 19-22 May 1980, Anaheim, California, USA, pp. 887-893, 1980, AFIPS Press, 978-1-4503-7923-6. The full citation details ...](Pics/full.jpeg) |
1980 |
DBLP DOI BibTeX RDF |
|
32 | R. Asbury, M. Wrinn |
MPI tuning with Intel© Trace Analyzer and Intel Trace Collector. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CLUSTER ![In: 2004 IEEE International Conference on Cluster Computing (CLUSTER 2004), September 20-23 2004, San Diego, California, USA, pp. 4, 2004, IEEE Computer Society, 0-7803-8694-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Carol Currie Sobczak, James Kessler, David Eldridge |
The dual os classroom: if you build it, will they come? ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGUCCS ![In: Proceedings of the 35th Annual ACM SIGUCCS Conference on User Services 2007, Orlando, Florida, USA, October 7-10, 2007, pp. 321-324, 2007, ACM, 978-1-59593-634-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
boot camp, deep freeze, intel dual core, winbatch, parallels, imaging, deployment, support, classroom technology |
29 | Linda Dailey Paulson |
News Briefs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computer ![In: Computer 39(1), pp. 24-26, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
AMD, chip-making technology, sports technology, Subdue program, Data mining, optical networks, microprocessors, pattern analysis, Intel, sensor technology |
29 | Sharad Garg, Jens Mache |
Performance Evaluation of Parallel File Systems for PC Clusters and ASCI Red. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CLUSTER ![In: 2001 IEEE International Conference on Cluster Computing (CLUSTER 2001), 8-11 October 2001, Newport Beach, CA, USA, pp. 172-177, 2001, IEEE Computer Society, 0-7695-1116-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Intel PFS, performance evaluation, parallel I/O, parallel file system, Beowulf cluster, PVFS |
29 | Miriam Leeser, John W. O'Leary |
Verification of a subtractive radix-2 square root algorithm and implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 526-531, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
subtractive radix-2 square root, floating point square root hardware, Intel Pentium, radix-2 square root, MIPS R4400, RTL level, verification, formal verification, theorem proving, theorem proving, floating point arithmetic, optimizing transformations |
28 | Martin Curley, Jim Kenneally |
Using the IT Capability Maturity Framework to Improve IT Capability and Value Creation: An Intel IT Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EDOC ![In: Proceedings of the 15th IEEE International Enterprise Distributed Object Computing Conference, EDOC 2011, Helsinki, Finland, August 29 - September 2, 2011, pp. 107-115, 2011, IEEE Computer Society, 978-1-4577-0362-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
IT-CMF, IT Capability Maturity Framework, Intel Corporation, Design Pattern, Information Technology, Business Value, Design Science |
28 | Stanley Mazor |
Intel's 8086. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Ann. Hist. Comput. ![In: IEEE Ann. Hist. Comput. 32(1), pp. 75-79, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
8086, Pentium, Bill Davidow, Steve Morse, CPU, Intel |
28 | Stanley Mazor, Peter Salmon |
Anecdotes: Magnavox and Intel: An Odyssey. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Ann. Hist. Comput. ![In: IEEE Ann. Hist. Comput. 31(3), pp. 64-67, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Anecdotes, Magnavox, Intel |
28 | Alexander Wolfe |
Toolkit: Intel's Heavy-Duty Dev Tools. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Queue ![In: ACM Queue 2(2), pp. 12-17, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Intel |
28 | Ville Lappalainen |
Performance Analysis of Intel MMX Technology for an H.263 Video H.263 Video Encoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Multimedia ![In: Proceedings of the 6th ACM International Conference on Multimedia '98, Bristol, England, September 12-16, 1998., pp. 309-314, 1998, ACM, 0-201-30990-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Intel MMX, performance, video encoder, H.263 |
28 | Jean Scholtz, Paul G. Sorenson |
Interface evaluation, design and research at Intel. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHI 95 Conference Companion ![In: Human Factors in Computing Systems, CHI '95 Conference Companion: Mosaic of Creativity, Denver, Colorado, USA, May 7-11, 1995., pp. 158-159, 1995, ACM, 0-89791-755-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Intel |
28 | Jhy-Chun Wang, Sanjay Ranka |
Scheduling of unstructured communication on the Intel iPSC/860. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings Supercomputing '94, Washington, DC, USA, November 14-18, 1994, pp. 360-369, 1994, IEEE Computer Society, 0-8186-6605-6. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
Intel iPSC/ |
27 | Jorge Guerra, Wendy Belluomini, Joseph S. Glider, Karan Gupta, Himabindu Pucha |
Energy proportionality for storage: impact and feasibility. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGOPS Oper. Syst. Rev. ![In: ACM SIGOPS Oper. Syst. Rev. 44(1), pp. 35-39, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
27 | Chad D. DeJong, Seth A. Fischbein |
Semiconductor manufacturing material handling systems: integrating dynamic fab capacity and automation models for 300mm semiconductor manufacturing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WSC ![In: Proceedings of the 32nd conference on Winter simulation, WSC 2000, Wyndham Palace Resort & Spa, Orlando, FL, USA, December 10-13, 2000, pp. 1505-1509, 2000, WSC, 0-7803-6582-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
26 | Roope Kaivola, Rajnish Ghughal, Naren Narasimhan, Amber Telfer, Jesse Whittemore, Sudhindra Pandav, Anna Slobodová, Christopher Taylor, Vladimir A. Frolov, Erik Reeber, Armaghan Naik |
Replacing Testing with Formal Verification in Intel CoreTM i7 Processor Execution Engine Validation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 21st International Conference, CAV 2009, Grenoble, France, June 26 - July 2, 2009. Proceedings, pp. 414-429, 2009, Springer, 978-3-642-02657-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
26 | Ryad Benadjila, Olivier Billet, Shay Gueron, Matthew J. B. Robshaw |
The Intel AES Instructions Set and the SHA-3 Candidates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASIACRYPT ![In: Advances in Cryptology - ASIACRYPT 2009, 15th International Conference on the Theory and Application of Cryptology and Information Security, Tokyo, Japan, December 6-10, 2009. Proceedings, pp. 162-178, 2009, Springer, 978-3-642-10365-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
26 | Aart J. C. Bik, David L. Kreitzer, Xinmin Tian |
A Case Study on Compiler Optimizations for the Intel® CoreTM 2 Duo Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 36(6), pp. 571-591, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Optimization, Parallelization, Compilers, Code generation, Vectorization |
26 | Michael Buettner, Richa Prasad, Alanson P. Sample, Daniel J. Yeager, Ben Greenstein, Joshua R. Smith 0001, David Wetherall |
RFID sensor networks with the intel WISP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SenSys ![In: Proceedings of the 6th International Conference on Embedded Networked Sensor Systems, SenSys 2008, Raleigh, NC, USA, November 5-7, 2008, pp. 393-394, 2008, ACM, 978-1-59593-990-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
sensor networks, rfid |
26 | Christian Terboven, Dieter an Mey, Dirk Schmidl, Marcus Wagner |
First Experiences with Intel Cluster OpenMP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWOMP ![In: OpenMP in a New Era of Parallelism, 4th International Workshop, IWOMP 2008, West Lafayette, IN, USA, May 12-14, 2008, Proceedings, pp. 48-59, 2008, Springer, 978-3-540-79560-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Pawel Gepner |
Intel's Technology Vision and Products for HPC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCS (1) ![In: Computational Science - ICCS 2008, 8th International Conference, Kraków, Poland, June 23-25, 2008, Proceedings, Part I, pp. 42, 2008, Springer, 978-3-540-69383-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Sivakumar Radhakrishnan, Sundaram Chinthamani, Kai Cheng |
The Blackford Northbridge Chipset for the Intel 5000. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 27(2), pp. 22-33, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
platform architecture, dual-processor system, northbridge chipset, I/O bridges, FB-DIMM memory technology, low-power design, shared memory |
26 | Robert Ennals, Eric A. Brewer, Minos N. Garofalakis, Michael Shadle, Prashant Gandhi |
Intel Mash Maker: join the web. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMOD Rec. ![In: SIGMOD Rec. 36(4), pp. 27-33, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
visualization, personalization, data integration, mashup |
26 | Tommy Bojan, Igor Frumkin, Robert Mauri |
Intel First Ever Converged Core Functional Validation Experience: Methodologies, Challenges, Results and Learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), Common Challenges and Solutions, 5-6 December 2007, Austin, Texas, USA, pp. 85-90, 2007, IEEE Computer Society, 978-0-7695-3241-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Andrew M. Scott, Mark E. Schuelein, Marly Roncken, Jin-Jer Hwan, John Bainbridge, John R. Mawer, David L. Jackson, Andrew Bardsley |
Asynchronous on-Chip Communication: Explorations on the Intel PXA27x Processor Peripheral Bus. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2007), 12-14 March 2006, Berkeley, California, USA, pp. 60-72, 2007, IEEE Computer Society, 978-0-7695-2771-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Daniel A. Orozco, Liping Xue, Murat Bolat, Xiaoming Li, Guang R. Gao |
Experience of Optimizing FFT on Intel Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), Proceedings, 26-30 March 2007, Long Beach, California, USA, pp. 1-8, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Pawel Gepner, David L. Fraser, Michal Filip Kowalik |
Performance Evolution and Power Benefits of Cluster System Utilizing Quad-Core and Dual-Core Intel Xeon Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PPAM ![In: Parallel Processing and Applied Mathematics, 7th International Conference, PPAM 2007, Gdansk, Poland, September 9-12, 2007, Revised Selected Papers, pp. 20-28, 2007, Springer, 978-3-540-68105-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
dual-core processors, quad-core processors, parallel processing, benchmarks, HPC, multi-core processors |
26 | Alon Flaisher, Alon Gluska, Eli Singerman |
Case study: Integrating FV and DV in the Verification of the Intel CoreTM 2 Duo Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Formal Methods in Computer-Aided Design, 7th International Conference, FMCAD 2007, Austin, Texas, USA, November 11-14, 2007, Proceedings, pp. 192-195, 2007, IEEE Computer Society, 0-7695-3023-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Mitsuru Matsui, Junko Nakajima |
On the Power of Bitslice Implementation on Intel Core2 Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2007, 9th International Workshop, Vienna, Austria, September 10-13, 2007, Proceedings, pp. 121-134, 2007, Springer, 978-3-540-74734-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Fast Software Encryption, Bitslice, KASUMI, Core2, AES |
26 | Jiangjiang Liu 0002, Brian Bell, Tan Truong |
Analysis and Characterization of Intel Itanium Instruction Bundles for Improving VLIW Processor Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IMSCCS (1) ![In: Interdisciplinary and Multidisciplinary Research in Computer Science, IEEE CS Proceeding of the First International Multi-Symposium of Computer and Computational Sciences (IMSCCS|06), June 20-24, 2006, Zhejiang University, Hangzhou, China, Vol. 1, pp. 389-396, 2006, IEEE Computer Society, 0-7695-2581-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Stephen Wheat, Bob Jones |
Grids and network applications - Addressing high performance and grid challenges: Intel and CERN. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE SC2006 Conference on High Performance Networking and Computing, November 11-17, 2006, Tampa, FL, USA, pp. 248, 2006, ACM Press, 0-7695-2700-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Richard Uhlig, Gil Neiger, Dion Rodgers, Amy L. Santoni, Fernando C. M. Martins, Andrew V. Anderson, Steven M. Bennett, Alain Kägi, Felix H. Leung, Larry Smith 0001 |
Intel Virtualization Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computer ![In: Computer 38(5), pp. 48-56, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Itanium architecture, IA-32 architecture, virtual machines, computer architectures, software systems, virtualization technology |
26 | Vikram A. Saletore, Paul M. Stillwell Jr., John A. Wiegert, Phil Cayton, Jeff Gray 0001, Greg J. Regnier |
Efficient Direct User Level Sockets for an Intel XeonTM Processor Based TCP On-Load Engin. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), CD-ROM / Abstracts Proceedings, 4-8 April 2005, Denver, CO, USA, 2005, IEEE Computer Society, 0-7695-2312-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Greg J. Regnier, Dave B. Minturn, Gary L. McAlpine, Vikram A. Saletore, Annie P. Foong |
ETA: Experience with an Intel Xeon Processor as a Packet Processing Engine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 24(1), pp. 24-31, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Gilberto Contreras, Margaret Martonosi, Jinzhan Peng, Roy Ju, Guei-Yuan Lueh |
XTREM: a power simulator for the Intel XScale® core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'04), Washington, DC, USA, June 11-13, 2004, pp. 115-125, 2004, ACM, 1-58113-806-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
XORP, XScale, Java, power modeling, hardware performance counters, power measurements |
26 | Jasmeet Chhabra, Nandakishore Kushalnagar, Benjamin Metzler, Allen Sampson |
Sensor networks in intel fabrication plants. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SenSys ![In: Proceedings of the 2nd International Conference on Embedded Networked Sensor Systems, SenSys 2004, Baltimore, MD, USA, November 3-5, 2004, pp. 324, 2004, ACM, 1-58113-879-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
predictive maintenance, sensor networks, vibration analysis |
26 | Faye A. Briggs, Suresh Chittor, Kai Cheng |
Micro-architecture techniques in the intel E8870 scalable memory controller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WMPI ![In: Proceedings of the 3rd Workshop on Memory Performance Issues, in conjunction with the 31st International Symposium on Computer Architecture 2004, Munich, Germany, June 20, 2004, pp. 30-36, 2004, ACM, 1-59593-040-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
distributed coherency, transaction flows, scalability, memory latency |
26 | Chi-Keung Luk, Robert Muth, Harish Patil, Robert S. Cohn, P. Geoffrey Lowney |
Ispike: A Post-link Optimizer for the Intel®Itanium®Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: 2nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2004), 20-24 March 2004, San Jose, CA, USA, pp. 15-26, 2004, IEEE Computer Society, 0-7695-2102-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Karl Solchenbach |
From Science to Enterprise - Intel's Grid Activities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GCC ![In: Grid and Cooperative Computing - GCC 2004: Third International Conference, Wuhan, China, October 21-24, 2004. Proceedings, pp. 7, 2004, Springer, 3-540-23564-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Ramesh Radhakrishnan, Rizwan Ali, Garima Kochhar, Kalyana Chadalavada, Ramesh Rajagopalan, Jenwei Hsieh, Onur Celebioglu |
Evaluating Performance of BLAST on Intel Xeon and Itanium2 Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPA ![In: Parallel and Distributed Processing and Applications, Second InternationalSymposium, ISPA 2004, Hong Kong, China, December 13-15, 2004, Proceedings, pp. 1017-1023, 2004, Springer, 3-540-24128-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Scott Hamilton |
Intel Research Extends Moore's Law. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computer ![In: Computer 36(1), pp. 31-40, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Wan-Chun Ma, Chia-Lin Yang |
Using Intel Streaming SIMD Extensions for 3D Geometry Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Pacific Rim Conference on Multimedia ![In: Advances in Multimedia Information Processing - PCM 2002, Third IEEE Pacific Rim Conference on Multimedia, Hsinchu, Taiwan, December 16-18, 2002, Proceedings, pp. 1080-1087, 2002, Springer, 3-540-00262-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Robert P. Colwell, Gary Brown, Frank See |
Intel's College Hiring Methods and Recent Results. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: IEEE International Conference on Microelectronic Systems Education, MSE 1999, Arlington, Virginia, USA, July 19-21, 1999, pp. 94-96, 1999, IEEE Computer Society, 0-7695-0312-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
26 | Aaron B. Brown, Margo I. Seltzer |
Operating System Benchmarking in the Wake of Lmbench: A Case Study of the Performance of NetBSD on Intel x86 Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS ![In: Proceedings of the 1997 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, Seattle, Washington, USA, June 15-18, 1997, pp. 214-224, 1997, ACM, 0-89791-909-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
26 | Meenakshi Arunachalam, Alok N. Choudhary, Brad Rullman |
Implementation and Evaluation of Prefetching in the Intel Paragon Parallel File System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '96, The 10th International Parallel Processing Symposium, April 15-19, 1996, Honolulu, Hawaii, USA, pp. 554-559, 1996, IEEE Computer Society, 0-8186-7255-2. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
26 | John N. Shadid, Scott A. Hutchinson, Harry Moffat, Gary L. Hennigan, Bruce Hendrickson, Robert W. Leland |
A 65+ Gflops/s unstructured finite element simulation of chemically reacting flows on the Intel Paragon. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings Supercomputing '94, Washington, DC, USA, November 14-18, 1994, pp. 673-679, 1994, IEEE Computer Society, 0-8186-6605-6. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
26 | David E. Womble, David S. Greenberg, Stephen R. Wheat, Robert E. Benner, Marc S. Ingber, Greg Henry, Satya Gupta |
Applications of boundary element methods on the Intel Paragon. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings Supercomputing '94, Washington, DC, USA, November 14-18, 1994, pp. 680-684, 1994, IEEE Computer Society, 0-8186-6605-6. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
26 | James C. French, Terrence W. Pratt, Mriganka Das |
Performance Measurement of a Parallel Input/Output System for the Intel iPSC/2 Hypercube. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS ![In: Proceedings of the 1991 ACM SIGMETRICS conference on Measurement and modeling of computer systems, San Diego, California, USA, May 21-24, 1991, pp. 178-187, 1991, ACM, 0-89791-392-2. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
26 | Robert P. Colwell, Edward F. Gehringer, E. Douglas Jensen |
Performance Effects of Architectural Complexity in the Intel 432. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Comput. Syst. ![In: ACM Trans. Comput. Syst. 6(3), pp. 296-339, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
25 | Azalea Raad, Luc Maranget, Viktor Vafeiadis |
Extending Intel-x86 consistency and persistency: formalising the semantics of Intel-x86 memory types and non-temporal stores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Proc. ACM Program. Lang. ![In: Proc. ACM Program. Lang. 6(POPL), pp. 1-31, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
25 | Galen M. Shipman, Sriram Swaminarayan, Gary Grider, Jim Lujan, R. Joseph Zerr |
Early Performance Results on 4th Gen Intel(R) Xeon (R) Scalable Processors with DDR and Intel(R) Xeon(R) processors, codenamed Sapphire Rapids with HBM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2211.05712, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
25 | Fabian Boemer, Sejun Kim, Gelila Seifu, Fillipe D. M. de Souza, Vinodh Gopal |
Intel HEXL: Accelerating Homomorphic Encryption with Intel AVX512-IFMA52. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2103.16400, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
25 | Fabian Boemer, Sejun Kim, Gelila Seifu, Fillipe D. M. de Souza, Vinodh Gopal |
Intel HEXL: Accelerating Homomorphic Encryption with Intel AVX512-IFMA52. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2021, pp. 420, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
25 | Fabian Boemer, Sejun Kim, Gelila Seifu, Fillipe D. M. de Souza, Vinodh Gopal |
Intel HEXL: Accelerating Homomorphic Encryption with Intel AVX512-IFMA52. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WAHC@CCS ![In: WAHC '21: Proceedings of the 9th on Workshop on Encrypted Computing & Applied Homomorphic Cryptography, Virtual Event, Korea, 15 November 2021, pp. 57-62, 2021, WAHC@ACM, 978-1-4503-8656-2. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
25 | Dounia Khaldi, Yuanke Luo, Bing Yu, Alexey Sotkin, Bruno Morais, Milind Girkar |
Extending LLVM IR for DPC++ Matrix Support: A Case Study with Intel® Advanced Matrix Extensions (Intel® AMX). ![Search on Bibsonomy](Pics/bibsonomy.png) |
LLVM-HPC@SC ![In: 7th IEEE/ACM Workshop on the LLVM Compiler Infrastructure in HPC, LLVM-HPC@SC 2021, St. Louis, MO, USA, November 14, 2021, pp. 20-26, 2021, IEEE, 978-1-6654-1134-9. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
25 | Roktaek Lim, Yeongha Lee, Raehyun Kim, Jaeyoung Choi, Myungho Lee |
Auto-tuning GEMM kernels on the Intel KNL and Intel Skylake-SP processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 75(12), pp. 7895-7908, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
25 | Gina Mathew, S. Sindhu Ramachandran, V. S. Suchithra |
Lung Nodule Detection from low dose CT scan using Optimization on Intel Xeon and Core processors with Intel Distribution of OpenVINO Toolkit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TENCON ![In: TENCON 2019 - 2019 IEEE Region 10 Conference (TENCON), Kochi, India, October 17-20, 2019, pp. 1783-1788, 2019, IEEE, 978-1-7281-1895-6. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
25 | Soyeon Park, Sangho Lee 0001, Wen Xu 0002, Hyungon Moon, Taesoo Kim |
libmpk: Software Abstraction for Intel Memory Protection Keys (Intel MPK). ![Search on Bibsonomy](Pics/bibsonomy.png) |
USENIX Annual Technical Conference ![In: 2019 USENIX Annual Technical Conference, USENIX ATC 2019, Renton, WA, USA, July 10-12, 2019, pp. 241-254, 2019, USENIX Association. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
25 | Somnath Chakrabarti, Matthew Hoekstra, Dmitrii Kuvaiskii, Mona Vij |
Scaling Intel® Software Guard Extensions Applications with Intel® SGX Card. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HASP@ISCA ![In: Proceedings of the 8th International Workshop on Hardware and Architectural Support for Security and Privacy, HASP@ISCA 2019, June 23, 2019., pp. 6:1-6:9, 2019, ACM, 978-1-4503-7226-8. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
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