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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 216 occurrences of 168 keywords
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Results
Found 242 publication records. Showing 242 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
95 | Lisa Higham, LillAnne Jackson, Jalal Kawash |
Capturing Register and Control Dependence in Memory Consistency Models with Applications to the Itanium Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DISC ![In: Distributed Computing, 20th International Symposium, DISC 2006, Stockholm, Sweden, September 18-20, 2006, Proceedings, pp. 164-178, 2006, Springer, 3-540-44624-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Multiprocessor memory consistency, register and control dependency, process coordination, Itanium |
95 | Lisa Higham, LillAnne Jackson |
Translating between itanium and sparc memory consistency models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPAA ![In: SPAA 2006: Proceedings of the 18th Annual ACM Symposium on Parallelism in Algorithms and Architectures, Cambridge, Massachusetts, USA, July 30 - August 2, 2006, pp. 170-179, 2006, ACM, 1-59593-452-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
multiprocessors, program transformations, memory consistency models, sparc, itanium |
84 | Lisa Higham, LillAnne Jackson, Jalal Kawash |
Programmer-Centric Conditions for Itanium Memory Consistency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDCN ![In: Distributed Computing and Networking, 8th International Conference, ICDCN 2006, Guwahati, India, December 27-30, 2006., pp. 58-69, 2006, Springer, 3-540-68139-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Programmer-centric memory consistency, Itanium multiprocessor |
84 | Bruce Greer, John Harrison 0001, Greg Henry, Wei Wayne Li, Ping Tak Peter Tang |
Scientific computing on the Itanium processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the 2001 ACM/IEEE conference on Supercomputing, Denver, CO, USA, November 10-16, 2001, CD-ROM, pp. 41, 2001, ACM, 1-58113-293-X. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
fused multiply-add, itanium (TM) processor, linear algebra, Intel, EPIC, transcendental functions |
83 | Tatiana Shpeisman, Guei-Yuan Lueh, Ali-Reza Adl-Tabatabai |
Just-In-Time Java? Compilation for the Itanium® Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 22-25 September 2002, Charlottesville, VA, USA, pp. 249-258, 2002, IEEE Computer Society, 0-7695-1620-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
72 | Perry H. Wang, Jamison D. Collins, Hong Wang 0003, Dongkeun Kim, Bill Greene, Kai-Ming Chan, Aamir B. Yunus, Terry Sych, Stephen F. Moore, John Paul Shen |
Helper threads via virtual multithreading on an experimental itanium® 2 processor-based platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2004, Boston, MA, USA, October 7-13, 2004, pp. 144-155, 2004, ACM, 1-58113-804-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
DB2 database, cache miss prefetching, itanium processor, switch-on-event, multithreading, helper thread, PAL |
71 | Chih Jeng Kenneth Tan, David Hagan, Matthew F. Dixon |
A Performance Comparison of Matrix Solvers on Compaq Alpha, Intel Itanium, and Intel Itanium II Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCSA (1) ![In: Computational Science and Its Applications - ICCSA 2003, International Conference, Montreal, Canada, May 18-21, 2003, Proceedings, Part I, pp. 818-827, 2003, Springer, 3-540-40155-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Systems of linear algebraic equations, Architecture specific tuning, Linear solver |
71 | Kazuyoshi Furukawa, Masahiko Takenaka, Kouichi Itoh |
A Fast RSA Implementation on Itanium 2 Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICICS ![In: Information and Communications Security, 8th International Conference, ICICS 2006, Raleigh, NC, USA, December 4-7, 2006, Proceedings, pp. 507-518, 2006, Springer, 3-540-49496-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Ita- 2, RSA, Montgomery multiplication, software implementation |
71 | Leonid Baraz, Tevi Devor, Orna Etzion, Shalom Goldenberg, Alex Skaletsky, Yun Wang, Yigel Zemach |
IA-32 Execution Layer: a two-phase dynamic translator designed to support IA-32 applications on Itanium-based systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 36th Annual International Symposium on Microarchitecture, San Diego, CA, USA, December 3-5, 2003, pp. 191-204, 2003, IEEE Computer Society, 0-7695-2043-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Intel |
71 | Alex Settle, Daniel A. Connors, Gerolf Hoflehner, Daniel M. Lavery |
Optimization for the Intel® Itanium ®Architectur Register Stack. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: 1st IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2003), 23-26 March 2003, San Francisco, CA, USA, pp. 115-124, 2003, IEEE Computer Society, 0-7695-1913-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
60 | Gerrit Saylor, Badriddine Khessib |
Large scale Itanium® 2 processor OLTP workload characterization and optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DaMoN ![In: Workshop on Data Management on New Hardware, DaMoN 2006, Chicago, Illinois, USA, June 25, 2006, pp. 3, 2006, ACM, 1-59593-466-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
cache coherency, data partitioning, performance characterization, profile guided optimization, OLTP, software optimization, Itanium, ccNUMA |
60 | Harish Patil, Robert S. Cohn, Mark Charney, Rajiv Kapoor, Andrew Sun, Anand Karunanidhi |
Pinpointing Representative Portions of Large Intel® Itanium® Programs with Dynamic Instrumentation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 4-8 December 2004, Portland, OR, USA, pp. 81-92, 2004, IEEE Computer Society, 0-7695-2126-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
60 | Wenlong Li, Haibo Lin, Yu Chen, Zhizhong Tang |
Increasing Software-Pipelined Loops in the Itanium-Like Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPA ![In: Parallel and Distributed Processing and Applications, Second InternationalSymposium, ISPA 2004, Hong Kong, China, December 13-15, 2004, Proceedings, pp. 947-951, 2004, Springer, 3-540-24128-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
60 | Perry H. Wang, Hong Wang 0003, Jamison D. Collins, Ed Grochowski, Ralph-Michael Kling, John Paul Shen |
Memory Latency-Tolerance Approaches for Itanium Processors: Out-of-Order Execution vs. Speculative Precomputation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), Boston, Massachusettes, USA, February 2-6, 2002, pp. 187-196, 2002, IEEE Computer Society, 0-7695-1525-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
60 | Terry Lyon, Eric Delano, Cameron McNairy, Dean Mulla |
Data Cache Design Considerations for the Itanium® 2 Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 20th International Conference on Computer Design (ICCD 2002), VLSI in Computers and Processors, 16-18 September 2002, Freiburg, Germany, Proceedings, pp. 356-, 2002, IEEE Computer Society, 0-7695-1700-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
60 | Alban Douillet, José Nelson Amaral, Guang R. Gao |
Fine-Grain Stacked Register Allocation for the Itanium Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCPC ![In: Languages and Compilers for Parallel Computing, 15th Workshop, LCPC 2002, College Park, MD, USA, July 25-27, 2002, Revised Papers, pp. 344-361, 2002, Springer, 3-540-30781-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
60 | John Crawford |
Guest Editor's Introduction: Introducing the Itanium Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 20(5), pp. 9-11, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
48 | Utpal Desai, Simon M. Tam, Robert Kim, Ji Zhang, Stefan Rusu |
Itanium processor clock design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2000 International Symposium on Physical Design, ISPD 2000, San Diego, CA, USA, April 9-12, 2000, pp. 94-98, 2000, ACM, 1-58113-191-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Itanium processor, deskew, on-die-clock-shrink, clock distribution, IA-64 |
48 | Noah Snavely, Saumya K. Debray, Gregory R. Andrews |
Unpredication, Unscheduling, Unspeculation: Reverse Engineering Itanium Executables. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 31(2), pp. 99-115, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
EPIC architectures, Reverse engineering, speculation, code optimization, predication |
48 | Roland E. Wunderlich, James C. Hoe |
In-system FPGA prototyping of an itanium microarchitecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004, pp. 255, 2004, ACM, 1-58113-829-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
48 | Gerolf Hoflehner, Knud Kirkegaard, Rod Skinner, Daniel M. Lavery, Yong-Fong Lee, Wei Li 0015 |
Compiler Optimizations for Transaction Processing Workloads on Itanium® Linux Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 4-8 December 2004, Portland, OR, USA, pp. 294-303, 2004, IEEE Computer Society, 0-7695-2126-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
48 | Chi-Keung Luk, Robert Muth, Harish Patil, Robert S. Cohn, P. Geoffrey Lowney |
Ispike: A Post-link Optimizer for the Intel®Itanium®Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: 2nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2004), 20-24 March 2004, San Jose, CA, USA, pp. 15-26, 2004, IEEE Computer Society, 0-7695-2102-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
48 | Roland E. Wunderlich, James C. Hoe |
In-System FPGA Prototyping of an Itanium Microarchitecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings, pp. 288-294, 2004, IEEE Computer Society, 0-7695-2231-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
48 | Cameron McNairy, Don Soltis |
Itanium 2 Processor Microarchitecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 23(2), pp. 44-55, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
48 | Jean-Francois Collard, Daniel M. Lavery |
Optimizations to Prevent Cache Penalties for the Intel ® Itanium 2 Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: 1st IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2003), 23-26 March 2003, San Francisco, CA, USA, pp. 105-114, 2003, IEEE Computer Society, 0-7695-1913-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
48 | Noah Snavely, Saumya K. Debray, Gregory R. Andrews |
Unscheduling, Unpredication, Unspeculation: Reverse Engineering Itanium Executables. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WCRE ![In: 10th Working Conference on Reverse Engineering, WCRE 2003, Victoria, Canada, November 13-16, 2003, pp. 4-13, 2003, IEEE Computer Society, 0-7695-2027-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
48 | Haibo Lin, Wenlong Li, Zhizhong Tang |
Overcoming Static Register Pressure for Software Pipelining in the Itanium Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APPT ![In: Advanced Parallel Programming Technologies, 5th International Workshop, APPT 2003, Xiamen, China, September 17-19, 2003, Proceedings, pp. 109-113, 2003, Springer, 3-540-20054-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
48 | R. David Weldon, Steven S. Chang, Hong Wang 0003, Gerolf Hoflehner, Perry H. Wang, Daniel M. Lavery, John Paul Shen |
Quantitative Evaluation of the Register Stack Engine and Optimizations for Future Itanium Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Interaction between Compilers and Computer Architectures ![In: 6th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-6 2002), 3 February 2002, Boston, MA, USA, pp. 57-67, 2002, IEEE Computer Society, 0-7695-1534-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
48 | Kazuhisa Ishizaka, Takamichi Miyamoto, Jun Shirako, Motoki Obata, Keiji Kimura, Hironori Kasahara |
Performance of OSCAR Multigrain Parallelizing Compiler on SMP Servers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCPC ![In: Languages and Compilers for High Performance Computing, 17th International Workshop, LCPC 2004, West Lafayette, IN, USA, September 22-24, 2004, Revised Selected Papers, pp. 319-331, 2004, Springer, 3-540-28009-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
36 | Sebastian Winkel, Rakesh Krishnaiyer, Robyn Sampson |
Latency-tolerant software pipelining in a production compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: Sixth International Symposium on Code Generation and Optimization (CGO 2008), April 5-9, 2008, Boston, MA, USA, pp. 104-113, 2008, ACM, 978-1-59593-978-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
latency-tolerant scheduling, load clustering, compiler, code generation, prefetching, software pipelining, modulo scheduling, memory latency, memory-level parallelism, itanium, epic |
36 | Eric S. Fetzer |
Using Adaptive Circuits to Mitigate Process Variations in a Microprocessor Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 23(6), pp. 476-483, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
dual core, Itanium microprocessor, Montecito, adaptive circuits, cache safe technology, active clock deskew, process variation, power measurement |
36 | Ivan D. Baev, Richard E. Hank, David H. Gross |
Prematerialization: reducing register pressure for free. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), Seattle, Washington, USA, September 16-20, 2006, pp. 285-294, 2006, ACM, 1-59593-264-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
rematerialization, register allocation, VLIW, Itanium, register pressure |
36 | Wei-Chung Hsu, Howard Chen 0002, Pen-Chung Yew, Dong-yuan Chen |
On the Predictability of Program Behavior Using Different Input Data Sets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Interaction between Compilers and Computer Architectures ![In: 6th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-6 2002), 3 February 2002, Boston, MA, USA, pp. 45-53, 2002, IEEE Computer Society, 0-7695-1534-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
SPEC2000int, profiles, performance simulation, Itanium, profile-based optimization |
36 | Darshan Desai, Gerolf Hoflehner, Arun Kejariwal, Daniel M. Lavery, Alexandru Nicolau, Alexander V. Veidenbaum, Cameron McNairy |
Performance Characterization of Itanium® 2-Based Montecito Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPEC Benchmark Workshop ![In: Computer Performance Evaluation and Benchmarking, SPEC Benchmark Workshop 2009, Austin, TX, USA, January 25, 2009. Proceedings, pp. 36-56, 2009, Springer, 978-3-540-93798-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
36 | Jiangjiang Liu 0002, Brian Bell, Tan Truong |
Analysis and Characterization of Intel Itanium Instruction Bundles for Improving VLIW Processor Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IMSCCS (1) ![In: Interdisciplinary and Multidisciplinary Research in Computer Science, IEEE CS Proceeding of the First International Multi-Symposium of Computer and Computational Sciences (IMSCCS|06), June 20-24, 2006, Zhejiang University, Hangzhou, China, Vol. 1, pp. 389-396, 2006, IEEE Computer Society, 0-7695-2581-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
36 | Cameron McNairy, Rohit Bhatia |
Montecito: A Dual-Core, Dual-Thread Itanium Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 25(2), pp. 10-20, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Reliability, Power Management, Cache memories, Multithreaded processors, Testing and Fault-Tolerance |
36 | Stefan Rusu, Harry Muljono, Brian S. Cherkauer |
Itanium 2 Processor 6M: Higher Frequency and Larger L3 Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 24(2), pp. 10-18, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
36 | Carl Scafidi, J. Douglas Gibson, Rohit Bhatia |
Validating the Itanium 2 Exception Control Unit: A Unit-Level Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 21(2), pp. 94-101, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
36 | Sebastian Winkel |
Exploring the Performance Potential of Itanium® Processors with ILP-based Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: 2nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2004), 20-24 March 2004, San Jose, CA, USA, pp. 189-200, 2004, IEEE Computer Society, 0-7695-2102-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
36 | Kuang-Kuo Lin, Sudhakar Kale, Aditi Nigam |
Methodology for Automated Layout Migration for 90 nm Itanium®2 Processor Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 5th International Symposium on Quality of Electronic Design (ISQED 2004), 22-24 March 2004, San Jose, CA, USA, pp. 31-35, 2004, IEEE Computer Society, 0-7695-2093-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
36 | John W. Sias, Sain-Zee Ueng, Geoff A. Kent, Ian M. Steiner, Erik M. Nystrom, Wen-mei W. Hwu |
Field-testing IMPACT EPIC research results in Itanium 2. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 31st International Symposium on Computer Architecture (ISCA 2004), 19-23 June 2004, Munich, Germany, pp. 26-39, 2004, IEEE Computer Society, 0-7695-2143-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
36 | James W. Thomas |
Inlining of Mathematical Functions in HP-UX for Itanium ® 2. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: 1st IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2003), 23-26 March 2003, San Francisco, CA, USA, pp. 135-148, 2003, IEEE Computer Society, 0-7695-1913-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
36 | Xinmin Tian, Milind Girkar, Sanjiv Shah, Douglas Armstrong, Ernesto Su, Paul Petersen |
Compiler and Runtime Support for Running OpenMP Programs on Pentium-and Itanium-Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HIPS ![In: Eighth International Workshop on High-Level Parallel Programming Models and Supportive Environments (HIPS'03), April 22-22, 2003, Nice, France, pp. 47-55, 2003, IEEE Computer Society, 0-7695-1880-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Hyper-Threading technology, Parallelization, OpenMP, compiler optimization, shared-memory multiprocessor, thread-level parallelism |
36 | Xinmin Tian, Milind Girkar, Sanjiv Shah, Douglas Armstrong, Ernesto Su, Paul Petersen |
Compiler and Runtime Support for Running OpenMP Programs on Pentium- and Itanium-Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 22-26 April 2003, Nice, France, CD-ROM/Abstracts Proceedings, pp. 130, 2003, IEEE Computer Society, 0-7695-1926-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Hyper-Threading technology, Parallelization, OpenMP, compiler optimization, shared-memory multiprocessor, thread-level parallelism |
36 | Yue Yang, Ganesh Gopalakrishnan, Gary Lindstrom, Konrad Slind |
Analyzing the Intel Itanium Memory Ordering Rules Using Logic Programming and SAT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHARME ![In: Correct Hardware Design and Verification Methods, 12th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2003, L'Aquila, Italy, October 21-24, 2003, Proceedings, pp. 81-95, 2003, Springer, 3-540-20363-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
36 | Liu Yang, Sun Chan, Guang R. Gao, Roy Ju, Guei-Yuan Lueh, Zhaoqing Zhang |
Inter-procedural stacked register allocation for itanium® like architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 17th Annual International Conference on Supercomputing, ICS 2003, San Francisco, CA, USA, June 23-26, 2003, pp. 215-225, 2003, ACM, 1-58113-733-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
hot region, inter-procedural stacked register allocation, quota assignment, register allocation, hotspot |
36 | Jason Stinson, Stefan Rusu |
A 1.5GHz third generation itanium® 2 processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 706-709, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
on-die cache, reliability, test, design methodology, processor |
36 | William A. Samaras, Naveen Cherukuri, Srinivas Venkataraman |
The IA-64 Itanium Processor Cartridge. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 21(1), pp. 82-89, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
36 | Youngsoo Choi, Allan D. Knies, Luke Gerke, Tin-Fook Ngai |
The impact of if-conversion and branch prediction on program execution on the Intel Itanium processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 34th Annual International Symposium on Microarchitecture, Austin, Texas, USA, December 1-5, 2001, pp. 182-191, 2001, ACM/IEEE Computer Society, 0-7695-1369-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
36 | Harsh Sharangpani, Ken Arora |
Itanium Processor Microarchitecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 20(5), pp. 24-43, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
36 | Nhon T. Quach |
High Availability and Reliability in the Itanium Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 20(5), pp. 61-69, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
36 | Somnath Ghosh, Abhay Kanhere, Rakesh Krishnaiyer, Dattatraya Kulkarni, Wei Li 0015, Chu-Cheow Lim, John Ng |
Integrating High-Level Optimizations in a Production Compiler: Design and Implementation Experience. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 12th International Conference, CC 2003, Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2003, Warsaw, Poland, April 7-11, 2003, Proceedings, pp. 303-319, 2003, Springer, 3-540-00904-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
24 | Richard Uhlig, Gil Neiger, Dion Rodgers, Amy L. Santoni, Fernando C. M. Martins, Andrew V. Anderson, Steven M. Bennett, Alain Kägi, Felix H. Leung, Larry Smith 0001 |
Intel Virtualization Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computer ![In: Computer 38(5), pp. 48-56, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Itanium architecture, IA-32 architecture, virtual machines, computer architectures, software systems, virtualization technology |
24 | Patrick Carribault, Albert Cohen 0001 |
Applications of storage mapping optimization to register promotion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 18th Annual International Conference on Supercomputing, ICS 2004, Saint Malo, France, June 26 - July 01, 2004, pp. 247-256, 2004, ACM, 1-58113-839-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
array contraction, array folding, scheduling, pattern matching, string matching, tiling, blocking, itanium, register promotion |
24 | Branimir Malnar, Goran Zelic |
Timing closure of clock enable signals on a 32 nm Intel Itanium processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MIPRO ![In: 41st International Convention on Information and Communication Technology, Electronics and Microelectronics, MIPRO 2018, Opatija, Croatia, May 21-25, 2018, pp. 78-83, 2018, IEEE, 978-953-233-095-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Anys Bacha, Radu Teodorescu |
Dynamic reduction of voltage margins by leveraging on-chip ECC in Itanium II processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: The 40th Annual International Symposium on Computer Architecture, ISCA'13, Tel-Aviv, Israel, June 23-27, 2013, pp. 297-307, 2013, ACM, 978-1-4503-2079-5. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
24 | Reid J. Riedlinger, Ron Arnold, Larry Biro, William J. Bowhill, Jason Crop, Kevin Duda, Eric S. Fetzer, Olivier Franza, Tom Grutkowski, Casey Little, Charles Morganti, Gary Moyer, Ashley O. Munch, Mahalingam Nagarajan, Cheolmin Park, Christopher Poirier, Bill Repasky, Edi Roytman, Tejpal Singh, Matthew W. Stefaniw |
A 32 nm, 3.1 Billion Transistor, 12 Wide Issue Itanium® Processor for Mission-Critical Servers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 47(1), pp. 177-193, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
24 | Steven R. Undy |
Poulson: An 8 core 32 nm next generation Intel® Itanium® processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Hot Chips Symposium ![In: 2011 IEEE Hot Chips 23 Symposium (HCS), Stanford, CA, USA, August 17-19, 2011, pp. 1-22, 2011, IEEE, 978-1-4673-8877-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
24 | Steve Richfield |
Dealing with the "itanium effect" (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, FPGA 2011, Monterey, California, USA, February 27, March 1, 2011, pp. 277, 2011, ACM, 978-1-4503-0554-9. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
24 | Reid J. Riedlinger, Rohit Bhatia, Larry Biro, William J. Bowhill, Eric S. Fetzer, Paul E. Gronowski, Tom Grutkowski |
A 32nm 3.1 billion transistor 12-wide-issue Itanium® processor for mission-critical servers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2011, Digest of Technical Papers, San Francisco, CA, USA, 20-24 February, 2011, pp. 84-86, 2011, IEEE, 978-1-61284-303-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
24 | Dilip K. Bhavsar, Steve Poehlman |
Test access and the testability features of the Poulson multi-core Intel Itanium® processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2011 IEEE International Test Conference, ITC 2011, Anaheim, CA, USA, September 20-22, 2011, pp. 1-8, 2011, IEEE Computer Society, 978-1-4577-0153-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
24 | Pankaj Pant, Joshua Zelman, Glenn Colón-Bonet, Jennifer Flint, Steve Yurash |
Lessons from at-speed scan deployment on an Intel® Itanium® microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2011 IEEE International Test Conference, ITC 2010, Austin, TX, USA, November 2-4, 2010, pp. 526-535, 2010, IEEE Computer Society, 978-1-4244-7206-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
24 | Blaine A. Stackhouse, Sal Bhimji, Chris Bostak, Dave Bradley, Brian S. Cherkauer, Jayen Desai, Erin Francom, Mike Gowan, Paul E. Gronowski, Dan Krueger, Charles Morganti, Steve Troyer |
A 65 nm 2-Billion Transistor Quad-Core Itanium Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 44(1), pp. 18-31, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
24 | Andrew Allen, Jay Desai, Frank Verdico, Ferd Anderson, David Mulvihill, Dan Krueger |
Dynamic frequency-switching clock system on a quad-core Itanium® processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2009, Digest of Technical Papers, San Francisco, CA, USA, 8-12 February, 2009, pp. 62-63, 2009, IEEE, 978-1-4244-3458-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
24 | Blaine A. Stackhouse, Brian S. Cherkauer, Michael K. Gowan, Paul E. Gronowski, Chris Lyles |
A 65nm 2-Billion-Transistor Quad-Core Itanium® Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2008 IEEE International Solid-State Circuits Conference, ISSCC 2008, Digest of Technical Papers, San Francisco, CA, USA, February 3-7, 2008, pp. 92-93, 2008, IEEE, 978-1-4244-2010-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Dan Krueger, Erin Francom, Jack Langsdorf |
Circuit Design for Voltage Scaling and SER Immunity on a Quad-Core Itanium® Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2008 IEEE International Solid-State Circuits Conference, ISSCC 2008, Digest of Technical Papers, San Francisco, CA, USA, February 3-7, 2008, pp. 94-95, 2008, IEEE, 978-1-4244-2010-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Jamel Tayeb |
Optimisation des performances et de la consommation de puissance électrique pour architecture Intel ltanium/EPIC. (Performance and Energy Optimization for Intel Itanium/EPIC architecture for Virtual Machine Support). ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2008 |
RDF |
|
24 | Arun Kejariwal, Gerolf Hoflehner, Darshan Desai, Daniel M. Lavery, Alexandru Nicolau, Alexander V. Veidenbaum |
Comparative characterization of SPEC CPU2000 and CPU2006 on Itanium architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS ![In: Proceedings of the 2007 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, SIGMETRICS 2007, San Diego, California, USA, June 12-16, 2007, pp. 361-362, 2007, ACM, 978-1-59593-639-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
SPEC CPU benchmarks, performance evaluation, caches, branch prediction |
24 | Eric S. Fetzer, David M. Dahle, Casey Little, Kevin Safford |
The Parity protected, multithreaded register files on the 90-nm itanium microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 41(1), pp. 246-255, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Rich McGowen, Christopher Poirier, Chris Bostak, Jim Ignowski, Mark Millican, Warren H. Parks, Samuel Naffziger |
Power and temperature control on a 90-nm Itanium family processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 41(1), pp. 229-237, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Samuel Naffziger, Blaine A. Stackhouse, Tom Grutkowski, Doug Josephson, Jayen Desai, Elad Alon, Mark Horowitz |
The implementation of a 2-core, multi-threaded itanium family processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 41(1), pp. 197-209, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Tim C. Fischer, Jayen Desai, Bruce Andrew Doyle, Samuel Naffziger, Ben Patella |
A 90-nm variable frequency clock system for a power-managed itanium architecture processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 41(1), pp. 218-228, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Lisa Higham, LillAnne Jackson, Jalal Kawash |
What is Itanium Memory Consistency from the Programmer's Point of View? ![Search on Bibsonomy](Pics/bibsonomy.png) |
TV@FLoC ![In: Proceedings of the Thread Verification Workshop, TV@FLoC 2006, Seattle, WA, USA, August 21-22, 2006, pp. 63-84, 2006, Elsevier. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | William Jalby, Christophe Lemuet, Sid Ahmed Ali Touati |
An efficient memory operations optimization technique for vector loops on Itanium 2 processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Concurr. Comput. Pract. Exp. ![In: Concurr. Comput. Pract. Exp. 18(11), pp. 1485-1508, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Jonathan Chang, Stefan Rusu, Jonathan Shoemaker, Simon Tam 0001, Ming Huang, Mizan Haque, Siufu Chiu, Kevin Truong, Mesbah Karim, Gloria Leong, Kiran Desai, Richard Goe, Sandhya Kulkarni |
A 130-nm triple-Vt 9-MB third-level on-die cache for the 1.7-GHz Itanium® 2 processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 40(1), pp. 195-203, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
24 | Markus Mock, Ricardo Villamarín-Salomón, José Baiocchi |
An empirical study of data speculation use on the Intel Itanium 2 processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Interaction between Compilers and Computer Architectures ![In: 9th Annual Workshop on Interaction between Compilers and Computer Architectures, INTERACT-9 2005, San Francisco, California, USA, February 13, 2005, pp. 22-33, 2005, IEEE Computer Society, 0-7695-2321-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
24 | Charles Gray, Matthew Chapman, Peter Chubb, David Mosberger, Gernot Heiser |
Itanium - A System Implementor's Tale(Awarded General Track Best Student Paper Award!). ![Search on Bibsonomy](Pics/bibsonomy.png) |
USENIX Annual Technical Conference, General Track ![In: Proceedings of the 2005 USENIX Annual Technical Conference, April 10-15, 2005, Anaheim, CA, USA, pp. 265-278, 2005, USENIX. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP BibTeX RDF |
|
24 | Simon Tam 0001, Rahul Dilip Limaye, Utpal Nagarji Desai |
Clock generation and distribution for the 130-nm Itanium® 2 processor with 6-MB on-die L3 cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 39(4), pp. 636-642, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
24 | Dong-yuan Chen, Lixia Liu, Roy Dz-Ching Ju, Chen Fu, Shuxin Yang, Chengyong Wu |
Efficient Modeling of Itanium Architecture during Instruction Scheduling using Extended Finite State Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Instr. Level Parallelism ![In: J. Instr. Level Parallelism 6, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
24 | Daniel J. Magenheimer, Thomas W. Christian |
vBlades: Optimized Paravirtualization for the Itanium Processor Family. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Virtual Machine Research and Technology Symposium ![In: Proceedings of the 3rd Virtual Machine Research and Technology Symposium, May 6-7, 2004, San Jose, CA, USA, pp. 73-82, 2004, USENIX. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
24 | Wilfredo E. Lugo-Beauchamp, Kennie Cruz, Carmen L. Carvajal-Jiménez, Wilson Rivera |
Performance of hyperspectral imaging algorithms using itanium architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits, Signals, and Systems ![In: Proceedings of the Second IASTED International Conference on Circuits, Signals, and Systems, Clearwater Beach, FL, USA, November 28, 2004 - December 1, 2004, pp. 327-332, 2004, IASTED/ACTA Press. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
24 | Marius Cornea |
Software implementations of division and square root operations for Intel® Itanium® processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WCAE ![In: Proceedings of the 2004 workshop on Computer architecture education - Held in conjunction with the 31st International Symposium on Computer Architecture, WCAE@ISCA 2004, Munich, Germany, June 19, 2004, pp. 17, 2004, ACM, 978-1-4503-4733-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
24 | Sebastian Winkel |
Optimal global instruction scheduling for the Itanium processor architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2004 |
RDF |
|
24 | Stefan Rusu, Jason Stinson, Simon Tam 0001, Justin Leung, Harry Muljono, Brian S. Cherkauer |
A 1.5-GHz 130-nm Itanium® 2 Processor with 6-MB on-die L3 cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 38(11), pp. 1887-1895, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
24 | U. Andersson, P. Ekman, Per Öster |
Performance and performance counters on the Itanium 2 - A benchmarking case study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARCO ![In: Parallel Computing: Software Technology, Algorithms, Architectures and Applications, PARCO 2003, Dresden, Germany, pp. 517-524, 2003, Elsevier, 0-444-51689-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP BibTeX RDF |
|
24 | Marius Cornea, John Harrison 0001, Ping Tak Peter Tang |
Intel® Itanium® floating-point architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WCAE ![In: Proceedings of the 2003 workshop on Computer architecture education - Held in conjunction with the 30th International Symposium on Computer Architecture, WCAE@ISCA 2003, San Diego, California, USA, June 8, 2003, pp. 3, 2003, ACM, 978-1-4503-4732-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
24 | Samuel D. Naffziger, Glenn Colón-Bonet, Timothy C. Fischer, Reid J. Riedlinger, Thomas J. Sullivan, Tom Grutkowski |
The implementation of the Itanium 2 microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 37(11), pp. 1448-1460, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
24 | Don Weiss, John J. Wuu, Victor Chin |
The on-chip 3-MB subarray-based third-level cache on an Itanium microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 37(11), pp. 1523-1529, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
24 | Eric S. Fetzer, Mark Gibson, Anthony Klein, Naomi Calick, Chengyu Zhu, Eric Busta, Baker Mohammad |
A fully bypassed six-issue integer datapath and register file on the Itanium-2 microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 37(11), pp. 1433-1440, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
24 | Bruce Greer, John Harrison 0001, Greg Henry, Wei Wayne Li, Ping Tak Peter Tang |
Scientific computing on the Itanium® processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. Program. ![In: Sci. Program. 10(4), pp. 329-337, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
24 | Chih Jeng Kenneth Tan |
Performance Evaluation of Matrix Solvers on Compaq Alpha and Intel Itanium Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDPTA ![In: Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA '02, June 24 - 27, 2002, Las Vegas, Nevada, USA, Volume 3, pp. 1247-1253, 2002, CSREA Press, 1-892512-89-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP BibTeX RDF |
|
24 | Vladik Kreinovich |
Itanium's new basic operation of fused multiply-add: theoretical explanation and theoretical challenge. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGACT News ![In: SIGACT News 32(1), pp. 115-117, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
24 | Fumio Aono, Masayuki Kimura |
The AzusA 16-Way Itanium Server. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 20(5), pp. 54-60, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
24 | Rory McInerney, Kurt Leeper, Troy Hill, Heming Chan, Bulent Basaran, Lance McQuiddy |
Methodology for repeater insertion management in the RTL, layout, floorplan and fullchip timing databases of the Itanium microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2000 International Symposium on Physical Design, ISPD 2000, San Diego, CA, USA, April 9-12, 2000, pp. 99-104, 2000, ACM, 1-58113-191-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
RC delay, routing, timing, estimation, microprocessors, floorplan, repeaters |
24 | Yoshiyuki Yamashita, Masato Tsuru |
Implementing Fast Packet Filters by Software Pipelining on x86 Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APPT ![In: Advanced Parallel Processing Technologies, 8th International Symposium, APPT 2009, Rapperswil, Switzerland, August 24-25, 2009, Proceedings, pp. 420-435, 2009, Springer, 978-3-642-03643-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
24 | Karl Fürlinger, Daniel Terpstra, Haihang You, Philip Mucci, Shirley Moore |
Enabling Data Structure Oriented Performance Analysis with Hardware Performance Counter Support. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par Workshops ![In: Euro-Par 2008 Workshops - Parallel Processing, VHPC 2008, UNICORE 2008, HPPC 2008, SGS 2008, PROPER 2008, ROIA 2008, and DPA 2008, Las Palmas de Gran Canaria, Spain, August 25-26, 2008, Revised Selected Papers, pp. 263-272, 2008, Springer, 978-3-642-00954-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Dawei Liu, Shan Wang 0001, Biao Qin, Weiwei Gong |
Characterizing DSS Workloads from the Processor Perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APWeb/WAIM Workshops ![In: Advances in Web and Network Technologies, and Information Management, APWeb/WAIM 2007 International Workshops: DBMAN 2007, WebETrends 2007, PAIS 2007 and ASWAN 2007, Huang Shan, China, June 16-18, 2007, Proceedings, pp. 235-240, 2007, Springer, 978-3-540-72908-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
24 | Youfeng Wu, Yong-Fong Lee |
Hardware-Software Collaborative Techniques for Runtime Profiling and Phase Transition Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 20(5), pp. 665-675, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
runtime profiling, phase transition detection, hardware-software collaboration, dynamic optimizations |
24 | David Bernick, Bill Bruckert, Paul Del Vigna, David García, Robert Jardine, Jim Klecka, Jim Smullen |
NonStop® Advanced Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: 2005 International Conference on Dependable Systems and Networks (DSN 2005), 28 June - 1 July 2005, Yokohama, Japan, Proceedings, pp. 12-21, 2005, IEEE Computer Society, 0-7695-2282-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
24 | Xinmin Tian, Rakesh Krishnaiyer, Hideki Saito 0001, Milind Girkar, Wei Li 0015 |
Impact of Compiler-based Data-Prefetching Techniques on SPEC OMP Application Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), CD-ROM / Abstracts Proceedings, 4-8 April 2005, Denver, CO, USA, 2005, IEEE Computer Society, 0-7695-2312-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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