Search results for "LEON3"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
98	Krzysztof Marcinek, Arkadiusz W. Luczyk, Witold A. Pleskacz	Enhanced LEON3 core for superscalar processing.	DDECS	2009	DBLP DOI BibTeX RDF
47	Jianjun Guo, Kui Dai, Zhiying Wang 0003	A Heterogeneous Multi-core Processor Architecture for High Performance Computing.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF	TTA, SoC, heterogeneous, multi-core
36	Jin Ouyang, Raghuveer Raghavendra, Sibin Mohan, Tao Zhang 0032, Yuan Xie 0001, Frank Mueller 0001	CheckerCore: enhancing an FPGA soft core to capture worst-case execution times.	CASES	2009	DBLP DOI BibTeX RDF	LEON3, checkercore, shadow pipeline, FPGA, embedded system, real-time, WCET, worst-case-execution-time, SPARC
28	Kris Nikov, Marcos Martínez, Pedro Vallejo, Abel Balbis, José L. Núñez-Yáñez, Kerstin Eder	GR712RC LEON3 Power Model Data.		2022	DOI RDF
28	Sowmith Nethula, Vivek Bansal, Ghaith Bany Hamad, Otmane Aït Mohamed	Layout-based Vulnerability Analysis of LEON3 Processor to Single Event Multiple Transients using Satisfiability Modulo Theories.	ISQED	2022	DBLP DOI BibTeX RDF
28	Server Kasap, Eduardo Weber Wächter, Xiaojun Zhai, Shoaib Ehsan, Klaus D. McDonald-Maier	Survey of Soft Error Mitigation Techniques Applied to LEON3 Soft Processors on SRAM-Based FPGAs.	IEEE Access	2020	DBLP DOI BibTeX RDF
28	Mouna Karmani, Noura Benhadjyoussef, Belgacem Hamdi, Mohsen Machhout	A Hardware-Software Codesign Case Study: The SHA3-512 algorithm Implementation on the LEON3 Processor.	ATSIP	2020	DBLP DOI BibTeX RDF
28	Nam Ho, Paul Kaufmann, Marco Platzner	Optimization of Application-Specific L1 Cache Translation Functions of the LEON3 Processor.	SoCPaR	2019	DBLP DOI BibTeX RDF
28	Gianmarco Dinelli, Gabriele Meoni, Pietro Nannipieri, Luca Dello Sterpaio, Antonino Marino, Luca Fanucci	Integration of a SpaceFibre IP Core with the LEON3 Microprocessor Through an AMBA AHB Bus.	ApplePies	2019	DBLP DOI BibTeX RDF
28	Rajul Bansal, Abhijit Karmakar	Efficient Closely-Coupled Integration of AES Coprocessor with LEON3 Processor.	VDAT	2019	DBLP DOI BibTeX RDF
28	Ilya Tuzov, David de Andrés, Juan Carlos Ruiz	Tuning synthesis flags to optimize implementation goals: Performance and robustness of the LEON3 processor as a case study.	J. Parallel Distributed Comput.	2018	DBLP DOI BibTeX RDF
28	Mohamed Abdelawwad, Ali Hayek, Ahmed Alsuleiman, Josef Börcsök	FPGA Implementation of a Safety System-on-Chip Based on 1oo4 Architecture Using LEON3 Processor.	ICCA	2018	DBLP DOI BibTeX RDF
28	Osvaldo Navarro, Michael Hübner 0001	Runtime Adaptive Cache for the LEON3 Processor.	ARC	2018	DBLP DOI BibTeX RDF
28	Lucas M. V. Pereira, Douglas R. Melo, Cesar A. Zeferino, Eduardo A. Bezerra	Analysis of LEON3 systems integration for a Network-on-Chip.	LATS	2018	DBLP DOI BibTeX RDF
28	Afef Kchaou, Wajih El Hadj Youssef, Rached Tourki	Performance Analysis of a Multicore Based LEON3 Integrating a RTOS.	SSD	2018	DBLP DOI BibTeX RDF
28	Rajul Bansal, Abhijit Karmakar	Efficient integration of coprocessor in LEON3 processor pipeline for System-on-Chip design.	Microprocess. Microsystems	2017	DBLP DOI BibTeX RDF
28	Nam Ho, Ishraq Ibne Ashraf, Paul Kaufmann, Marco Platzner	Accurate private/shared classification of memory accesses: A run-time analysis system for the LEON3 multi-core processor.	DATE	2017	DBLP DOI BibTeX RDF
28	Nam Ho, Paul Kaufmann, Marco Platzner	Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor.	FPT	2017	DBLP DOI BibTeX RDF
28	Thierry Bonnoit, Alexandre Coelho, Nacer-Eddine Zergainoh, Raoul Velazco	SEU impact in processor's control-unit: Preliminary results obtained for LEON3 soft-core.	LATS	2017	DBLP DOI BibTeX RDF
28	Rajul Bansal, Mahendra Kumar Jatav, Abhijit Karmakar	A Lifting Instruction for Performing DWT in LEON3 Processor Based System-on-Chip.	VDAT	2017	DBLP DOI BibTeX RDF
28	Zhe Hou, David Sanán, Alwen Tiu, Yang Liu 0003	A formal model for the SPARCv8 ISA and a proof of non-interference for the LEON3 processor.	Arch. Formal Proofs	2016	DBLP BibTeX RDF
28	Michael J. Wirthlin, Andrew M. Keller, Chase McCloskey, Parker Ridd, David S. Lee, Jeffrey Draper	SEU Mitigation and Validation of the LEON3 Soft Processor Using Triple Modular Redundancy for Space Processing.	FPGA	2016	DBLP DOI BibTeX RDF
28	Zhe Hou, David Sanán, Alwen Tiu, Yang Liu 0003, Koh Chuen Hoa	An Executable Formalisation of the SPARCv8 Instruction Set Architecture: A Case Study for the LEON3 Processor.	FM	2016	DBLP DOI BibTeX RDF
28	Zohaib Najam, Muhammad Najam Dar, Muhammad Yasir Qadri, Shaheryar Najam, Jameel Ahmed	Architectural Enhancement of LEON3 Processor for Real Time and Feedback Applications.	FIT	2016	DBLP DOI BibTeX RDF
28	Afef Kchaou, W. El Hadj Youssef, Rached Tourki, Fraidy Bouesse, Pablo Ramos, Raoul Velazco	A deep analysis of SEU consequences in the internal memory of LEON3 processor.	LATS	2016	DBLP DOI BibTeX RDF
28		Super-scale architecture enhancement of LEON3 core for DSP application.	VDAT	2015	DBLP DOI BibTeX RDF
28	Nam Ho, Paul Kaufmann, Marco Platzner	A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms.	FPL	2014	DBLP DOI BibTeX RDF
28	Andrej Kincel, Marcel Baláz	MBIST for LEON3 processor core cache.	DDECS	2013	DBLP DOI BibTeX RDF
28	Zhenni Li, Jingjiao Li, Liang Li, Yue Zhao, Chaoqun Rong	A SoC design and implementation of dynamic image edge detection based on the LEON3 open source processor.	ICNC	2013	DBLP DOI BibTeX RDF
28	Hamed Abbasitabar, Hamid R. Zarandi, Ronak Salamat	Susceptibility Analysis of LEON3 Embedded Processor against Multiple Event Transients and Upsets.	CSE	2012	DBLP DOI BibTeX RDF
28	Antonio da Silva 0001, Sebastián Sánchez 0001	A LEON3 virtual platform with real spacewire interfaces for dependable space software development.	SimuTools	2011	DBLP DOI BibTeX RDF
28	Martin Danek, Leos Kafka, Lukas Kohout, Jaroslav Sykora	Instruction set extensions for multi-threading in LEON3.	DDECS	2010	DBLP DOI BibTeX RDF
28	Antonio da Silva 0001, Sebastián Sánchez 0001	LEON3 ViP: A Virtual Platform with Fault Injection Capabilities.	DSD	2010	DBLP DOI BibTeX RDF
28	Syed Zahid Ahmed, Julien Eydoux, Laurent Rouge, Jean-Baptiste Cuelle, Gilles Sassatelli, Lionel Torres	Exploration of power reduction and performance enhancement in LEON3 processor with ESL reprogrammable eFPGA in processor pipeline and as a co-processor.	DATE	2009	DBLP DOI BibTeX RDF
28	Sandro Penolazzi, Luca Bolognino, Ahmed Hemani	Energy and Performance Model of a SPARC Leon3 Processor.	DSD	2009	DBLP DOI BibTeX RDF
23	Ales Plsek, Lei Zhao, Veysel Harun Sahin, Daniel Tang, Tomas Kalibera, Jan Vitek	Developing safety critical Java applications with oSCJ/L0.	JTRES	2010	DBLP DOI BibTeX RDF	memory management, Java virtual machine, safety critical systems
23	Filip Pizlo, Lukasz Ziarek, Ethan Blanton, Petr Maj, Jan Vitek	High-level programming of embedded hard real-time devices.	EuroSys	2010	DBLP DOI BibTeX RDF	real-time systems, memory management, java virtual machine
23	Roy Chaoming Hsu, Yaw-Yu Lee, Bin-Wen Kao, Din-Yuen Chan	Hardware Design of Shape-Preserving Contour Tracing for Object of Segmented Images.	PSIVT	2009	DBLP DOI BibTeX RDF	AMBA bus, SOC, Boundary Extraction, Contour Tracing
23	Izhar Zaidi, Atukem Nabina, Cedric Nishan Canagarajah, José L. Núñez-Yáñez	Power/Area Analysis of a FPGA-Based Open-Source Processor using Partial Dynamic Reconfiguration.	DSD	2008	DBLP DOI BibTeX RDF
23	Izhar Zaidi, Atukem Nabina, Cedric Nishan Canagarajah, José L. Núñez-Yáñez	Evaluating dynamic partial reconfiguration in the integer pipeline of a FPGA-based opensource processor.	FPL	2008	DBLP DOI BibTeX RDF
23	José L. Núñez-Yáñez, Vassilios A. Chouliaras, Jiri Gaisler	Dynamic Voltage Scaling in a FPGA-based System-on-Chip.	FPL	2007	DBLP DOI BibTeX RDF