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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 17 occurrences of 15 keywords
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Results
Found 41 publication records. Showing 41 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
98 | Krzysztof Marcinek, Arkadiusz W. Luczyk, Witold A. Pleskacz |
Enhanced LEON3 core for superscalar processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009, April 15-17, 2009, Liberec, Czech Republic, pp. 238-241, 2009, IEEE Computer Society, 978-1-4244-3341-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
47 | Jianjun Guo, Kui Dai, Zhiying Wang 0003 |
A Heterogeneous Multi-core Processor Architecture for High Performance Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings, pp. 359-365, 2006, Springer, 3-540-40056-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
TTA, SoC, heterogeneous, multi-core |
36 | Jin Ouyang, Raghuveer Raghavendra, Sibin Mohan, Tao Zhang 0032, Yuan Xie 0001, Frank Mueller 0001 |
CheckerCore: enhancing an FPGA soft core to capture worst-case execution times. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2009, Grenoble, France, October 11-16, 2009, pp. 175-184, 2009, ACM. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
LEON3, checkercore, shadow pipeline, FPGA, embedded system, real-time, WCET, worst-case-execution-time, SPARC |
28 | Kris Nikov, Marcos Martínez, Pedro Vallejo, Abel Balbis, José L. Núñez-Yáñez, Kerstin Eder |
GR712RC LEON3 Power Model Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
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2022 |
DOI RDF |
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28 | Sowmith Nethula, Vivek Bansal, Ghaith Bany Hamad, Otmane Aït Mohamed |
Layout-based Vulnerability Analysis of LEON3 Processor to Single Event Multiple Transients using Satisfiability Modulo Theories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 23rd International Symposium on Quality Electronic Design, ISQED 2022, Santa Clara, CA, USA, April 6-7, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-9466-3. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
28 | Server Kasap, Eduardo Weber Wächter, Xiaojun Zhai, Shoaib Ehsan, Klaus D. McDonald-Maier |
Survey of Soft Error Mitigation Techniques Applied to LEON3 Soft Processors on SRAM-Based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 8, pp. 28646-28658, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
28 | Mouna Karmani, Noura Benhadjyoussef, Belgacem Hamdi, Mohsen Machhout |
A Hardware-Software Codesign Case Study: The SHA3-512 algorithm Implementation on the LEON3 Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATSIP ![In: 5th International Conference on Advanced Technologies for Signal and Image Processing, ATSIP 2020, Sousse, Tunisia, September 2-5, 2020, pp. 1-5, 2020, IEEE, 978-1-7281-7513-3. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
28 | Nam Ho, Paul Kaufmann, Marco Platzner |
Optimization of Application-Specific L1 Cache Translation Functions of the LEON3 Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCPaR ![In: Proceedings of the 11th International Conference on Soft Computing and Pattern Recognition (SoCPaR 2019), Hyderabad, India, December 13-15, 2019., pp. 266-276, 2019, Springer, 978-3-030-49344-8. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
28 | Gianmarco Dinelli, Gabriele Meoni, Pietro Nannipieri, Luca Dello Sterpaio, Antonino Marino, Luca Fanucci |
Integration of a SpaceFibre IP Core with the LEON3 Microprocessor Through an AMBA AHB Bus. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ApplePies ![In: Applications in Electronics Pervading Industry, Environment and Society - APPLEPIES 2019, Pisa, Italy, 11-13 September 2019, pp. 499-504, 2019, Springer, 978-3-030-37276-7. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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28 | Rajul Bansal, Abhijit Karmakar |
Efficient Closely-Coupled Integration of AES Coprocessor with LEON3 Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 23rd International Symposium, VDAT 2019, Indore, India, July 4-6, 2019, Revised Selected Papers, pp. 345-356, 2019, Springer, 978-981-32-9766-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
28 | Ilya Tuzov, David de Andrés, Juan Carlos Ruiz |
Tuning synthesis flags to optimize implementation goals: Performance and robustness of the LEON3 processor as a case study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Parallel Distributed Comput. ![In: J. Parallel Distributed Comput. 112, pp. 84-96, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
28 | Mohamed Abdelawwad, Ali Hayek, Ahmed Alsuleiman, Josef Börcsök |
FPGA Implementation of a Safety System-on-Chip Based on 1oo4 Architecture Using LEON3 Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCA ![In: 2018 International Conference on Computer and Applications (ICCA), Beirut, Lebanon, August 25-26, 2018, pp. 231-235, 2018, IEEE, 978-1-5386-4371-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
28 | Osvaldo Navarro, Michael Hübner 0001 |
Runtime Adaptive Cache for the LEON3 Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Applied Reconfigurable Computing. Architectures, Tools, and Applications - 14th International Symposium, ARC 2018, Santorini, Greece, May 2-4, 2018, Proceedings, pp. 343-354, 2018, Springer, 978-3-319-78889-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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28 | Lucas M. V. Pereira, Douglas R. Melo, Cesar A. Zeferino, Eduardo A. Bezerra |
Analysis of LEON3 systems integration for a Network-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-3, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
28 | Afef Kchaou, Wajih El Hadj Youssef, Rached Tourki |
Performance Analysis of a Multicore Based LEON3 Integrating a RTOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SSD ![In: 15th International Multi-Conference on Systems, Signals & Devices, SSD 2018, Yassmine Hammamet, Tunisia, March 19-22, 2018, pp. 858-864, 2018, IEEE, 978-1-5386-5305-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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28 | Rajul Bansal, Abhijit Karmakar |
Efficient integration of coprocessor in LEON3 processor pipeline for System-on-Chip design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 51, pp. 56-75, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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28 | Nam Ho, Ishraq Ibne Ashraf, Paul Kaufmann, Marco Platzner |
Accurate private/shared classification of memory accesses: A run-time analysis system for the LEON3 multi-core processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, pp. 788-793, 2017, IEEE, 978-3-9815370-8-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
28 | Nam Ho, Paul Kaufmann, Marco Platzner |
Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: International Conference on Field Programmable Technology, FPT 2017, Melbourne, Australia, December 11-13, 2017, pp. 215-218, 2017, IEEE, 978-1-5386-2656-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
28 | Thierry Bonnoit, Alexandre Coelho, Nacer-Eddine Zergainoh, Raoul Velazco |
SEU impact in processor's control-unit: Preliminary results obtained for LEON3 soft-core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 18th IEEE Latin American Test Symposium, LATS 2017, Bogotá, Colombia, March 13-15, 2017, pp. 1-4, 2017, IEEE, 978-1-5386-0415-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
28 | Rajul Bansal, Mahendra Kumar Jatav, Abhijit Karmakar |
A Lifting Instruction for Performing DWT in LEON3 Processor Based System-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 21st International Symposium, VDAT 2017, Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers, pp. 731-736, 2017, Springer, 978-981-10-7469-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
28 | Zhe Hou, David Sanán, Alwen Tiu, Yang Liu 0003 |
A formal model for the SPARCv8 ISA and a proof of non-interference for the LEON3 processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Arch. Formal Proofs ![In: Arch. Formal Proofs 2016, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
|
28 | Michael J. Wirthlin, Andrew M. Keller, Chase McCloskey, Parker Ridd, David S. Lee, Jeffrey Draper |
SEU Mitigation and Validation of the LEON3 Soft Processor Using Triple Modular Redundancy for Space Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, USA, February 21-23, 2016, pp. 205-214, 2016, ACM, 978-1-4503-3856-1. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
28 | Zhe Hou, David Sanán, Alwen Tiu, Yang Liu 0003, Koh Chuen Hoa |
An Executable Formalisation of the SPARCv8 Instruction Set Architecture: A Case Study for the LEON3 Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FM ![In: FM 2016: Formal Methods - 21st International Symposium, Limassol, Cyprus, November 9-11, 2016, Proceedings, pp. 388-405, 2016, 978-3-319-48988-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
28 | Zohaib Najam, Muhammad Najam Dar, Muhammad Yasir Qadri, Shaheryar Najam, Jameel Ahmed |
Architectural Enhancement of LEON3 Processor for Real Time and Feedback Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FIT ![In: International Conference on Frontiers of Information Technology, FIT 2016, Islamabad, Pakistan, December 19-21, 2016, pp. 29-34, 2016, IEEE Computer Society, 978-1-5090-5300-1. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
28 | Afef Kchaou, W. El Hadj Youssef, Rached Tourki, Fraidy Bouesse, Pablo Ramos, Raoul Velazco |
A deep analysis of SEU consequences in the internal memory of LEON3 processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 17th Latin-American Test Symposium, LATS 2016, Foz do Iguacu, Brazil, April 6-8, 2016, pp. 178, 2016, IEEE, 978-1-5090-1331-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
28 | |
Super-scale architecture enhancement of LEON3 core for DSP application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 19th International Symposium on VLSI Design and Test, VDAT 2015, Ahmedabad, India, June 26-29, 2015, pp. 1-2, 2015, IEEE Computer Society, 978-1-4799-1743-3. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
28 | Nam Ho, Paul Kaufmann, Marco Platzner |
A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1-4, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
28 | Andrej Kincel, Marcel Baláz |
MBIST for LEON3 processor core cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2013, Karlovy Vary, Czech Republic, April 8-10, 2013, pp. 287-288, 2013, IEEE Computer Society, 978-1-4673-6135-4. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
28 | Zhenni Li, Jingjiao Li, Liang Li, Yue Zhao, Chaoqun Rong |
A SoC design and implementation of dynamic image edge detection based on the LEON3 open source processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICNC ![In: Ninth International Conference on Natural Computation, ICNC 2013, Shenyang, China, July 23-25, 2013, pp. 1263-1267, 2013, IEEE, 978-1-4673-4714-3. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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28 | Hamed Abbasitabar, Hamid R. Zarandi, Ronak Salamat |
Susceptibility Analysis of LEON3 Embedded Processor against Multiple Event Transients and Upsets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSE ![In: 15th IEEE International Conference on Computational Science and Engineering, CSE 2012, Paphos, Cyprus, December 5-7, 2012, pp. 548-553, 2012, IEEE Computer Society, 978-1-4673-5165-2. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
28 | Antonio da Silva 0001, Sebastián Sánchez 0001 |
A LEON3 virtual platform with real spacewire interfaces for dependable space software development. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SimuTools ![In: 4th International ICST Conference on Simulation Tools and Techniques, SIMUTools '11, Barcelona, Spain, March 22 - 24, 2011, pp. 1-8, 2011, ICST/ACM, 978-1-936968-00-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
28 | Martin Danek, Leos Kafka, Lukas Kohout, Jaroslav Sykora |
Instruction set extensions for multi-threading in LEON3. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010, Vienna, Austria, April 14-16, 2010, pp. 237-242, 2010, IEEE Computer Society, 978-1-4244-6612-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
28 | Antonio da Silva 0001, Sebastián Sánchez 0001 |
LEON3 ViP: A Virtual Platform with Fault Injection Capabilities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 13th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2010, 1-3 September 2010, Lille, France, pp. 813-816, 2010, IEEE Computer Society, 978-0-7695-4171-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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28 | Syed Zahid Ahmed, Julien Eydoux, Laurent Rouge, Jean-Baptiste Cuelle, Gilles Sassatelli, Lionel Torres |
Exploration of power reduction and performance enhancement in LEON3 processor with ESL reprogrammable eFPGA in processor pipeline and as a co-processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009, pp. 184-189, 2009, IEEE, 978-1-4244-3781-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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28 | Sandro Penolazzi, Luca Bolognino, Ahmed Hemani |
Energy and Performance Model of a SPARC Leon3 Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2009, 27-29 August 2009, Patras, Greece, pp. 651-656, 2009, IEEE Computer Society, 978-0-7695-3782-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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23 | Ales Plsek, Lei Zhao, Veysel Harun Sahin, Daniel Tang, Tomas Kalibera, Jan Vitek |
Developing safety critical Java applications with oSCJ/L0. ![Search on Bibsonomy](Pics/bibsonomy.png) |
JTRES ![In: Proceedings of the 8th International Workshop on Java Technologies for Real-Time and Embedded Systems, JTRES 2010, Prague, Czech Republic, August 19-21, 2010, pp. 95-101, 2010, ACM, 978-1-4503-0122-0. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
memory management, Java virtual machine, safety critical systems |
23 | Filip Pizlo, Lukasz Ziarek, Ethan Blanton, Petr Maj, Jan Vitek |
High-level programming of embedded hard real-time devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EuroSys ![In: European Conference on Computer Systems, Proceedings of the 5th European conference on Computer systems, EuroSys 2010, Paris, France, April 13-16, 2010, pp. 69-82, 2010, ACM, 978-1-60558-577-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
real-time systems, memory management, java virtual machine |
23 | Roy Chaoming Hsu, Yaw-Yu Lee, Bin-Wen Kao, Din-Yuen Chan |
Hardware Design of Shape-Preserving Contour Tracing for Object of Segmented Images. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PSIVT ![In: Advances in Image and Video Technology, Third Pacific Rim Symposium, PSIVT 2009, Tokyo, Japan, January 13-16, 2009. Proceedings, pp. 976-987, 2009, Springer, 978-3-540-92956-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
AMBA bus, SOC, Boundary Extraction, Contour Tracing |
23 | Izhar Zaidi, Atukem Nabina, Cedric Nishan Canagarajah, José L. Núñez-Yáñez |
Power/Area Analysis of a FPGA-Based Open-Source Processor using Partial Dynamic Reconfiguration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008, pp. 592-598, 2008, IEEE Computer Society, 978-0-7695-3277-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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23 | Izhar Zaidi, Atukem Nabina, Cedric Nishan Canagarajah, José L. Núñez-Yáñez |
Evaluating dynamic partial reconfiguration in the integer pipeline of a FPGA-based opensource processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, pp. 547-550, 2008, IEEE, 978-1-4244-1961-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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23 | José L. Núñez-Yáñez, Vassilios A. Chouliaras, Jiri Gaisler |
Dynamic Voltage Scaling in a FPGA-based System-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 459-462, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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