Search results for "Ldi/dt"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
52	Woo Hyung Lee, Sanjay Pant, David T. Blaauw	Analysis and Reduction of On-Chip Inductance Effects in Power Supply Grids.	ISQED	2004	DBLP DOI BibTeX RDF
52	Zhenyu Tang, Lei He 0001, Norman Chang, Shen Lin, Weize Xie, O. Sam Nakagawa	Instruction Prediction for Step Power Reduction.	ISQED	2001	DBLP DOI BibTeX RDF
45	Sanjay Pant, David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda	A stochastic approach To power grid analysis.	DAC	2004	DBLP DOI BibTeX RDF	Ldi/dt, IR drop, power supply networks
45	Wael El-Essawy, David H. Albonesi, Balaram Sinharoy	A microarchitectural-level step-power analysis tool.	ISLPED	2002	DBLP DOI BibTeX RDF	Ldi/dt, step-power, microprocessors, clock-gating, architectural simulation, inductive noise
28	Sanjay Pant, Eli Chiprout	Power grid physics and implications for CAD.	DAC	2006	DBLP DOI BibTeX RDF	Ldi/dt, decap, locality, IR, resonance, power supply networks
27	Igor Arsovski, Akhilesh Patil, Robert M. Houle, Michael Fragano, Ramon Rodriguez, Raymond Kim, Van Butler	1.4Gsearch/s 2-Mb/mm2 TCAM Using Two-Phase-Pre-Charge ML Sensing and Power-Grid Pre-Conditioning to Reduce Ldi/dt Power-Supply Noise by 50%.	IEEE J. Solid State Circuits	2018	DBLP DOI BibTeX RDF
27	Igor Arsovski, Michael Fragano, Robert M. Houle, Akhilesh Patil, Van Butler, Raymond Kim, Ramon Rodriguez, Tom Maffitt, Joseph J. Oler, John Goss, Christopher Parkinson, Michael A. Ziegerhofer, Steven Burns 0001	12.4 1.4Gsearch/s 2Mb/mm2 TCAM using two-phase-precharge ML sensing and power-grid preconditioning to reduce Ldi/dt power-supply noise by 50%.	ISSCC	2017	DBLP DOI BibTeX RDF
27	Siraj Fulum Mossa, Syed Rafay Hasan, Omar Sayed Ahmed Elkeelany	Grouped through silicon vias for lower Ldi/dt drop in three-dimensional integrated circuit.	IET Circuits Devices Syst.	2016	DBLP DOI BibTeX RDF
27	Xiaoying He, Shen Xu, Weifeng Sun, Weichang Cheng, Shengli Lu	Modelling of Ldi/dt effect with frequency spectrum analysis and parameter design in float ground driver system.	IET Circuits Devices Syst.	2014	DBLP DOI BibTeX RDF
27	Xiaoying He, Weifeng Sun, Guohuan Hua, Shen Xu, Shengli Lu	Analytic Ldi/dt Effect Model Based on Float Ground in Plasma Display Panel Driver System.	IEICE Trans. Electron.	2013	DBLP DOI BibTeX RDF
27	Shiyou Zhao, Kaushik Roy 0001	Estimation of Switching Noise on Power Supply Lines in Deep Sub-micron CMOS Circuits.	VLSI Design	2000	DBLP DOI BibTeX RDF	switching noise, Ldi/dt noise, maximum switching current, IR voltage drop
17	Jie Gu 0003, Chris H. Kim	Multi-story power delivery for supply noise reduction and low voltage operation.	ISLPED	2005	DBLP DOI BibTeX RDF	digital voltage regulator, multi-story power delivery, supply noise, capacitive coupling
17	Yu-Min Lee, Charlie Chung-Ping Chen	The power grid transient simulation in linear time based on 3-D alternating-direction-implicit method.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
17	Yu-Min Lee, Charlie Chung-Ping Chen	The Power Grid Transient Simulation in Linear Time Based on 3D Alternating-Direction-Implicit Method .	DATE	2003	DBLP DOI BibTeX RDF
17	Sanjay Pant, David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda	Vectorless Analysis of Supply Noise Induced Delay Variation.	ICCAD	2003	DBLP DOI BibTeX RDF
17	Yonghee Im, Kaushik Roy 0001	A logic-aware layout methodology to enhance the noise immunity of domino circuits.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
17	Shiyou Zhao, Kaushik Roy 0001, Cheng-Kok Koh	Estimation of Inductive and Resistive Switching Noise on Power Supply Network in Deep Sub-Micron CMOS Circuits.	ICCD	2000	DBLP DOI BibTeX RDF