|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 3 occurrences of 3 keywords
|
|
|
Results
Found 7 publication records. Showing 7 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
153 | Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez |
A multilevel hierarchical interconnection structure for FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006, pp. 225, 2006, ACM, 1-59593-292-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
117 | Zied Marrakchi, Hayder Mrabet, Christian Masson, Habib Mehrez |
Mesh of Tree: Unifying Mesh and MFPGA for Better Device Performances. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: First International Symposium on Networks-on-Chips, NOCS 2007, 7-9 May 2007, Princeton, New Jersey, USA, Proceedings, pp. 243-252, 2007, IEEE Computer Society, 978-0-7695-2773-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
91 | Zied Marrakchi, Hayder Mrabet, Habib Mehrez |
A new Multilevel Hierarchical MFPGA and its suitable configuration tools. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany, pp. 263-268, 2006, IEEE Computer Society, 0-7695-2533-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
76 | Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez |
Performances improvement of FPGA using novel multilevel hierarchical interconnection structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 675-679, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
51 | Zied Marrakchi, Hayder Mrabet, Habib Mehrez |
Configuration tools for a new multilevel hierarchical FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006, pp. 229, 2006, ACM, 1-59593-292-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
40 | Emna Amouri, Hayder Mrabet, Zied Marrakchi, Habib Mehrez |
Placement and routing techniques to improve delay balance of WDDL netlist in MFPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 16th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2009, Yasmine Hammamet, Tunisia, 13-19 December, 2009, pp. 791-794, 2009, IEEE, 978-1-4244-5090-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
36 | Emna Amouri, Hayder Mrabet, Zied Marrakchi, Habib Mehrez |
Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, Cancun, Quintana Roo, Mexico, 9-11 December 2009, Proceedings, pp. 201-206, 2009, IEEE Computer Society, 978-0-7695-3917-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
MFPGA, Timing balance, WDDL, Routing, Placement, Differential Power Analysis |
Displaying result #1 - #7 of 7 (100 per page; Change: )
|
|