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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 43 occurrences of 28 keywords
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Results
Found 18 publication records. Showing 18 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
96 | Jacob Savir |
On shrinking wide compressors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 108-117, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
wiring overhead, detection probability loss, test length penalty, fault coverage degradation, fault diagnosis, logic testing, built-in self test, built-in self-test, integrated circuit testing, shift registers, pseudo-random test, MISRs, parity, multiple-input signature registers |
80 | Geetani Edirisooriya, John P. Robinson |
Aliasing properties of circular MISRs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 4(2), pp. 151-158, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
multiple input signature analysis, test data compaction, built-in self-test, Aliasing probability |
64 | Joon-Sung Yang, Nur A. Touba |
Enhancing Silicon Debug via Periodic Monitoring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA, pp. 125-133, 2008, IEEE Computer Society, 978-0-7695-3365-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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64 | Kazuhiko Iwasaki, Fumio Arakawa |
An analysis of the aliasing probability of multiple-input signature registers in the case of a 2m-ary symmetric channel. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(4), pp. 427-438, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
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64 | Kazuhiko Iwasaki |
Analysis and proposal of signature circuits for LSI testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(1), pp. 84-90, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
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59 | Slawomir Pilarski |
Comments on "Aliasing Properties of Circular MISRs". ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 6(1), pp. 139-140, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
built-in self-test, Aliasing, signature analysis, error models, test response compaction |
42 | Hussam Y. Abujbara, Sami A. Al-Arian |
Self-testing and self-reconfiguration architecture for 2-D WSI arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPDP ![In: Proceedings of the Second IEEE Symposium on Parallel and Distributed Processing, SPDP 1990, Dallas, Texas, USA, December 9-13, 1990., pp. 527-530, 1990, IEEE Computer Society, 0-8186-2087-0. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
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37 | Rajendra S. Katti, Rucha Sule |
MISRs for Fast Authentication of Long Messages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2013 Euromicro Conference on Digital System Design, DSD 2013, Los Alamitos, CA, USA, September 4-6, 2013, pp. 653-657, 2013, IEEE Computer Society, 978-1-4799-2978-8. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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37 | Brion L. Keller, Thomas Bartenstein |
Use of MISRs for compression and diagnostics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2005 IEEE International Test Conference, ITC 2005, Austin, TX, USA, November 8-10, 2005, pp. 9, 2005, IEEE Computer Society, 0-7803-9038-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
37 | Geetani Edirisooriya, John P. Robinson |
Authors' reply to comments on "Aliasing Properties of Circular MISRs". ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 6(1), pp. 141-142, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
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33 | Kazuhiko Iwasaki, Shigeo Nakamura |
Aliasing Error for a Mask ROM Built-In Self-Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 45(3), pp. 270-277, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
mask ROM, experimental faults analysis, Built-in self-test, aliasing probability, MISRs |
21 | Chunsheng Liu, Krishnendu Chakrabarty, Michael Gössel |
An Interval-Based Diagnosis Scheme for Identifying Failing Vectors in a Scan-BIST Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 382-386, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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21 | Firas Khadour, Xiaoling Sun |
Fast Signature Simulation for PPSFP Simulators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), November 1-3, 1999, Albuquerque, NM, USA, Proceedings, pp. 181-, 1999, IEEE Computer Society, 0-7695-0325-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
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21 | Rodrigue Byrne |
Determining Aliasing Probabilities in BIST by Counting Strings. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 11(3), pp. 263-272, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
response analysis architectures, compression techniques, aliasing probabilities, deterministic finite automata |
21 | Manoj Franklin |
Fast computation of C-MISR signatures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 293-297, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
C-MISR signatures, built-in self-test applications, good circuit signature, faulty circuit signatures, cellular automata-based multi-input signature registers, equivalent single input circuit, VLSI, logic testing, built-in self test, cellular automata, integrated circuit testing, sequential circuits, shift registers, test responses, signature analyzers, equivalent circuits |
21 | Manoj Franklin, Kewal K. Saluja, Kyuchull Kim |
Fast computation of MISR signatures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 414-418, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
MISR signatures, fast computation, test response compression, multi-input signature registers, equivalent single input circuit, logic testing, design for testability, logic design, table lookup, table lookups, shift registers, binary sequences, speedup technique, signature analyzers |
21 | Martin Rudolph |
Feedback-testing by using multiple input signature registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 1(3), pp. 213-219, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
Bult-in self-test, design for testability, test-pattern generation, testability analysis, MISR |
21 | Micaela Serra, Jon C. Muzio |
Space compaction for multiple-output circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(10), pp. 1105-1113, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
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