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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 541 occurrences of 254 keywords
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Results
Found 947 publication records. Showing 947 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
102 | Yu Wang 0002, Jiang Xu 0001, Shengxi Huang, Weichen Liu, Huazhong Yang |
A case study of on-chip sensor network in multiprocessor system-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2009, Grenoble, France, October 11-16, 2009, pp. 241-250, 2009, ACM. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
sensor network, reliability, low-power, system on chip, dynamic control, power grid noise |
95 | Zhenyu (Peter) Gu, Changyun Zhu, Li Shang, Robert P. Dick |
Application-Specific MPSoC Reliability Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(5), pp. 603-608, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
83 | Liping Xue, Ozcan Ozturk 0001, Feihui Li, Mahmut T. Kandemir, Ibrahim Kolcu |
Dynamic partitioning of processing and memory resources in embedded MPSoC architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 690-695, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
73 | David Atienza, Pablo García Del Valle, Giacomo Paci, Francesco Poletti, Luca Benini, Giovanni De Micheli, Jose Manuel Mendias |
A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 618-623, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
thermal studies, FPGA, emulation, MPSoC |
72 | Yuriy Sheynin, Elena Suvorova, Felix Shutenko |
Complexity and Low Power Issues for On-chip Interconnections in MPSoC System Level Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany, pp. 283-288, 2006, IEEE Computer Society, 0-7695-2533-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
66 | Jianjiang Ceng, Weihua Sheng, Jerónimo Castrillón, Anastasia Stulova, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
A high-level virtual platform for early MPSoC software development. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009, pp. 11-20, 2009, ACM, 978-1-60558-628-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
simulation, parallel programming, software, embedded, MPSoC, system level design, virtual platform |
66 | Eric Cheung, Harry Hsieh, Felice Balarin |
Software optimization for MPSoC: a mpeg-2 decoder case study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008, Atlanta, GA, USA, October 19-24, 2008, pp. 43-48, 2008, ACM, 978-1-60558-470-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
mpsoc, software optimization |
66 | Hong Yue, Zhiying Wang 0003, Kui Dai |
A Heterogeneous Embedded MPSoC for Multimedia Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCC ![In: High Performance Computing and Communications, Second International Conference, HPCC 2006, Munich, Germany, September 13-15, 2006, Proceedings, pp. 591-600, 2006, Springer, 3-540-39368-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Transport Triggered Architecture, DSP, Embedded Processor, Heterogeneous MPSoC |
62 | Diana Göhringer, Michael Hübner 0001, Michael Benz, Jürgen Becker 0001 |
A semi-automatic toolchain for reconfigurable multiprocessor systems-on-chip: architecture development and application partitioning (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 286, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
designflow, toolchain, fpga, partitioning, reconfigurable computing, mpsoc, hardware/software co-design |
62 | Eshel Haritan, Toshihiro Hattori, Hiroyuki Yagi, Pierre G. Paulin, Wayne H. Wolf, Achim Nohl, Drew Wingard, Mike Muller |
Multicore design is the challenge! what is the solution? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 128-130, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
heterogeneous/homogenous multicore, symmetric/asymmetric multicore, multiprocessors, interconnect, multi-core, MPSoC, programming model, virtual prototyping, ESL, virtual platforms |
62 | Lei Gao, Kingshuk Karuri, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
Multiprocessor performance estimation using hybrid simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 325-330, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
HySim, address recovery, cross replay, MPSoC, performance estimation, cache simulation, hybrid simulation |
62 | David Atienza, Pablo García Del Valle, Giacomo Paci, Francesco Poletti, Luca Benini, Giovanni De Micheli, Jose Manuel Mendias, Román Hermida |
HW-SW emulation framework for temperature-aware design in MPSoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 12(3), pp. 26:1-26:26, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Thermal-aware design, FPGA, emulation, MPSoC, temperature |
62 | Wayne H. Wolf |
The future of multiprocessor systems-on-chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 681-685, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
real-time, low power, system-on-chip, embedded software, MPSoC |
61 | Eric Cheung, Harry Hsieh, Felice Balarin |
Fast and accurate performance simulation of embedded software for MPSoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 552-557, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
55 | Qiwei Zhang, André B. J. Kokkeler, Gerard J. M. Smit |
Cognitive Radio Design on an MPSoC Reconfigurable Platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Mob. Networks Appl. ![In: Mob. Networks Appl. 13(5), pp. 424-430, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
task transaction level interface, sparse FFT, OFDM, cognitive radio, design method, MPSoC |
55 | Jianjiang Ceng, Jerónimo Castrillón, Weihua Sheng, Hanno Scharwächter, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tsuyoshi Isshiki, Hiroaki Kunieda |
MAPS: an integrated framework for MPSoC application parallelization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 754-759, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
MPSoC programming, parallelization, software, embedded |
55 | Ines Viskic, Samar Abdi, Daniel D. Gajski |
Automatic generation of embedded communication SW for heterogeneous MPSoC platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'07), San Diego, California, USA, June 13-15, 2007, pp. 143-145, 2007, ACM, 978-1-59593-632-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
custom communication SW, pin/cycle accurate models, MPSoC, system level design, transaction level models, platform based design, automatic synthesis, on-chip communication |
55 | Melhem Tawk, Khaled Z. Ibrahim, Smaïl Niar |
Adaptive Sampling for Efficient MPSoC Architecture Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MASCOTS ![In: 15th International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS 2007), October 24-26, 2007, Istanbul, Turkey, pp. 186-192, 2007, IEEE Computer Society, 978-1-4244-1854-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Simulation, Sampling, MPSoC, Acceleration |
55 | Pramod Chandraiah, Rainer Dömer |
Pointer re-coding for creating definitive MPSoC models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 33-38, 2007, ACM, 978-1-59593-824-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
re-coding, MPSoC, pointers, system specification |
55 | Vivy Suhendra, Chandrashekar Raghavan, Tulika Mitra |
Integrated scratchpad memory optimization and task scheduling for MPSoC architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2006 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2006, Seoul, Korea, October 22-25, 2006, pp. 401-410, 2006, ACM, 1-59593-543-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
scheduling, MPSoC, scratchpad memory, task mapping |
55 | Julien Bernard 0001, Jean-Louis Roch, Serge De Paoli, Miguel Santana |
Adaptive Encoding of Multimedia Streams on MPSoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Computational Science (4) ![In: Computational Science - ICCS 2006, 6th International Conference, Reading, UK, May 28-31, 2006, Proceedings, Part IV, pp. 999-1006, 2006, Springer, 3-540-34385-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
scheduling, MPSoC, work-stealing |
55 | Grant Martin |
Overview of the MPSoC design challenge. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 274-279, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
MPSoC, system-level design, multi-processor system-on-chip |
55 | Ozcan Ozturk 0001, Mahmut T. Kandemir, Mary Jane Irwin |
Using data compression in an MPSoC architecture for improving performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 353-356, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
compression, MPSoC |
51 | Salvatore Carta, Andrea Acquaviva, Pablo García Del Valle, David Atienza, Giovanni De Micheli, Fernando Rincón, Luca Benini, Jose Manuel Mendias |
Multi-processor operating system emulation framework with thermal feedback for systems-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 311-316, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
thermal studies, FPGA, operating system, emulation, MPSoC |
49 | Francesco Zanini, David Atienza, Giovanni De Micheli |
A control theory approach for thermal balancing of MPSoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 37-42, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
49 | Sung-Kwan Ku, Han-Sam Jung, Ki-Seok Chung |
A unified power measurement and management platform for pipelined MPSoC executions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 21st Annual IEEE International SoC Conference, SoCC 2008, September 17-20, 2008, Radisson Hotel, Newport Beach, CA, USA, Proceedings, pp. 13-16, 2008, IEEE, 978-1-4244-2596-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
49 | Sudeep Pasricha, Nikil D. Dutt |
A Framework for Cosynthesis of Memory and Communication Architectures for MPSoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(3), pp. 408-420, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
49 | Katalin Popovici, Ahmed Amine Jerraya |
Simulink based hardware-software codesign flow for heterogeneous MPSoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCSC ![In: Proceedings of the 2007 Summer Computer Simulation Conference, SCSC 2007, San Diego, California, USA, July 16-19, 2007, pp. 497-504, 2007, Simulation Councils, Inc., 1-56555-316-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
hardware-software gradual refinement, multimedia applications, abstraction levels |
49 | Youssef Atat, Nacer-Eddine Zergainoh |
Simulink-based MPSoC Design: New Approach to Bridge the Gap between Algorithm and Architecture Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pp. 9-14, 2007, IEEE Computer Society, 0-7695-2896-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
49 | Matthieu Briere, Bruno Girodias, Youcef Bouchebaba, Gabriela Nicolescu, Fabien Mieyeville, Frédéric Gaffiot, Ian O'Connor |
System level assessment of an optical NoC in an MPSoC platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 1084-1089, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
49 | Rabie Ben Atitallah, Smaïl Niar, Samy Meftali, Jean-Luc Dekeyser |
An MPSoC Performance Estimation Framework Using Transaction Level Modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007), 21-24 August 2007, Daegu, Korea, pp. 525-533, 2007, IEEE Computer Society, 0-7695-2975-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
49 | Andrea Marongiu, Luca Benini, Mahmut T. Kandemir |
Lightweight barrier-based parallelization support for non-cache-coherent MPSoC platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 145-149, 2007, ACM. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
code parallelization, MPSoCs, barrier synchronization |
49 | Tianmiao Wang, Kai Sun, Hongxing Wei, Meng Wang 0005, Zili Shao, Hui Liu 0006 |
Interconnection Synthesis of MPSoC Architecture for Gamma Cameras. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC ![In: Embedded and Ubiquitous Computing, International Conference, EUC 2007, Taipei, Taiwan, December 17-20, 2007, Proceedings, pp. 209-218, 2007, Springer, 978-3-540-77091-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
49 | Pramod Chandraiah, Rainer Dömer |
Designer-Controlled Generation of Parallel and Flexible Heterogeneous MPSoC Specification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 787-790, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
49 | Sudeep Pasricha, Nikil D. Dutt |
COSMECA: application specific co-synthesis of memory and communication architectures for MPSoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 700-705, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
49 | Ana Lucia Varbanescu, Henk J. Sips, Arjan J. C. van Gemund |
PAM-SoC: A Toolchain for Predicting MPSoC Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2006, Parallel Processing, 12th International Euro-Par Conference, Dresden, Germany, August 28 - September 1, 2006, Proceedings, pp. 111-123, 2006, Springer, 3-540-37783-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
49 | Terry Tao Ye, Luca Benini, Giovanni De Micheli |
Packetized On-Chip Interconnect Communication Analysis for MPSoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 10344-10349, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
45 | Frank E. B. Ophelders, Marco Bekooij, Henk Corporaal |
A tuneable software cache coherence protocol for heterogeneous MPSoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009, pp. 383-392, 2009, ACM, 978-1-60558-628-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
performance, design, reliability |
45 | Jayanta Bhadra, Ekaterina Trofimova, Magdy S. Abadir |
Validating Power ArchitectureTM Technology-Based MPSoCs Through Executable Specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(4), pp. 388-396, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
45 | Roman Obermaisser, Hubert Kraut, Christian El Salloum |
A Transient-Resilient System-on-a-Chip Architecture with Support for On-Chip and Off-Chip TMR. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EDCC ![In: Seventh European Dependable Computing Conference, EDCC-7 2008, Kaunas, Lithuania, 7-9 May 2008, pp. 123-134, 2008, IEEE Computer Society, 978-0-7695-3138-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
45 | Pablo García Del Valle, David Atienza, Ivan Magan, Javier Garcia Flores, Esther Andres Perez, Jose Manuel Mendias, Luca Benini, Giovanni De Micheli |
A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP VLSI-SoC 2006, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Nice, France, 16-18 October 2006, pp. 140-145, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
44 | Yiannis Iosifidis, Arindam Mallik, Stylianos Mamagkakis, Eddy de Greef, Alexandros Bartzas, Dimitrios Soudris, Francky Catthoor |
A framework for automatic parallelization, static and dynamic memory optimization in MPSoC platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 549-554, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
embedded systems, MPSoC, memory optimization |
44 | Bjorn De Sutter, Diederik Verkest, Erik Brockmeyer, Eric Delfosse, Arnout Vandecappelle, Jean-Yves Mignolet |
Design and Tool Flow of Multimedia MPSoC Platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 57(2), pp. 229-247, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Tool flow, Multimedia, Parallelization, Predictability, MPSoC |
44 | Patrice Gerin, Mian Muhammad Hamayun, Frédéric Pétrot |
Native MPSoC co-simulation environment for software performance estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009, pp. 403-412, 2009, ACM, 978-1-60558-628-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
code annotation, MPSoC, system simulation, cross-compilation |
44 | Anders Sejer Tranberg-Hansen, Jan Madsen |
A compositional modelling framework for exploring MPSoC systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009, pp. 1-10, 2009, ACM, 978-1-60558-628-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
MPSoC, system level design, performance estimation |
44 | Gustavo Girão, Bruno Cruz de Oliveira, Rodrigo Soares, Ivan Saraiva Silva |
Cache coherency communication cost in a NoC-based MPSoC platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007, pp. 288-293, 2007, ACM, 978-1-59593-816-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
cache coherence, MPSoC, NoC, directory |
44 | Ozcan Ozturk 0001, Mahmut T. Kandemir, Seung Woo Son 0001, Mustafa Karaköy |
Selective code/data migration for reducing communication energy in embedded MpSoC architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006, pp. 386-391, 2006, ACM, 1-59593-347-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
energy, migration, MPSoC |
44 | Slo-Li Chu |
POERS: A Performance-Oriented Energy Reduction Scheduling Technique for a High-Performance MPSoC Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS (2) ![In: 11th International Conference on Parallel and Distributed Systems, ICPADS 2005, Fuduoka, Japan, July 20-22, 2005, pp. 699-703, 2005, IEEE Computer Society, 0-7695-2281-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
POERS, SAGE II, MPSoC, Processor-in-Memory, Energy Reduction |
44 | Feihui Li, Mahmut T. Kandemir |
Locality-conscious workload assignment for array-based computations in MPSOC architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 95-100, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
MPSoC, data locality |
40 | Ari Kulmala, Erno Salminen, Marko Hännikäinen, Timo D. Hämäläinen |
Evaluating SoC Network Performance in MPEG-4 Encoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 56(2-3), pp. 105-123, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
FPGA multiprocessor, Multiprocessor, System-on-chip, Network-on-chip, MPEG-4, MPSoC, On-chip interconnection |
40 | Lobna Kriaa, Aimen Bouchhima, Marius Gligor, Anne-Marie Fouillart, Frédéric Pétrot, Ahmed Amine Jerraya |
Parallel Programming of Multi-processor SoC: A HW-SW Interface Perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 36(1), pp. 68-92, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
HW/SW interfaces, Programming models, heterogeneous MPSoC |
40 | Grant Martin |
Multi-Processor SoC-Based Design Methodologies Using Configurable and Extensible Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 53(1-2), pp. 113-127, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
MPSoC, programming models, dataflow, instruction-set extension, multiprocessor system-on-chip, configurable processor, electronic system-level design |
40 | Ahmed Amine Jerraya, Aimen Bouchhima, Frédéric Pétrot |
Programming models and HW-SW interfaces abstraction for multi-processor SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 280-285, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
HW/SW interfaces, programming models, heterogeneous MPSoC |
38 | Ines Viskic, Lochi Yu, Daniel Gajski |
Design exploration and automatic generation of MPSoC platform TLMs from Kahn Process Network applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems, LCTES 2010, Stockholm, Sweden, April 13-15, 2010, pp. 77-84, 2010, ACM, 978-1-60558-953-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
kahn process, transaction level model, automatic generation, process network, process mapping |
38 | Hritam Dutta, Frank Hannig, Jürgen Teich |
Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC Using Modular Performance Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS ![In: Architecture of Computing Systems - ARCS 2009, 22nd International Conference, Delft, The Netherlands, March 10-13, 2009. Proceedings, pp. 233-245, 2009, Springer, 978-3-642-00453-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
38 | Hao Shen, Frédéric Pétrot |
Novel task migration framework on configurable heterogeneous MPSoC platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 733-738, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
38 | Katalin Popovici, Ahmed Amine Jerraya |
Flexible and abstract communication and interconnect modeling for MPSoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 143-148, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
38 | Deepak Gangadharan, Samarjit Chakraborty, Roger Zimmermann |
Fast model-based test case classification for performance analysis of multimedia MPSoC platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009, pp. 413-422, 2009, ACM, 978-1-60558-628-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
multimedia, workload, video classification |
38 | Shankar Mahadevan, Federico Angiolini, Jens Sparsø, Luca Benini, Jan Madsen |
A Reactive and Cycle-True IP Emulator for MPSoC Exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(1), pp. 109-122, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
38 | Wayne H. Wolf, Ahmed Amine Jerraya, Grant Martin |
Multiprocessor System-on-Chip (MPSoC) Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(10), pp. 1701-1713, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
38 | Seongnam Kwon, Yongjoo Kim, Woo-Chul Jeun, Soonhoi Ha, Yunheung Paek |
A retargetable parallel-programming framework for MPSoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 13(3), pp. 39:1-39:18, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
parallel-programming, design-space exploration, Embedded software, multiprocessor system on chip, software generation |
38 | Patrice Gerin, Xavier Guerin, Frédéric Pétrot |
Efficient Implementation of Native Software Simulation for MPSoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 676-681, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
38 | Bart D. Theelen |
Performance Model Generation for MPSoC Design-Space Exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
QEST ![In: Fifth International Conference on the Quantitative Evaluaiton of Systems (QEST 2008), 14-17 September 2008, Saint-Malo, France, pp. 39-40, 2008, IEEE Computer Society, 978-0-7695-3360-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
38 | Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa |
A Modular Approach to Model Heterogeneous MPSoC at Cycle Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008, pp. 158-164, 2008, IEEE Computer Society, 978-0-7695-3277-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
38 | Luca Benini, Davide Bertozzi, Michela Milano |
Resource Management Policy Handling Multiple Use-Cases in MPSoC Platforms Using Constraint Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICLP ![In: Logic Programming, 24th International Conference, ICLP 2008, Udine, Italy, December 9-13 2008, Proceedings, pp. 470-484, 2008, Springer, 978-3-540-89981-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
38 | Frank E. B. Ophelders, Samarjit Chakraborty, Henk Corporaal |
Intra- and inter-processor hybrid performance modeling for MPSoC architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008, Atlanta, GA, USA, October 19-24, 2008, pp. 91-96, 2008, ACM, 978-1-60558-470-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
simulation, performance analysis, system-on-chip |
38 | Anders Sejer Tranberg-Hansen, Jan Madsen, Bjørn Sand Jensen |
A service based estimation method for MPSoC performance modelling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIES ![In: IEEE Third International Symposium on Industrial Embedded Systems, SIES 2008, Montpellier / La Grande Motte, France, June 11-13, 2008, pp. 43-50, 2008, IEEE, 978-1-4244-1994-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
38 | Jehangir Khan, Smaïl Niar, Atika Rivenq, Yassin Elhillali, Jean-Luc Dekeyser |
An MPSoC architecture for the Multiple Target Tracking application in driver assistant system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 19th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2008, July 2-4, 2008, Leuven, Belgium, pp. 126-131, 2008, IEEE Computer Society, 978-1-4244-1897-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
38 | Simone Medardoni, Martino Ruggiero, Davide Bertozzi, Luca Benini, Giovanni Strano, Carlo Pistritto |
Interactive presentation: Capturing the interaction of the communication, memory and I/O subsystems in memory-centric industrial MPSoC platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 660-665, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
38 | Vincent Nollet, Diederik Verkest, Henk Corporaal |
A Quick Safari Through the MPSoC Run-Time Management Jungle. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESTIMedia ![In: Proceedings of the 2007 5th Workshop on Embedded Systems for Real-Time Multimedia, ESTIMedia 2007, October 4-5, Salzburg, Austria, conjunction with CODES+ISSS 2007, pp. 41-46, 2007, IEEE Computer Society, 978-1-4244-1654-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
38 | AbdelHalim Samahi, El-Bay Bourennane |
Automated Integration and Communication Synthesis of Reconfigurable MPSoC Platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AHS ![In: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), August 5-8, 2007, University of Edinburgh, Scotland, United Kingdom, pp. 379-385, 2007, IEEE Computer Society, 0-7695-2866-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
38 | Kai Huang 0002, Sang-Il Han, Katalin Popovici, Lisane B. de Brisolara, Xavier Guerin, Lei Li, Xiaolang Yan, Soo-Ik Chae, Luigi Carro, Ahmed Amine Jerraya |
Simulink-Based MPSoC Design Flow: Case Study of Motion-JPEG and H.264. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 39-42, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
38 | Yuan Xie 0001, Wei-Lun Hung |
Temperature-Aware Task Allocation and Scheduling for Embedded Multiprocessor Systems-on-Chip (MPSoC) Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 45(3), pp. 177-189, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
thermal-aware design, scheduling, embedded system design, system-on-chip design |
38 | Junggyu Park, Hyojung Song, Seungmo Cho, Najeong Han, Kyungjeon Kim, Jinman Park |
A Real-time Media Framework for Asymmetric MPSoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISORC ![In: Ninth IEEE International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC 2006), 24-26 April 2006, Gyeongju, Korea, pp. 205-207, 2006, IEEE Computer Society, 0-7695-2561-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
38 | Florin Dumitrascu, Iuliana Bacivarov, Lorenzo Pieralisi, Marius Bonaciu, Ahmed Amine Jerraya |
Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE Designers' Forum ![In: Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 166-171, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-0-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
38 | Wolfgang Klingauf, Hagen Gädke, Robert Günzel |
TRAIN: a virtual transaction layer architecture for TLM-based HW/SW codesign of synthesizable MPSoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 1318-1323, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
38 | Rabie Ben Atitallah, Smaïl Niar, Alain Greiner, Samy Meftali, Jean-Luc Dekeyser |
Estimating Energy Consumption for an MPSoC Architectural Exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS ![In: Architecture of Computing Systems - ARCS 2006, 19th International Conference, Frankfurt/Main, Germany, March 13-16, 2006, Proceedings, pp. 298-310, 2006, Springer, 3-540-32765-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
38 | Peter Flake, Simon J. Davidmann, Frank Schirrmeister |
System-level exploration tools for MPSoC designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 286-287, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
simulation, software development, debugging, multicore |
38 | Shankar Mahadevan, Michael Storgaard, Jan Madsen, Kashif Virk |
ARTS: A System-Level Framework for Modeling MPSoC Components and Analysis of their Causality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MASCOTS ![In: 13th International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS 2005), 27-29 September 2005, Atlanta, GA, USA, pp. 480-483, 2005, IEEE Computer Society, 0-7695-2458-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
38 | Ivan Petkov, Paul Amblard, Marin Hristov |
Systematic Design Flow for Fast Hardware/Software Prototype Generation from Bus Functional Model for MPSoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 8-10 June 2005, Montreal, Canada, pp. 218-224, 2005, IEEE Computer Society, 0-7695-2361-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
38 | Ali Erdem Özcan, Sébastien Jean, Jean-Bernard Stefani |
Bringing Ease and Adaptability to MPSoC Software Design: A Component-Based Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASSIS ![In: Construction and Analysis of Safe, Secure, and Interoperable Smart Devices, Second International Workshop, CASSIS 2005, Nice, France, March 8-11, 2005, Revised Selected Papers, pp. 118-137, 2005, Springer, 3-540-33689-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
38 | Mohamed-Wassim Youssef, Sungjoo Yoo, Arif Sasongko, Yanick Paviot, Ahmed Amine Jerraya |
Debugging HW/SW interface for MPSoC: video encoder system design case study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 908-913, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
hardware-dependant software, hardware-software interface, debug, multiprocessor system-on-chip |
34 | Roberto Airoldi, Fabio Garzia, Tapani Ahonen, Dragomir Milojevic, Jari Nurmi |
Implementation of W-CDMA Cell Search on a FPGA Based Multi-Processor System-on-Chip with Power Management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009. Proceedings, pp. 88-97, 2009, Springer, 978-3-642-03137-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
34 | Leandro Fiorin, Slobodan Lukovic, Gianluca Palermo |
Implementation of a reconfigurable data protection module for NoC-based MPSoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 22nd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008, Miami, Florida USA, April 14-18, 2008, pp. 1-8, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
34 | Love Singhal, Elaheh Bozorgzadeh |
Process variation aware system-level task allocation using stochastic ordering of delay distributions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 570-574, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
34 | Ayse Kivilcim Coskun, Tajana Simunic Rosing, Kenny C. Gross |
Proactive temperature balancing for low cost thermal management in MPSoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 250-257, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
34 | Akash Kumar 0001, Andreas Hansson 0001, Jos Huisken, Henk Corporaal |
Interactive presentation: An FPGA design flow for reconfigurable network-based multi-processor systems on chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 117-122, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
34 | Woo-Chul Jeun, Soonhoi Ha |
Effective OpenMP Implementation and Translation For Multiprocessor System-On-Chip without Using OS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 44-49, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
hardware semaphores, parallel programming, OpenMP, shared memory system, multiprocessor system-on-chip |
34 | Akash Kumar 0001, Shakith Fernando, Yajun Ha, Bart Mesman, Henk Corporaal |
Multi-processor System-level Synthesis for Multiple Applications on Platform FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 92-97, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
34 | Changyun Zhu, Zhenyu (Peter) Gu, Robert P. Dick, Li Shang |
Reliable multiprocessor system-on-chip synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 239-244, 2007, ACM, 978-1-59593-824-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
synthesis, multiprocessor system-on-chip, thermal |
34 | Chong Sun, Li Shang, Robert P. Dick |
Three-dimensional multiprocessor system-on-chip thermal optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 117-122, 2007, ACM, 978-1-59593-824-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
synthesis, 3D, multiprocessor system-on-chip, thermal |
34 | Akira Yamawaki 0002, Masahiko Iwane |
An FPGA implementation of a snoop cache with synchronization for a multiprocessor system-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 13th International Conference on Parallel and Distributed Systems, ICPADS 2007, Hsinchu, Taiwan, December 5-7, 2007, pp. 1-8, 2007, IEEE Computer Society, 978-1-4244-1889-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
34 | Jaehwan John Lee, Vincent John Mooney |
A Novel {O(n)} Parallel Banker's Algorithm for System-on-a-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 17(12), pp. 1377-1389, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Parallel Banker's Algorithm, deadlock avoidance in hardware, multiprocessor system-on-a-chip |
34 | Shankar Mahadevan, Federico Angiolini, Jens Sparsø, Luca Benini, Jan Madsen |
A Traffic Injection Methodology with Support for System-Level Synchronization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: VLSI-SoC: From Systems To Silicon, Proceedings of IFIP TC 10, WG 10.5, Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005), October 17-19, 2005, Perth, Australia, pp. 145-161, 2005, Springer, 978-0-387-73660-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Jaehwan John Lee, Vincent John Mooney III |
A novel O(n) parallel banker's algorithm for System-on-a-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 1304-1308, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Sungjoo Yoo, Mohamed-Wassim Youssef, Aimen Bouchhima, Ahmed Amine Jerraya, Mario Diaz-Nava |
Multi-Processor SoC Design Methodology Using a Concept of Two-Layer Hardware-Dependent Software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 1382-1383, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
34 | Kai Richter 0001, Razvan Racu, Rolf Ernst |
Scheduling Analysis Integration for Heterogeneous Multiprocessor SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTSS ![In: Proceedings of the 24th IEEE Real-Time Systems Symposium (RTSS 2003), 3-5 December 2003, Cancun, Mexico, pp. 236-245, 2003, IEEE Computer Society, 0-7695-2044-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
32 | Nicolas Ventroux, Alexandre Guerre, Tanguy Sassolas, L. Moutaoukil, Guillaume Blanc, Charly Bechara, Raphaël David |
SESAM: An MPSoC Simulation Environment for Dynamic Application Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIT ![In: 10th IEEE International Conference on Computer and Information Technology, CIT 2010, Bradford, West Yorkshire, UK, June 29-July 1, 2010, pp. 1880-1886, 2010, IEEE Computer Society, 978-0-7695-4108-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
SESAM, simulation, modeling, multiprocessor, dynamic, exploration, SystemC, MPSoC |
32 | Francesco Paterna, Andrea Acquaviva, Alberto Caprara, Francesco Papariello, Giuseppe Desoli, Luca Benini |
Variability-tolerant run-time workload allocation for MPSoC energy minimization under real-time constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 7th Conference on Computing Frontiers, 2010, Bertinoro, Italy, May 17-19, 2010, pp. 109-110, 2010, ACM, 978-1-4503-0044-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
real-time, variability, mpsoc, energy minimization |
32 | Zheng Liu, Jueping Cai, Ming Du, Lei Yao, Zan Li |
Hybrid Communication Reconfigurable Network on Chip for MPSoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AINA ![In: 24th IEEE International Conference on Advanced Information Networking and Applications, AINA 2010, Perth, Australia, 20-13 April 2010, pp. 356-361, 2010, IEEE Computer Society, 978-0-7695-4018-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
HCR-NoC, low power, interconnection, MPSoC |
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