Search results for "NFET"

Found 12 publication records. Showing 12 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
36	Sangheon Lee 0005, Jaehyun Park, Hanwool Jeong	Cross-Coupled nFET Preamplifier for Low Voltage SRAM.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
36	Sonu Hooda, Chun-Kuei Chen, Manohar Lal, Shih-Hao Tsai, Evgeny Zamburg, Aaron Voon-Yew Thean	Overcoming Negative nFET VTH by Defect-Compensated Low-Thermal Budget ITO-IGZO Hetero-Oxide Channel to Achieve Record Mobility and Enhancement-mode Operation.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
36	Md Nur K. Alam, Yusuke Higashi, Brecht Truijen, Ben Kaczer, Mihaela Ioana Popovici, Bj O'Sullivan, Philippe Roussel, Robin Degraeve, Marc M. Heyns, Jan Van Houdt	Insight to Data Retention loss in ferroelectric Hf0.5Zr0.5O2 pFET and nFET from simultaneous PV and IV measurements.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
36	M. Iqbal Mahmud, Amit Gupta, Maria Toledano-Luque, N. Rao Mavilla, J. Johnson, P. Srinivasan 0002, A. Zainuddin, S. Rao, Salvatore Cimino, Byoung Min, Tanya Nigam	Hot Carrier Reliability Improvement of Thicker Gate Oxide nFET Devices in Advanced FinFETs.	IRPS	2019	DBLP DOI BibTeX RDF
36	Carlos Suarez-Segovia, Charles Leroux, Florian Domengie, Karen Dabertrand, Vincent Joseph, Giovanni Romano 0003, Pierre Caubet, Stephane Zoll, Olivier Weber, Gérard Ghibaudo, Gilles Reimbold, Michel Haond	Effective work function engineering by sacrificial lanthanum diffusion on HfON-based 14 nm NFET devices.	ESSDERC	2015	DBLP DOI BibTeX RDF
36	Jihoon Jeong, Francois Atallah, Hoan Nguyen, Josh Puckett, Keith A. Bowman, David Hansquine	A 16nm configurable pass-gate bit-cell register file for quantifying the VMIN advantage of PFET versus NFET pass-gate bit cells.	CICC	2015	DBLP DOI BibTeX RDF
36	Nandakumar P. Venugopal, Nihal Shastry, Shambhu J. Upadhyaya	Effect of Process Variation on the Performance of Phase Frequency Detector.	DFT	2006	DBLP DOI BibTeX RDF	Phase Frequency Detector (PFD), NFET, PFET, process variation, Monte Carlo simulation, Jitter, Phase noise
25	Kanak Agarwal	On-die sensors for measuring process and environmental variations in integrated circuits.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	environmental variation, test structure, monitors, sensors, process variation, characterization
25	Vita Pi-Ho Hu, Yu-Sheng Wu, Ming-Long Fan, Pin Su, Ching-Te Chuang	Design and analysis of ultra-thin-body SOI based subthreshold SRAM.	ISLPED	2009	DBLP DOI BibTeX RDF	poisson's equation, subthreshold SRAM, ultra-thin-body, soi, static noise margin
25	Nestoras Tzartzanis, William C. Athas	Clock-Powered CMOS: A Hybrid Adiabatic Logic Style for Energy-Efficient Computing.	ARVLSI	1999	DBLP DOI BibTeX RDF	low-power digital CMOS, adiabatic switching, clock-powered logic, energy recovery
25	C. S. Murthy, M. Gall	Process variation effects on circuit performance: TCAD simulation of 256-Mbit technology [DRAMs].	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
25	Allen C.-H. Wu, Nels Vander Zanden, Daniel Gajski	A new algorithm for transistor sizing in CMOS circuits.	EURO-DAC	1990	DBLP DOI BibTeX RDF