Search results for "Power4"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
73	John M. Ludden, Wolfgang Roesner, Gerry M. Heiling, John R. Reysa, Jonathan R. Jackson, Bing-Lun Chu, Michael L. Behm, Jason Baumgartner, Richard D. Peterson, Jamee Abdulhafiz, William E. Bucy, John H. Klaus, Danny J. Klema, Tien N. Le, F. Danette Lewis, Philip E. Milling, Lawrence A. McConville, Bradley S. Nelson, Viresh Paruthi, Travis W. Pouarz, Audre D. Romonosky, Jeff Stuecheli, Kent D. Thompson, Dave W. Victor, Bruce Wile	Functional verification of the POWER4 microprocessor and POWER4 multiprocessor system.	IBM J. Res. Dev.	2002	DBLP DOI BibTeX RDF
55	Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand	Predicting interconnect requirements in ultra-large-scale integrated control logic circuitry.	SLIP	2005	DBLP DOI BibTeX RDF	wire-length distribution model, routing, interconnect, rent
55	Douglas C. Bossen, Joel M. Tendler, Kevin Reick	Power4 System Design for High Reliability.	IEEE Micro	2002	DBLP DOI BibTeX RDF
37	Gerald G. Lopez, Giovanni Fiorenza, Thomas J. Bucelot, Phillip J. Restle, Mary Yvonne Lanzerotti	Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	load capacitance, routing, application specific integrated circuit (ASIC), clock, power dissipation
37	Guansong Zhang, Francisco Martínez, Arie Tal, Bob Blainey	Busy-Wait Barrier Synchronization Using Distributed Counters with Local Sensor.	WOMPAT	2003	DBLP DOI BibTeX RDF	distributed counter, synchronization, multiprocessor, Barrier
36	Taqi N. Buti, Robert G. McDonald, Zakaria Khwaja, Asit Ambekar, Hung Q. Le, William E. Burky, Bert Williams	Organization and implementation of the register-renaming mapper for out-of-order IBM POWER4 processors.	IBM J. Res. Dev.	2005	DBLP BibTeX RDF
36	Joel M. Tendler, J. Steve Dodson, J. S. Fields Jr., Hung Q. Le, Balaram Sinharoy	POWER4 system microarchitecture.	IBM J. Res. Dev.	2002	DBLP DOI BibTeX RDF
36	James D. Warnock, John M. Keaty, John G. Petrovick, Joachim G. Clabes, Charles J. Kircher, Byron Krauter, Phillip J. Restle, Brian A. Zoric, Carl J. Anderson	The circuit and physical design of the POWER4 microprocessor.	IBM J. Res. Dev.	2002	DBLP DOI BibTeX RDF
36	Douglas C. Bossen, Alongkorn Kitamorn, Kevin Reick, Michael S. Floyd	Fault-tolerant design of the IBM pSeries 690 system using POWER4 processor technology.	IBM J. Res. Dev.	2002	DBLP DOI BibTeX RDF
33	Michael L. Welcome, Charles A. Rendleman, Leonid Oliker, Rupak Biswas	Performance characteristics of an adaptive mesh refinement calculation on scalar and vector platforms.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	IBM power3 and power4, SGI, altix, cray X1E, high end computing, hyperCLaw framework, integrated performance monitoring
33	Raúl Rojas 0001	Reviews.	IEEE Ann. Hist. Comput.	2005	DBLP DOI BibTeX RDF	IBM iSeries, Power4, e-business trends, Galileo's military instrument, copyright legal battles and Whelan Associates, artificial intelligence, software integration, PowerPC, IT industry, policy making
18	Todd Mytkowicz, Peter F. Sweeney, Matthias Hauswirth, Amer Diwan	Time Interpolation: So Many Metrics, So Few Registers.	MICRO	2007	DBLP DOI BibTeX RDF
18	Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand	Impact of interconnect length changes on effective materials properties (dielectric constant).	SLIP	2007	DBLP DOI BibTeX RDF	performance, routing, interconnect, cycle time, interconnect model, rent, path delay
18	Jaime H. Moreno	Chip-level integration: the new frontier for microprocessor architecture.	SPAA	2006	DBLP DOI BibTeX RDF	chip-level integration, microprocessor architecture
18	Yingmin Li, David M. Brooks, Zhigang Hu, Kevin Skadron	Performance, Energy, and Thermal Considerations for SMT and CMP Architectures.	HPCA	2005	DBLP DOI BibTeX RDF
18	Hans M. Jacobson, Pradip Bose, Zhigang Hu, Alper Buyuktosunoglu, Victor V. Zyuban, Richard J. Eickemeyer, Lee Eisen, John Griswell, Doug Logan, Balaram Sinharoy, Joel M. Tendler	Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors.	HPCA	2005	DBLP DOI BibTeX RDF
18	Ying Chen, Dennis Abts, David J. Lilja	Efficiently generating test vectors with state pruning.	ASP-DAC	2005	DBLP DOI BibTeX RDF
18	Wei Huang 0004, Eric Humenay, Kevin Skadron, Mircea R. Stan	The need for a full-chip and package thermal model for thermally optimized IC designs.	ISLPED	2005	DBLP DOI BibTeX RDF	leakage, package, thermal model, temperature-aware design
18	Soraya Ghiasi, Tom W. Keller, Freeman L. Rawson III	Scheduling for heterogeneous processors in server systems.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	scheduling, performance, power, heterogeneous processors
18	Pawel J. Matuszyk, Krzysztof Boryczko	A Parallel Preconditioning for the Nonlinear Stokes Problem.	PPAM	2005	DBLP DOI BibTeX RDF
18	Prasad Jayanti, Srdjan Petrovic	Efficiently Implementing a Large Number of LL/SC Objects.	OPODIS	2005	DBLP DOI BibTeX RDF
18	Prasad Jayanti, Srdjan Petrovic	Efficiently Implementing LL/SC Objects Shared by an Unknown Number of Processes.	IWDC	2005	DBLP DOI BibTeX RDF
18	Ronald N. Kalla, Balaram Sinharoy, Joel M. Tendler	IBM Power5 Chip: A Dual-Core Multithreaded Processor.	IEEE Micro	2004	DBLP DOI BibTeX RDF
18	Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand	Interpretation of rent's rule for ultralarge-scale integrated circuit designs, with an application to wirelength distribution models.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
18	Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand	Assessment of on-chip wire-length distribution models.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
18	A. J. KleinOsowski, David J. Lilja	The NanoBox Project: Exploring Fabrics of Self-Correcting Logic Blocks for High Defect Rate Molecular Device Technologies.	ISVLSI	2004	DBLP DOI BibTeX RDF
18	Jonathan Carter, Julian Borrill, Leonid Oliker	Performance Characteristics of a Cosmology Package on Leading HPC Architectures.	HiPC	2004	DBLP DOI BibTeX RDF
18	Gorden Griem, Leonid Oliker, John Shalf, Katherine A. Yelick	Identifying Performance Bottlenecks on Modern Microarchitectures Using an Adaptable Probe.	IPDPS	2004	DBLP DOI BibTeX RDF
18	Ying Chen, Dennis Abts, David J. Lilja	State Pruning for Test Vector Generation for a Multiprocessor Cache Coherence Protocol.	IEEE International Workshop on Rapid System Prototyping	2004	DBLP DOI BibTeX RDF
18	Leonid Oliker, Rupak Biswas, Julian Borrill, Andrew Canning, Jonathan Carter, M. Jahed Djomehri, Hongzhang Shan, David Skinner	A Performance Evaluation of the Cray X1 for Scientific Applications.	VECPAR	2004	DBLP DOI BibTeX RDF
18	Mary Y. L. Wisniewski, Emmanuel Yashchin, Robert L. Franch, David P. Conrady, Daniel N. Maynard, Giovanni Fiorenza, I. Cevdet Noyan	The physical design of on-chip interconnections.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
18	M. Jahed Djomehri, Rupak Biswas	Performance Analysis of a Hybrid Overset Multi-block Application on Multiple Architectures.	HiPC	2003	DBLP DOI BibTeX RDF
18	Wolfgang Roesner	What Is beyond the RTL Horizon for Microprocessor and System Design?	CHARME	2003	DBLP DOI BibTeX RDF
18	Prasad Jayanti, Srdjan Petrovic	Efficient and practical constructions of LL/SC variables.	PODC	2003	DBLP DOI BibTeX RDF
18	Mark F. Adams, Harun H. Bayraktar, Tony M. Keaveny, Panayiotis Papadopoulos	Applications of Algebraic Multigrid to Large-Scale Finite Element Analysis of Whole Bone Micro-Mechanics on the IBM SP.	SC	2003	DBLP DOI BibTeX RDF	trabecular bone, human vertebral body, finite element method, multigrid, massively parallel computing
18	Siegfried Höfinger, Torsten Schindler, András Aszódi	Parallel Global Optimization of High-Dimensional Problems.	PVM/MPI	2002	DBLP DOI BibTeX RDF