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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 34 occurrences of 29 keywords
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Results
Found 36 publication records. Showing 36 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
73 | John M. Ludden, Wolfgang Roesner, Gerry M. Heiling, John R. Reysa, Jonathan R. Jackson, Bing-Lun Chu, Michael L. Behm, Jason Baumgartner, Richard D. Peterson, Jamee Abdulhafiz, William E. Bucy, John H. Klaus, Danny J. Klema, Tien N. Le, F. Danette Lewis, Philip E. Milling, Lawrence A. McConville, Bradley S. Nelson, Viresh Paruthi, Travis W. Pouarz, Audre D. Romonosky, Jeff Stuecheli, Kent D. Thompson, Dave W. Victor, Bruce Wile |
Functional verification of the POWER4 microprocessor and POWER4 multiprocessor system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IBM J. Res. Dev. ![In: IBM J. Res. Dev. 46(1), pp. 53-76, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
55 | Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand |
Predicting interconnect requirements in ultra-large-scale integrated control logic circuitry. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings, pp. 43-50, 2005, ACM, 1-59593-033-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
wire-length distribution model, routing, interconnect, rent |
55 | Douglas C. Bossen, Joel M. Tendler, Kevin Reick |
Power4 System Design for High Reliability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 22(2), pp. 16-24, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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37 | Gerald G. Lopez, Giovanni Fiorenza, Thomas J. Bucelot, Phillip J. Restle, Mary Yvonne Lanzerotti |
Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 38-43, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
load capacitance, routing, application specific integrated circuit (ASIC), clock, power dissipation |
37 | Guansong Zhang, Francisco Martínez, Arie Tal, Bob Blainey |
Busy-Wait Barrier Synchronization Using Distributed Counters with Local Sensor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WOMPAT ![In: OpenMP Shared Memory Parallel Programming, International Workshop on OpenMP Applications and Tools, WOMPAT 2003, Toronto, Canada, June 26-27, 2003, Proceedings, pp. 84-98, 2003, Springer, 3-540-40435-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
distributed counter, synchronization, multiprocessor, Barrier |
36 | Taqi N. Buti, Robert G. McDonald, Zakaria Khwaja, Asit Ambekar, Hung Q. Le, William E. Burky, Bert Williams |
Organization and implementation of the register-renaming mapper for out-of-order IBM POWER4 processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IBM J. Res. Dev. ![In: IBM J. Res. Dev. 49(1), pp. 167-188, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP BibTeX RDF |
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36 | Joel M. Tendler, J. Steve Dodson, J. S. Fields Jr., Hung Q. Le, Balaram Sinharoy |
POWER4 system microarchitecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IBM J. Res. Dev. ![In: IBM J. Res. Dev. 46(1), pp. 5-26, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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36 | James D. Warnock, John M. Keaty, John G. Petrovick, Joachim G. Clabes, Charles J. Kircher, Byron Krauter, Phillip J. Restle, Brian A. Zoric, Carl J. Anderson |
The circuit and physical design of the POWER4 microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IBM J. Res. Dev. ![In: IBM J. Res. Dev. 46(1), pp. 27-52, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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36 | Douglas C. Bossen, Alongkorn Kitamorn, Kevin Reick, Michael S. Floyd |
Fault-tolerant design of the IBM pSeries 690 system using POWER4 processor technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IBM J. Res. Dev. ![In: IBM J. Res. Dev. 46(1), pp. 77-86, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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33 | Michael L. Welcome, Charles A. Rendleman, Leonid Oliker, Rupak Biswas |
Performance characteristics of an adaptive mesh refinement calculation on scalar and vector platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the Third Conference on Computing Frontiers, 2006, Ischia, Italy, May 3-5, 2006, pp. 393-402, 2006, ACM, 1-59593-302-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
IBM power3 and power4, SGI, altix, cray X1E, high end computing, hyperCLaw framework, integrated performance monitoring |
33 | Raúl Rojas 0001 |
Reviews. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Ann. Hist. Comput. ![In: IEEE Ann. Hist. Comput. 27(4), pp. 86-88, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
IBM iSeries, Power4, e-business trends, Galileo's military instrument, copyright legal battles and Whelan Associates, artificial intelligence, software integration, PowerPC, IT industry, policy making |
18 | Todd Mytkowicz, Peter F. Sweeney, Matthias Hauswirth, Amer Diwan |
Time Interpolation: So Many Metrics, So Few Registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 1-5 December 2007, Chicago, Illinois, USA, pp. 286-300, 2007, IEEE Computer Society, 0-7695-3047-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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18 | Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand |
Impact of interconnect length changes on effective materials properties (dielectric constant). ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings, pp. 73-80, 2007, ACM, 978-1-59593-622-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
performance, routing, interconnect, cycle time, interconnect model, rent, path delay |
18 | Jaime H. Moreno |
Chip-level integration: the new frontier for microprocessor architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPAA ![In: SPAA 2006: Proceedings of the 18th Annual ACM Symposium on Parallelism in Algorithms and Architectures, Cambridge, Massachusetts, USA, July 30 - August 2, 2006, pp. 328, 2006, ACM, 1-59593-452-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
chip-level integration, microprocessor architecture |
18 | Yingmin Li, David M. Brooks, Zhigang Hu, Kevin Skadron |
Performance, Energy, and Thermal Considerations for SMT and CMP Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 12-16 February 2005, San Francisco, CA, USA, pp. 71-82, 2005, IEEE Computer Society, 0-7695-2275-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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18 | Hans M. Jacobson, Pradip Bose, Zhigang Hu, Alper Buyuktosunoglu, Victor V. Zyuban, Richard J. Eickemeyer, Lee Eisen, John Griswell, Doug Logan, Balaram Sinharoy, Joel M. Tendler |
Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 12-16 February 2005, San Francisco, CA, USA, pp. 238-242, 2005, IEEE Computer Society, 0-7695-2275-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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18 | Ying Chen, Dennis Abts, David J. Lilja |
Efficiently generating test vectors with state pruning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 1196-1199, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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18 | Wei Huang 0004, Eric Humenay, Kevin Skadron, Mircea R. Stan |
The need for a full-chip and package thermal model for thermally optimized IC designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 245-250, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
leakage, package, thermal model, temperature-aware design |
18 | Soraya Ghiasi, Tom W. Keller, Freeman L. Rawson III |
Scheduling for heterogeneous processors in server systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the Second Conference on Computing Frontiers, 2005, Ischia, Italy, May 4-6, 2005, pp. 199-210, 2005, ACM, 1-59593-019-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
scheduling, performance, power, heterogeneous processors |
18 | Pawel J. Matuszyk, Krzysztof Boryczko |
A Parallel Preconditioning for the Nonlinear Stokes Problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PPAM ![In: Parallel Processing and Applied Mathematics, 6th International Conference, PPAM 2005, Poznan, Poland, September 11-14, 2005, Revised Selected Papers, pp. 534-541, 2005, Springer, 3-540-34141-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Prasad Jayanti, Srdjan Petrovic |
Efficiently Implementing a Large Number of LL/SC Objects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OPODIS ![In: Principles of Distributed Systems, 9th International Conference, OPODIS 2005, Pisa, Italy, December 12-14, 2005, Revised Selected Papers, pp. 17-31, 2005, Springer, 3-540-36321-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Prasad Jayanti, Srdjan Petrovic |
Efficiently Implementing LL/SC Objects Shared by an Unknown Number of Processes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWDC ![In: Distributed Computing - IWDC 2005, 7th International Workshop, Kharagpur, India, December 27-30, 2005, Proceedings, pp. 45-56, 2005, Springer, 3-540-30959-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Ronald N. Kalla, Balaram Sinharoy, Joel M. Tendler |
IBM Power5 Chip: A Dual-Core Multithreaded Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 24(2), pp. 40-47, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand |
Interpretation of rent's rule for ultralarge-scale integrated circuit designs, with an application to wirelength distribution models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 12(12), pp. 1330-1347, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand |
Assessment of on-chip wire-length distribution models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 12(10), pp. 1108-1112, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | A. J. KleinOsowski, David J. Lilja |
The NanoBox Project: Exploring Fabrics of Self-Correcting Logic Blocks for High Defect Rate Molecular Device Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), Emerging Trends in VLSI Systems Design, 19-20 February 2004, Lafayette, LA, USA, pp. 19-24, 2004, IEEE Computer Society, 0-7695-2097-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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18 | Jonathan Carter, Julian Borrill, Leonid Oliker |
Performance Characteristics of a Cosmology Package on Leading HPC Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: High Performance Computing - HiPC 2004, 11th International Conference, Bangalore, India, December 19-22, 2004, Proceedings, pp. 176-188, 2004, Springer, 3-540-24129-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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18 | Gorden Griem, Leonid Oliker, John Shalf, Katherine A. Yelick |
Identifying Performance Bottlenecks on Modern Microarchitectures Using an Adaptable Probe. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), CD-ROM / Abstracts Proceedings, 26-30 April 2004, Santa Fe, New Mexico, USA, 2004, IEEE Computer Society, 0-7695-2132-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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18 | Ying Chen, Dennis Abts, David J. Lilja |
State Pruning for Test Vector Generation for a Multiprocessor Cache Coherence Protocol. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 15th IEEE International Workshop on Rapid System Prototyping (RSP 2004), 28-30 June 2004, Geneva, Switzerland, pp. 74-77, 2004, IEEE Computer Society, 0-7695-2159-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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18 | Leonid Oliker, Rupak Biswas, Julian Borrill, Andrew Canning, Jonathan Carter, M. Jahed Djomehri, Hongzhang Shan, David Skinner |
A Performance Evaluation of the Cray X1 for Scientific Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VECPAR ![In: High Performance Computing for Computational Science - VECPAR 2004, 6th International Conference, Valencia, Spain, June 28-30, 2004, Revised Selected and Invited Papers, pp. 51-65, 2004, Springer, 3-540-25424-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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18 | Mary Y. L. Wisniewski, Emmanuel Yashchin, Robert L. Franch, David P. Conrady, Daniel N. Maynard, Giovanni Fiorenza, I. Cevdet Noyan |
The physical design of on-chip interconnections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(3), pp. 254-276, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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18 | M. Jahed Djomehri, Rupak Biswas |
Performance Analysis of a Hybrid Overset Multi-block Application on Multiple Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: High Performance Computing - HiPC 2003, 10th International Conference, Hyderabad, India, December 17-20, 2003, Proceedings, pp. 383-392, 2003, Springer, 3-540-20626-4. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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18 | Wolfgang Roesner |
What Is beyond the RTL Horizon for Microprocessor and System Design? ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHARME ![In: Correct Hardware Design and Verification Methods, 12th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2003, L'Aquila, Italy, October 21-24, 2003, Proceedings, pp. 1, 2003, Springer, 3-540-20363-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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18 | Prasad Jayanti, Srdjan Petrovic |
Efficient and practical constructions of LL/SC variables. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PODC ![In: Proceedings of the Twenty-Second ACM Symposium on Principles of Distributed Computing, PODC 2003, Boston, Massachusetts, USA, July 13-16, 2003, pp. 285-294, 2003, ACM, 1-58113-708-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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18 | Mark F. Adams, Harun H. Bayraktar, Tony M. Keaveny, Panayiotis Papadopoulos |
Applications of Algebraic Multigrid to Large-Scale Finite Element Analysis of Whole Bone Micro-Mechanics on the IBM SP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE SC2003 Conference on High Performance Networking and Computing, 15-21 November 2003, Phoenix, AZ, USA, CD-Rom, pp. 26, 2003, ACM, 1-58113-695-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
trabecular bone, human vertebral body, finite element method, multigrid, massively parallel computing |
18 | Siegfried Höfinger, Torsten Schindler, András Aszódi |
Parallel Global Optimization of High-Dimensional Problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PVM/MPI ![In: Recent Advances in Parallel Virtual Machine and Message Passing Interface, 9th European PVM/MPI Users' Group Meeting, Linz, Austria, September 29 - October 2, 2002, Proceedings, pp. 148-155, 2002, Springer, 3-540-44296-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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