Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
132 | Massimo Panella, Giuseppe Martinelli |
An RNS Architecture for Quasi-Chaotic Oscillators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 33(1-2), pp. 199-220, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
RNS quasi-chaotic oscillators, RNS, secure communication, primitive polynomials |
104 | Luiz Maltar, Felipe M. G. França, Vladimir Castro Alves, Cláudio L. Amorim |
Implementation of RNS Addition and RNS Multiplication into FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 15-17 April 1998, Napa Valley, CA, USA, pp. 331-332, 1998, IEEE Computer Society, 0-8186-8900-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
100 | Gian Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re |
Programmable power-of-two RNS scaler and its application to a QRNS polyphase filter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1102-1105, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
87 | Salvatore Pontarelli, Gian Carlo Cardarilli, Marco Re, Adelio Salsano |
A Novel Error Detection and Correction Technique for RNS Based FIR Filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA, pp. 436-444, 2008, IEEE Computer Society, 978-0-7695-3365-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
87 | Leonel Sousa |
Efficient Method for Magnitude Comparison in RNS Based on Two Pairs of Conjugate Moduli. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 18th IEEE Symposium on Computer Arithmetic (ARITH-18 2007), 25-27 June 2007, Montpellier, France, pp. 240-250, 2007, IEEE Computer Society, 0-7695-2854-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
87 | Jean-Claude Bajard, Laurent Imbert |
A Full RNS Implementation of RSA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(6), pp. 769-774, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
87 | Neil Burgess |
Scaling an RNS Number Using the Core Function. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 16th IEEE Symposium on Computer Arithmetic (Arith-16 2003), 15-18 June 2003, Santiago de Compostela, Spain, pp. 262-, 2003, IEEE Computer Society, 0-7695-1894-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
87 | Javier Ramírez 0001, Antonio García 0001, Pedro G. Fernández, Luis Parrilla 0001, Antonio Lloris-Ruíz |
Analysis of RNS-FPL Synergy for High Throughput DSP Applications: Discrete Wavelet Transform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 342-351, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
83 | Andreas Persson, Lars Bengtsson |
Forward and Reverse Converters and Moduli Set Selection in Signed-Digit Residue Number Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 56(1), pp. 1-15, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Signed-digit, Moduli-selection, Residue number system, FIR filters, Converters |
83 | Shin-ichi Kawamura, Masanobu Koike, Fumihiko Sano, Atsushi Shimbo |
Cox-Rower Architecture for Fast Parallel Montgomery Multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROCRYPT ![In: Advances in Cryptology - EUROCRYPT 2000, International Conference on the Theory and Application of Cryptographic Techniques, Bruges, Belgium, May 14-18, 2000, Proceeding, pp. 523-538, 2000, Springer, 3-540-67517-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
83 | Alexander Skavantzos, Thanos Stouraitis |
Grouped-moduli residue number systems for fast signal processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 478-483, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
82 | Shang Ma, Jianhao Hu, Lin Zhang, Xiang Ling 0002 |
An efficient RNS parity checker for moduli set {2 n - 1, 2 n + 1, 22 n + 1} and its applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Ser. F Inf. Sci. ![In: Sci. China Ser. F Inf. Sci. 51(10), pp. 1563-1571, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
number comparison, sign determination, overflow detection, VLSI, RNS, parity check |
78 | Inseop Lee, W. Kenneth Jenkins |
The Design of Residue Number System Arithmetic Units for A VLSI Adaptive Equalizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 19-21 February 1998, Lafayette, LA, USA, pp. 179-184, 1998, IEEE Computer Society, 0-8186-8409-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
residue number, LMS, RNS |
73 | Shugang Wei |
Number conversions between RNS and mixed-radix number system based on Modulo (2p - 1) signed-digit arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2005, Florianolpolis, Brazil, September 4-7, 2005, pp. 160-165, 2005, ACM. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
73 | Andrea Del Re, Alberto Nannarelli, Marco Re |
A Tool for Automatic Generation of RTL-Level VHDL Description of RNS FIR Filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 686-687, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
73 | Wei Wang 0003, M. N. S. Swamy, M. Omair Ahmad |
RNS Application for Digital Image Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 19-21 July 2004, Banff, Alberta, Canada, pp. 77-80, 2004, IEEE Computer Society, 0-7695-2182-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
73 | Javier Ramírez 0001, Antonio García 0001, Uwe Meyer-Bäse, Fred J. Taylor, Antonio Lloris-Ruíz |
Implementation of RNS-Based Distributed Arithmetic Discrete Wavelet Transform Architectures Using Field-Programmable Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 33(1-2), pp. 171-190, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
field-programmable logic, digital signal processing, discrete wavelet transform, residue number system, distributed arithmetic |
73 | Peter R. Turner |
Fraction-Free RNS Algorithms for Solving Linear Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 13th Symposium on Computer Arithmetic (ARITH-13 '97), 6-9 July 1997, Asilomar, CA, USA, pp. 218-217, 1997, IEEE Computer Society, 0-8186-7846-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
69 | Aaron So, Ben Liang 0001 |
A Lagrangian Approach for the Optimal Placement of Wireless Relay Nodes in Wireless Local Area Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Networking ![In: NETWORKING 2006 - Networking Technologies, Services, and Protocols; Performance of Computer and Communication Networks; Mobile and Wireless Communications Systems, 5th International IFIP-TC6 Networking Conference, Coimbra, Portugal, May 15-19, 2006, Proceedings, pp. 160-172, 2006, Springer, 3-540-34192-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
immobile relays, optimal placement, WLAN, throughput capacity |
69 | Chunsheng Liu, Krishnendu Chakrabarty |
Compact Dictionaries for Fault Diagnosis in Scan-BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(6), pp. 775-780, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
69 | Matthias Nickles, Michael Rovatsos, Gerhard Weiß 0001 |
A Schema for Specifying Computational Autonomy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESAW ![In: Engineering Societies in the Agents World III, Third International Workshop, ESAW 2002, Madrid, Spain, September 16-17, 2002, Revised Papers, pp. 82-95, 2002, Springer, 3-540-14009-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
69 | W. Kenneth Jenkins, Bernard A. Schnaufer, Andrew J. Mansen |
Combined system-level redundancy and modular arithmetic for fault tolerant digital signal processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 11th Symposium on Computer Arithmetic, 29 June - 2 July 1993, Windsor, Canada, Proceedings., pp. 28-35, 1993, IEEE Computer Society/, 0-8186-3862-1. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
68 | Javier Ramírez 0001, Uwe Meyer-Bäse, Fred J. Taylor, Antonio García 0001, Antonio Lloris-Ruíz |
Design and Implementation of High-Performance RNS Wavelet Processors Using Custom IC Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 34(3), pp. 227-237, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
RNS arithmetic, custom integrated circuit, field-programmable logic devices, discrete wavelet transform |
68 | Uwe Meyer-Bäse, Antonio García 0001, Fred J. Taylor |
Implementation of a Communications Channelizer using FPGAs and RNS Arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 28(1-2), pp. 115-128, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
field-programmable logic (FPL), complex programmable logic devices (CPLD), zero-IF filter, field programmable gate array (FPGA), digital signal processing (DSP), residue number system (RNS), channelizer |
65 | Gerhard Weiß 0001, Michael Rovatsos, Matthias Nickles |
Capturing agent autonomy in roles and XML. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AAMAS ![In: The Second International Joint Conference on Autonomous Agents & Multiagent Systems, AAMAS 2003, July 14-18, 2003, Melbourne, Victoria, Australia, Proceedings, pp. 105-112, 2003, ACM, 1-58113-683-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
XRNS, computational autonomy, XML, specification, agent-oriented software engineering, RNS |
64 | M. N. Mahesh, Mahesh Mehendale |
Low Power Realization of Residue Number System Based FIR Filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India, pp. 30-33, 2000, IEEE Computer Society, 0-7695-0487-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Low power implementation, DSP, Residue Number System(RNS), FIR filters |
64 | Jean-Claude Bajard, Laurent-Stéphane Didier, Peter Kornerup |
An IWS Montgomery Modular Multiplication Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 13th Symposium on Computer Arithmetic (ARITH-13 '97), 6-9 July 1997, Asilomar, CA, USA, pp. 234-239, 1997, IEEE Computer Society, 0-8186-7846-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
RNS Montgomery modular multiplication algorithm, very large operands, mixed radix, processor ring, redundant high-radix implementation, residue number systems, residue number system, computation time, table look-up |
59 | Pedro Miguens Matutino, Leonel Sousa |
An RNS based Specific Processor for Computing the Minimum Sum-of-Absolute-Differences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008, pp. 768-775, 2008, IEEE Computer Society, 978-0-7695-3277-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
59 | Uwe Meyer-Bäse, Thanos Stouraitis |
New power-of-2 RNS scaling scheme for cell-based IC design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(2), pp. 280-283, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
59 | Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou |
Deterministic BIST for RNS Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 52(7), pp. 896-906, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
deterministic and pseudorandom tests, formal test sets, Built-In Self-Test, Residue Number System |
59 | Dimitrios Soudris, K. Sgouropoulos, Konstantinos Tatas, Vasilis F. Pavlidis, Adonios Thanailakis |
A methodology for implementing FIR filters and CAD tool development for designing RNS-based systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 129-132, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
59 | Hanae Nozaki, Masahiko Motoyama, Atsushi Shimbo, Shin-ichi Kawamura |
Implementation of RSA Algorithm Based on RNS Montgomery Multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2001, Third International Workshop, Paris, France, May 14-16, 2001, Proceedings, pp. 364-376, 2001, Springer, 3-540-42521-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
RSA cryptography, residue number systems, Montgomery multiplication, modular exponentiation |
55 | A. S. Madhukumar, Francois P. S. Chin |
Enhanced architecture for residue number system-based CDMA for high-rate data transmission. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Wirel. Commun. ![In: IEEE Trans. Wirel. Commun. 3(5), pp. 1363-1368, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
55 | Wu Woan Kim, Sang-Dong Jang |
Multiplier with Parallel CSA Using CRT's Specific Moduli (2k-1, 2k , 2k+1). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCSA (2) ![In: Computational Science and Its Applications - ICCSA 2004, International Conference, Assisi, Italy, May 14-17, 2004, Proceedings, Part II, pp. 216-225, 2004, Springer, 3-540-22056-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
55 | Ricardo Chaves, Leonel Sousa |
RDSP: A RISC DSP based on Residue Number System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), Architectures, Methods and Tools, 3-5 September 2003, Belek-Antalya, Turkey, pp. 128-137, 2003, IEEE Computer Society, 0-7695-2003-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
55 | Jean-Claude Bajard, Laurent-Stéphane Didier, Peter Kornerup |
Modular Multiplication and Base Extensions in Residue Number Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 11-17 June 2001, Vail, CO, USA, pp. 59-65, 2001, IEEE Computer Society, 0-7695-1150-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
50 | Jean-Claude Bajard, Laurent Imbert, Pierre-Yvan Liardet, Yannick Teglia |
Leak Resistant Arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2004: 6th International Workshop Cambridge, MA, USA, August 11-13, 2004. Proceedings, pp. 62-75, 2004, Springer, 3-540-22666-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
RNS Montgomery multiplication, Side channel attacks, residue number systems |
50 | Ansgar Drolshagen, Walter Anheier, C. Chandra Sekhar |
A Residue Number Arithmetic based Circuit for Pipelined Computation of Autocorrelation Coefficients of Speech Signal. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 122-127, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
modulo arithmetic circuits, RNS compiler, Autocorrelator circuit, Residue number systems |
45 | Ioannis Kouretas, Vassilis Paliouras |
Mixed Radix-2 and High-Radix RNS Bases for Low-Power Multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers, pp. 93-102, 2008, Springer, 978-3-540-95947-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
45 | Shahana Thottathikkulam Kassim, Babita R. Jose, Rekha K. James, K. Poulose Jacob, Sreela Sasi |
RNS Based Programmable Multi-Mode Decimation Filter for WCDMA and WiMAX. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTC Spring ![In: Proceedings of the 67th IEEE Vehicular Technology Conference, VTC Spring 2008, 11-14 May 2008, Singapore, pp. 1831-1835, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
45 | Shahana Thottathikkulam Kassim, Babita R. Jose, Rekha K. James, K. Poulose Jacob, Sreela Sasi |
Dual-mode RNS based programmable decimation filter for WCDMA and WLANa. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 952-955, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
45 | G. L. Bernocchi, Gian Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re |
Low-power adaptive filter based on RNS components. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3211-3214, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
45 | Dimitrios M. Schinianakis, Apostolos P. Fournaris, Athanasios Kakarountas, Thanos Stouraitis |
An RNS architecture of an Fp elliptic curve point multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
45 | Su-Hon Lin, Ming-Hwa Sheu, Jing-Shiun Lin, Wen-Tsai Sheu |
Efficient VLSI Design for RNS Reverse Converter Based on New Moduli Set (2n-1, 2n+1, 22n+1). ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 2020-2023, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
45 | Daniel González, Luis Parrilla 0001, Antonio García 0001, Encarnación Castillo, Antonio Lloris-Ruíz |
Efficient Clock Distribution Scheme for VLSI RNS-Enabled Controllers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings, pp. 657-665, 2005, Springer, 3-540-29013-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
45 | Ricardo Chaves, Leonel Sousa |
{2n+1, sn+k, sn-1}: A New RNS Moduli Set Extension. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August - 3 September 2004, Rennes, France, pp. 210-217, 2004, IEEE Computer Society, 0-7695-2203-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
45 | Luis Parrilla 0001, Encarnación Castillo, Antonio García 0001, Antonio Lloris-Ruíz |
Intellectual Property Protection for RNS Circuits on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings, pp. 1139-1141, 2004, Springer, 3-540-22989-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
45 | Javier Ramírez 0001, Uwe Meyer-Bäse, Antonio García 0001, Antonio Lloris-Ruíz |
Design and Implementation of RNS-Based Adaptive Filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings, pp. 1135-1138, 2003, Springer, 3-540-40822-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
45 | Javier Ramírez 0001, Antonio García 0001 |
U. Meyer-Baese, A. Lloris: Fast RNS FPL-based Communications Receiver Design and Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 472-481, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
45 | Adimathara P. Preethy, Damu Radhakrishnan, Amos Omondi |
Fault-tolerance scheme for an RNS MAC: performance and cost analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 717-720, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
45 | B. J. Kirsch, Peter R. Turner |
Adaptive beamforming using RNS arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 11th Symposium on Computer Arithmetic, 29 June - 2 July 1993, Windsor, Canada, Proceedings., pp. 36-43, 1993, IEEE Computer Society/, 0-8186-3862-1. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
41 | Rooju Chokshi, Krzysztof S. Berezowski, Aviral Shrivastava, Stanislaw J. Piestrak |
Exploiting residue number system for power-efficient digital signal processing in embedded processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2009, Grenoble, France, October 11-16, 2009, pp. 19-28, 2009, ACM. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
compiler, power, processor, residue number system, per- |
41 | Wenxuan Guo, Xinming Huang 0001, Wenjing Lou, Cao Liang |
On Relay Node Placement and Assignment for Two-tiered Wireless Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Mob. Networks Appl. ![In: Mob. Networks Appl. 13(1-2), pp. 186-197, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
two-tiered wireless network, optimal relayed path, packet reception rate, BIP, relay node placement |
41 | Andreas Lindahl, Lars Bengtsson |
A Low-Power FIR Filter Using Combined Residue and Radix-2 Signed-Digit Representation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August - 3 September 2005, Porto, Portugal, pp. 42-47, 2005, IEEE Computer Society, 0-7695-2433-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
41 | Quanhong Wang, Glen Takahara, Hossam S. Hassanein, Kenan Xu |
On Relay Node Placement and Locally Optimal Traffic Allocation in Heterogeneous Wireless Sensor Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCN ![In: 30th Annual IEEE Conference on Local Computer Networks (LCN 2005), 15-17 November 2005, Sydney, Australia, Proceedings, pp. 656-664, 2005, IEEE Computer Society, 0-7695-2421-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Device Placement, Variable Transmission Range, Wireless Sensor Networks, Cost, Lifetime |
41 | Hyun-Sung Kim, Hee-Joo Park, Sung-Ho Hwang |
Parallel Modular Multiplication Algorithm in Residue Number System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PPAM ![In: Parallel Processing and Applied Mathematics, 5th International Conference, PPAM 2003, Czestochowa, Poland, September 7-10, 2003. Revised Papers, pp. 1028-1033, 2003, Springer, 3-540-21946-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
41 | Alberto Nannarelli, Marco Re, Gian Carlo Cardarilli |
Tradeoffs between residue number system and traditional FIR filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 305-308, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
41 | Xipeng Xiao, Lionel M. Ni |
Parallel Routing Table Computation for Scalable IP Routers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CANPC ![In: Network-Based Parallel Computing: Communication, Architecture, and Applications, Second International Workshop, CANPC '98, Las Vegas, Nevada, USA, January 31 - February 1, 1998, Proceedings, pp. 144-158, 1998, Springer, 3-540-64140-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
41 | Alexander Skavantzos |
An Efficient Residue to Weighted Converter for a New Residue Number System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 19-21 February 1998, Lafayette, LA, USA, pp. 185-191, 1998, IEEE Computer Society, 0-8186-8409-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
41 | Jenn-Dong Sun, Hari Krishna, K.-Y. Lin |
A superfast algorithm for single-error correction in rrns and hardware implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 6(3), pp. 259-269, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
40 | Antonio García 0001, Antonio Lloris-Ruíz |
A Look-Up Scheme for Scaling in the RNS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 48(7), pp. 748-751, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
look-up table implementation, scaling, Residue number system (RNS) |
40 | Richard Conway 0001, John S. Nelson |
Fast Converter for 3 Moduli RNS Using New Property of CRT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 48(8), pp. 852-860, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Residue number system (RNS) converter, Chinese remainder theorem (CRT) |
36 | Javad Ahsan, Mohammad Esmaeildoust, Amer Kaabi, Vahid Zarei |
Efficient FPGA implementation of RNS Montgomery multiplication using balanced RNS bases. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 84, pp. 72-83, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
36 | Libey Djath |
RNS-Flexible hardware accelerators for high-security asymmetric cryptography. (Accélérateurs matériels RNS flexibles pour la cryptographie asymétrique à haute sécurité). ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2021 |
RDF |
|
36 | Jérôme Courtois |
Leak study of cryptosystem implementations in randomized RNS arithmetic. (Étude des fuites d'implémentations de cryptosystème en arithmétique RNS randomisée). ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2020 |
RDF |
|
36 | Eric B. Olsen |
RNS Hardware Matrix Multiplier for High Precision Neural Network Acceleration: "RNS TPU". ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy, pp. 1-5, 2018, IEEE, 978-1-5386-4881-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
36 | Shiva Taghipour Eivazi, Mehdi Hosseinzadeh 0001, Ahmad Habibizad Navin |
Efficient RNS Converter via Two-Part RNS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 24(1), pp. 1550016:1-1550016:12, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
36 | Julien Eynard |
Approche arithmétique RNS de la cryptographie asymétrique. (RNS arithmetic approach of asymmetric cryptography). ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2015 |
RDF |
|
36 | Stefan Bienert |
RNA Energetics And Sequence Design (Betrachtungen der Energie von RNS und RNS Sequenzgestaltung) ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2015 |
RDF |
|
32 | Riyaz A. Patel, Mohammed Benaissa, Said Boussakta |
Fast Modulo 2n - (2n-2+1) Addition: A New Class of Adder for RNS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(4), pp. 572-576, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
modular adder, VLSI, Computer arithmetic, residue number system, parallel-prefix adder |
32 | Dimitris G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou |
Efficient BIST schemes for RNS datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 573-576, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
32 | Wei Wang 0003, M. N. S. Swamy, M. Omair Ahmad |
Moduli selection in RNS for efficient VLSI implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 512-515, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
32 | Ioannis Kouretas, Vassilis Paliouras |
High-radix redundant circuits for RNS modulo rn-1, rn, or rn+1. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 229-232, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
32 | Daniel González, Antonio García 0001, Graham A. Jullien, Javier Ramírez 0001, Luis Parrilla 0001, Antonio Lloris-Ruíz |
A New Methodology for Efficient Synchronization of RNS-Based VLSI Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation, 12th International Workshop, PATMOS 2002, Seville, Spain, September 11-13, 2002, pp. 188-197, 2002, Springer, 3-540-44143-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
32 | Marco Re, Alberto Nannarelli, Gian Carlo Cardarilli, Roberto Lojacono |
FPGA realization of RNS to binary signed conversion architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 350-353, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
32 | D. J. Soudris, Minas Dasygenis, Spyridoula K. Vasilopoulou, Adonios Thanailakis |
A CAD tool for architecture level exploration and automatic generation of RNS converters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 730-733, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
32 | Antonio García 0001, Uwe Meyer-Bäse, Antonio Lloris-Ruíz, Fred J. Taylor |
RNS implementation of FIR filters based on distributed arithmetic using field-programmable logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 486-489, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
32 | Yuke Wang, Xiaoyu Song, El Mostapha Aboulhamid |
A New Algorithm for RNS Magnitude Comparison Based on New Chinese Remainder Theorem II. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 4-6 March 1999, Ann Arbor, MI, USA, pp. 362-, 1999, IEEE Computer Society, 0-7695-0104-4. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
32 | Ahmad A. Hiasat, Hoda S. Abdel-Aty-Zohdy |
Design and Implementation of An RNS Division Algorithmm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 13th Symposium on Computer Arithmetic (ARITH-13 '97), 6-9 July 1997, Asilomar, CA, USA, pp. 240-249, 1997, IEEE Computer Society, 0-8186-7846-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
28 | Anand Srinivas, Eytan H. Modiano |
Joint Node Placement and Assignment for Throughput Optimization in Mobile Backbone Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
INFOCOM ![In: INFOCOM 2008. 27th IEEE International Conference on Computer Communications, Joint Conference of the IEEE Computer and Communications Societies, 13-18 April 2008, Phoenix, AZ, USA, pp. 1130-1138, 2008, IEEE, 978-1-4244-2026-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
28 | Zhang Zhang |
On the Application of Directional Antenna to Two Hop Relay System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTC Spring ![In: Proceedings of the 65th IEEE Vehicular Technology Conference, VTC Spring 2007, 22-25 April 2007, Dublin, Ireland, pp. 3130-3134, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
28 | W. Kenneth Jenkins, Chandrasekhar Radhakrishnan, Siddharth Pal |
Fault Tolerant Signal Processing for Masking Transient Errors in VLSI Signal Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 2570-2573, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
28 | Tuukka Toivonen, Janne Heikkilä |
Video filtering with Fermat number theoretic transforms using residue number system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. Video Technol. ![In: IEEE Trans. Circuits Syst. Video Technol. 16(1), pp. 92-101, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Andreas Persson, Lars Bengtsson |
Reverse conversion architectures for signed-digit residue number systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Grace Y. Cho, Louis G. Johnson, Michael A. Soderstrand |
Residue number system implementations of complex heterodyne tunable filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 548-551, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
28 | Bin Cao, Chip-Hong Chang, Thambipillai Srikanthan |
New efficient residue-to-binary converters for 4-moduli set {2n - 1, 2n, 2n + 1, 2n+1 - 1}. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 536-539, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
28 | Jimson Mathew, Elena Dubrova |
Self-Checking 1-out-of-n CMOS Current-Mode Checker. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 6-8 November 2002, Vancouver, BC, Canada, Proceedings, pp. 69-77, 2002, IEEE Computer Society, 0-7695-1831-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
28 | M. N. Mahesh, Mahesh Mehendale |
Improving performance of high precision signal processing algorithms on programmable DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 488-491, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
28 | Jean-Claude Bajard, Laurent-Stéphane Didier, Jean-Michel Muller |
A New Euclidean Division Algorithm for Residue Number Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 19(2), pp. 167-178, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
28 | Neil Burgess |
Scaled and Unscaled Residue Number System to Binary Conversion Techniques using the Core Function. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 13th Symposium on Computer Arithmetic (ARITH-13 '97), 6-9 July 1997, Asilomar, CA, USA, pp. 250-, 1997, IEEE Computer Society, 0-8186-7846-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Scaled Conversion, Core Function, Conversion, Residue Number System |
28 | Vassilis Paliouras, Thanos Stouraitis |
Area-time performance of VLSI FIR filter architectures based on residue arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 23rd EUROMICRO Conference '97, New Frontiers of Information Technology, 1-4 September 1997, Budapest, Hungary, pp. 576-583, 1997, IEEE Computer Society, 0-8186-8129-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
area-time performance optimization, VLSI FIR filter architectures, FIR processors, moduli bases, binary-to-residue conversion complexity, residue-to-binary conversion complexity, multiply-by-constant units, binary structures, performance models, Chinese remainder theorem, residue number system, FIR filters, residue arithmetic |
28 | Giuseppe Alia, Enrico Martinelli |
A VLSI structure forX(modm) operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 1(4), pp. 257-264, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
23 | Kooroush Manochehri, Saadat Pourmozafari, Babak Sadeghiyan |
Efficient Methods in Converting to Modulo 2^n+1 and 2^n-1. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITNG ![In: Third International Conference on Information Technology: New Generations (ITNG 2006), 10-12 April 2006, Las Vegas, Nevada, USA, pp. 178-185, 2006, IEEE Computer Society, 0-7695-2497-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Diminished-1, RNS, Modular multiplication, CSA, Wallace tree |
23 | Reto Zimmermann |
Efficient VLSI Implementation of Modulo (2^n=B11) Addition and Multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 14th IEEE Symposium on Computer Arithmetic (Arith-14 '99), 14-16 April 1999, Adelaide, Australia, pp. 158-167, 1999, IEEE Computer Society, 0-7695-0116-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Modulo (2^n=B11) adders and multipliers, end-around-carry parallel-prefix adders, IDEA cipher, cryptography, computer arithmetic, RNS, VLSI circuits |
23 | Chien-Chun Su, Hao-Yung Lo |
An Algorithm for Scaling and Single Residue Error Correction in Residue Number Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 39(8), pp. 1053-1064, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
single residue digit error correction, mixed radix conversion, redundant digits, scaling error, error-correction circuit with scaling, fault tolerant computing, digital signal processing, digital arithmetic, error correction, residue number systems, RNS, fault-tolerant systems, digital signal processing chips, number theory, lookup table |
22 | Shugang Wei, Kensuke Shimizu |
Error Detection of Arithmetic Circuits Using a Residue Checker with Signed-Digit Number System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 24-26 October 2001, San Francisco, CA, USA, Proceedings, pp. 72-77, 2001, IEEE Computer Society, 0-7695-1203-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
residue addition, residue multiplication, signed-digit(SD) number representation, SD adder, error detection, residue number system(RNS) |
22 | Ching Yu Hung, Behrooz Parhami |
Error Analysis of Approximate Chinese-Reminder-Theorem Decoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 44(11), pp. 1344-1348, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
residue numbers, RNS representation, scaled decoding, computer arithmetic, Computation errors |
22 | Jermy C. Smith, Fred J. Taylor |
A Fault-Tolerant GEQRNS Processing Element for Linear Systolic Array DSP Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 44(9), pp. 1121-1130, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Fault-tolerant, redundancy, DSP, systolic array, VLSI design, residue number system (RNS), yield enhancement |
22 | Ben-Dau Tseng, Graham A. Jullien, William C. Miller |
Implementation of FFT Structures Using the Residue Number System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 28(11), pp. 831-844, 1979. The full citation details ...](Pics/full.jpeg) |
1979 |
DBLP DOI BibTeX RDF |
ROM arrays, FFT structures, high-speed filters, optimum hardware realization, Error analysis, residue number system (RNS) |
18 | Ravikumar Selvam, Akhilesh Tyagi |
Residue Number System (RNS) and Power Distribution Network Topology-Based Mitigation of Power Side-Channel Attacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Cryptogr. ![In: Cryptogr. 8(1), pp. 1, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|