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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 6 occurrences of 6 keywords
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Results
Found 6 publication records. Showing 6 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
159 | Harald P. E. Vranken, Tom Waayers, Hérvé Fleury, David Lelouvier |
Enhanced Reduced Pin-Count Test for Full-Scan Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 18(2), pp. 129-143, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
reduced pin-count test, core test, design for testability, ATE, boundary-scan test, scan test |
79 | Jay Jahangiri, Nilanjan Mukherjee 0001, Wu-Tung Cheng, Subramanian Mahadevan, Ron Press |
Achieving High Test Quality with Reduced Pin Count Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 312-317, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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63 | A. Dehghani, F. Shabani, Patricia Nava |
Off-Line Recognition of Isolated Persian Handwritten Characters Using Multiple Hidden Markov Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITCC ![In: 2001 International Symposium on Information Technology (ITCC 2001), 2-4 April 2001, Las Vegas, NV, USA, pp. 506-510, 2001, IEEE Computer Society, 0-7695-1062-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
RPCT, CME, HMM, OCR |
42 | Prakash Srinivasan, Ronan Farrell |
Hierarchical DFT with Combinational Scan Compression, Partition Chain and RPCT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2010, 5-7 July 2010, Lixouri Kefalonia, Greece, pp. 52-57, 2010, IEEE Computer Society, 978-0-7695-4076-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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42 | Yuan Yan Tang, Ching Y. Suen |
RPCT Algorithm and its VLSI Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Syst. Man Cybern. Syst. ![In: IEEE Trans. Syst. Man Cybern. Syst. 24(1), pp. 87-99, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
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26 | Sandeep Kumar Goel, Erik Jan Marinissen |
On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 44-49, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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