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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 5 occurrences of 5 keywords
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Results
Found 16 publication records. Showing 16 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
71 | Alireza Ejlali, Bashir M. Al-Hashimi, Marcus T. Schmitz, Paul M. Rosinger, Seyed Ghassem Miremadi |
Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(4), pp. 323-335, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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62 | Rajesh Garg, Sunil P. Khatri |
Efficient analytical determination of the SEU-induced pulse shape. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 461-467, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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60 | Ahmad Patooghy, Mahdi Fazeli, Seyed Ghassem Miremadi |
A Low-Power and SEU-Tolerant Switch Architecture for Network on Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 13th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2007), 17-19 December, 2007, Melbourne, Victoria, Australia, pp. 264-267, 2007, IEEE Computer Society, 0-7695-3054-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
SEU-Tolerance, Power Consumption, NoC |
45 | Rajesh Garg, Sunil P. Khatri |
A novel, highly SEU tolerant digital circuit design approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 14-20, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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35 | Chong Zhao, Sujit Dey |
Improving Transient Error Tolerance of Digital VLSI Circuits Using RObustness COmpiler (ROCO). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 133-140, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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29 | Rui Gong, Wei Chen 0009, Fang Liu 0002, Kui Dai, Zhiying Wang 0003 |
A New Approach to Single Event Effect Tolerance Based on Asynchronous Circuit Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 24(1-3), pp. 57-65, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
SEE tolerance, SEU tolerance, SET tolerance, Asynchronous circuit |
28 | Takashi Yoshida, Kazutoshi Kobayashi, Jun Furuta |
Total Ionizing Dose Effects by alpha irradiation on circuit performance and SEU tolerance in thin BOX FDSOI process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 25th IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2019, Rhodes, Greece, July 1-3, 2019, pp. 236-238, 2019, IEEE, 978-1-7281-2490-2. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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28 | Ahmed S. Sajit, Michael A. Turi |
SEU tolerance of FinFET 6T SRAM, 8T SRAM and DICE memory cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCWC ![In: IEEE 7th Annual Computing and Communication Workshop and Conference, CCWC 2017, Las Vegas, NV, USA, January 9-11, 2017, pp. 1-5, 2017, IEEE, 978-1-5090-4228-9. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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28 | Igor Villata, Unai Bidarte, Uli Kretzschmar, Armando Astarloa, Jesús Lázaro 0001 |
Fast and accurate SEU-tolerance characterization method for Zynq SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1-4, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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28 | Wei Wei 0034, Fabrizio Lombardi, Kazuteru Namba |
Designs and analysis of non-volatile memory cells for single event upset (SEU) tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2014, Amsterdam, The Netherlands, October 1-3, 2014, pp. 69-74, 2014, IEEE Computer Society, 978-1-4799-6155-9. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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28 | Seokjoong Kim, Matthew R. Guthaus |
Dynamic voltage scaling for SEU-tolerance in low-power memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012, pp. 207-212, 2012, IEEE, 978-1-4673-2657-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
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28 | Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato |
A routing architecture exploration for coarse-grained reconfigurable architecture with automated seu-tolerance evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: Annual IEEE International SoC Conference, SoCC 2010, September 27-29, 2010, Las Vegas, NV, USA, Proceedings, pp. 248-253, 2010, IEEE, 978-1-4244-6682-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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28 | Toshimasa Funaki, Toshinori Sato |
Formulating MITF for a Multicore Processor with SEU Tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008, pp. 234-241, 2008, IEEE Computer Society, 978-0-7695-3277-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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28 | Costas Argyrides, Fabian Vargas 0001, Marlon Moraes, Dhiraj K. Pradhan |
Embedding Current Monitoring in H-Tree RAM Architecture for Multiple SEU Tolerance and Reliability Improvement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 7-9 July 2008, Rhodes, Greece, pp. 155-160, 2008, IEEE Computer Society, 978-0-7695-3264-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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28 | Alireza Ejlali, Marcus T. Schmitz, Bashir M. Al-Hashimi, Seyed Ghassem Miremadi, Paul M. Rosinger |
Energy efficient SEU-tolerance in DVS-enabled real-time systems through information redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 281-286, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
single event upset (SEU), dynamic voltage scaling (DVS), information redundancy |
22 | Chong Zhao, Yi Zhao, Sujit Dey |
Intelligent Robustness Insertion for Optimal Transient Error Tolerance Improvement in VLSI Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(6), pp. 714-724, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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Displaying result #1 - #16 of 16 (100 per page; Change: )
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