Search results for "SEU-Tolerance"

Found 16 publication records. Showing 16 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
71	Alireza Ejlali, Bashir M. Al-Hashimi, Marcus T. Schmitz, Paul M. Rosinger, Seyed Ghassem Miremadi	Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
62	Rajesh Garg, Sunil P. Khatri	Efficient analytical determination of the SEU-induced pulse shape.	ASP-DAC	2009	DBLP DOI BibTeX RDF
60	Ahmad Patooghy, Mahdi Fazeli, Seyed Ghassem Miremadi	A Low-Power and SEU-Tolerant Switch Architecture for Network on Chips.	PRDC	2007	DBLP DOI BibTeX RDF	SEU-Tolerance, Power Consumption, NoC
45	Rajesh Garg, Sunil P. Khatri	A novel, highly SEU tolerant digital circuit design approach.	ICCD	2008	DBLP DOI BibTeX RDF
35	Chong Zhao, Sujit Dey	Improving Transient Error Tolerance of Digital VLSI Circuits Using RObustness COmpiler (ROCO).	ISQED	2006	DBLP DOI BibTeX RDF
29	Rui Gong, Wei Chen 0009, Fang Liu 0002, Kui Dai, Zhiying Wang 0003	A New Approach to Single Event Effect Tolerance Based on Asynchronous Circuit Technique.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	SEE tolerance, SEU tolerance, SET tolerance, Asynchronous circuit
28	Takashi Yoshida, Kazutoshi Kobayashi, Jun Furuta	Total Ionizing Dose Effects by alpha irradiation on circuit performance and SEU tolerance in thin BOX FDSOI process.	IOLTS	2019	DBLP DOI BibTeX RDF
28	Ahmed S. Sajit, Michael A. Turi	SEU tolerance of FinFET 6T SRAM, 8T SRAM and DICE memory cells.	CCWC	2017	DBLP DOI BibTeX RDF
28	Igor Villata, Unai Bidarte, Uli Kretzschmar, Armando Astarloa, Jesús Lázaro 0001	Fast and accurate SEU-tolerance characterization method for Zynq SoCs.	FPL	2014	DBLP DOI BibTeX RDF
28	Wei Wei 0034, Fabrizio Lombardi, Kazuteru Namba	Designs and analysis of non-volatile memory cells for single event upset (SEU) tolerance.	DFT	2014	DBLP DOI BibTeX RDF
28	Seokjoong Kim, Matthew R. Guthaus	Dynamic voltage scaling for SEU-tolerance in low-power memories.	VLSI-SoC	2012	DBLP DOI BibTeX RDF
28	Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato	A routing architecture exploration for coarse-grained reconfigurable architecture with automated seu-tolerance evaluation.	SoCC	2010	DBLP DOI BibTeX RDF
28	Toshimasa Funaki, Toshinori Sato	Formulating MITF for a Multicore Processor with SEU Tolerance.	DSD	2008	DBLP DOI BibTeX RDF
28	Costas Argyrides, Fabian Vargas 0001, Marlon Moraes, Dhiraj K. Pradhan	Embedding Current Monitoring in H-Tree RAM Architecture for Multiple SEU Tolerance and Reliability Improvement.	IOLTS	2008	DBLP DOI BibTeX RDF
28	Alireza Ejlali, Marcus T. Schmitz, Bashir M. Al-Hashimi, Seyed Ghassem Miremadi, Paul M. Rosinger	Energy efficient SEU-tolerance in DVS-enabled real-time systems through information redundancy.	ISLPED	2005	DBLP DOI BibTeX RDF	single event upset (SEU), dynamic voltage scaling (DVS), information redundancy
22	Chong Zhao, Yi Zhao, Sujit Dey	Intelligent Robustness Insertion for Optimal Transient Error Tolerance Improvement in VLSI Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF