Search results for "SFG"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
108	Andrew Stone, Elias S. Manolakos	Minimal Complexity Hierarchical Loop Representations of SFG Processors for Optimal High Level Synthesis.	ASAP	2000	DBLP DOI BibTeX RDF	Optimal VHDL, DG2VHDL, Hierarchical CDFG, High Level Synthesis, Dependence Graph, Signal Flow Graph, Design Complexity
95	Jae Chung, Mark Claypool, Robert E. Kinicki	Stochastic Fair Traffic Management for Efficient and Robust IP Networking.	IPCCC	2007	DBLP DOI BibTeX RDF
76	Laurens Bierens, Ed F. Deprettere	Efficient Partitioning of Algorithms for Long Convolutions and their Mapping onto Architectures.	J. VLSI Signal Process.	1998	DBLP DOI BibTeX RDF
76	Filip Van Aelten, Jonathan Allen, Srinivas Devadas	Event-based verification of synchronous, globally controlled, logic designs against signal flow graphs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
57	M. Helena Fino, José E. da Franca, Adolfo Steiger-Garção	Automatic symbolic analysis of switched-capacitor filtering networks using signal flow graphs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
51	Zülküf Genç	SFG: smart flooding by gossiping.	CoNEXT	2005	DBLP DOI BibTeX RDF	mobile ad hoc networks, flooding, information dissemination, reliable multicast, epidemic
38	Kazuo Aoyama	Design Methods for Symmetric Function Generators Based on Threshold Elements.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
38	Renè Jensen, Yngvar Berg	Dual Data-Rate Cyclic D/A Converter Using Semi Floating-Gate Devices.	ISMVL	2007	DBLP DOI BibTeX RDF
38	Miao Zhu, Fang Lin Luo	Steady-State Performance Analysis of Cascade Boost Converters.	APCCAS	2006	DBLP DOI BibTeX RDF
38	Omid Mirmotahari, Yngvar Berg	A Novel Multiple-Input Multiple-Valued Semi-Floating-Gate LATC.	ISMVL	2003	DBLP DOI BibTeX RDF
38	F. Rosati, Paolo Campolucci, Francesco Piazza	Learning in linear and nonlinear multirate digital systems by signal flow graphs.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
38	Sree Ganesan, Ranga Vemuri	Library Binding for High-Level Synthesis of Analog Systems.	VLSI Design	2001	DBLP DOI BibTeX RDF
38	Chao-Huang Chang, Gilbert K. Krulee	Resolution of ambiguity in Chinese and its application to machine translation.	Mach. Transl.	1991	DBLP DOI BibTeX RDF	ambiguity typology, serial verb construction, predication ambiguity, semantic functional grammar, disambiguation, Chinese
34	Peter F. A. Middelhoek, Sreeranga P. Rajan	From VHDL to efficient and first-time-right designs: a formal approach.	ACM Trans. Design Autom. Electr. Syst.	1996	DBLP DOI BibTeX RDF	CDFG, SFG, rapid system prototyping, VHDL, VHDL, design methodology, correctness by construction, transformational design
33	S. Ramanathan, V. Visvanathan	A systolic architecture for LMS adaptive filtering with minimal adaptation delay.	VLSI Design	1996	DBLP DOI BibTeX RDF	LMS adaptive filtering, minimal adaptation delay, convergence behaviour, function preserving transformations, SFG representation, carry-save arithmetic, systolic folded pipelined architecture, VLSI, delays, systolic arrays, pipeline processing, adaptive filters, digital filters, digital signal processing chips, convergence of numerical methods, systolic architecture, signal flow graphs, signal flow graph, least mean squares methods, LMS algorithm
32	Mahmood Hussain Bhat, Trung-Hieu Le, Shih-Chia Huang	SFG-Net: an Efficient Image to Image Translation Approach for Synthetic Fog Generation.	ICCE-TW	2022	DBLP DOI BibTeX RDF
32	Soheila Nazari, Karim Faez	Novel systematic mathematical computation based on the spiking frequency gate (SFG): Innovative organization of spiking computer.	Inf. Sci.	2019	DBLP DOI BibTeX RDF
32	Li-Chun Liao, Kuo-Wei Chien	The large-signal SFG model of DC-DC buck-boost converters.	iCAST	2017	DBLP DOI BibTeX RDF
32	Rahul Bhattacharya, S. H. M. Ragamai, Subindu Kumar	SFG Based Fault Simulation of Linear Analog Circuits Using Fault Classification and Sensitivity Analysis.	VDAT	2017	DBLP DOI BibTeX RDF
32	Jia Yao, Jianfeng Zhao 0001, Alexander Abramovitz	Modeling of the Tapped Inductor SEPIC converter by the TIS-SFG approach.	IECON	2015	DBLP DOI BibTeX RDF
32	Barbara Magnani, Francesca Frassinetti, Thomas Ditye, Massimiliano Oliveri, Marcello Costantini, Vincent Walsh	Left insular cortex and left SFG underlie prismatic adaptation effects on time perception: Evidence from fMRI.	NeuroImage	2014	DBLP DOI BibTeX RDF
32	Basireddy Karunakar Reddy, Srinivas Sabbavarapu, Amit Acharyya	Effect of Constant One and Zero, Shared and Non-decomposed Nodes on Runtime and Graph Size of the Shannon Factor Graph (SFG).	ISED	2014	DBLP DOI BibTeX RDF
32	Mourad Fakhfakh, Marian Pierzchala	Synthesis of active inductors using SFG stamps.	Microelectron. J.	2013	DBLP DOI BibTeX RDF
32	C. R. Wan, David J. Evans 0001	Systolic Array Synthesis using SFG Representations.	Int. J. Comput. Math.	2002	DBLP DOI BibTeX RDF
32	Zhao Shujiang	Designing OTA-C filters by SFG approach.	ISCAS	1993	DBLP BibTeX RDF
32	Mark Genoe, Luc J. M. Claesen, Eric Verlind, Frank Proesmans, Hugo De Man	Illustration of the SFG-Tracing Multi-Level Behavioral Verification Methodology, by the Correctness Proof of a High to Low Level Synthesis Application in CATHEDRAL-II.	ICCD	1991	DBLP DOI BibTeX RDF
19	Omid Mirmotahari, Yngvar Berg	Proposal for a Bidirectional Gate Using Pseudo Floating-Gate.	DELTA	2008	DBLP DOI BibTeX RDF	floating-gate (FG), multiple-valued logic (MVL), bidirectional
19	Chih-Chun Lin 0001, Damon Shing-Min Liu	An intelligent virtual piano tutor.	VRCIA	2006	DBLP DOI BibTeX RDF	fingering problem, virtual pianist, computer animation, inverse kinematics
19	Miao Zhu, Fang Lin Luo	Generalized Steady-State Analysis on Developed Series of Cascade Boost Converters.	APCCAS	2006	DBLP DOI BibTeX RDF
19	Henning Gundersen, Renè Jensen, Yngvar Berg	A Novel Ternary Switching Element Using CMOS Recharge Semi Floating-Gate Devices.	ISMVL	2005	DBLP DOI BibTeX RDF
19	Yngvar Berg, Snorre Aunet, Øivind Næss, Omid Mirmotahari	Basic Multiple-Valued Functions Using Recharge CMOS Logic.	ISMVL	2004	DBLP DOI BibTeX RDF
19	Omid Mirmotahari, Yngvar Berg	A Systolic Parallel Multiplier over GF(3m) Using Neuron-MOS DLC.	ISMVL	2004	DBLP DOI BibTeX RDF
19	Omid Mirmotahari, Yngvar Berg	A Novel D-Latch in Multiple-Valued Semi-Floating-Gate Recharged Logic.	ISMVL	2004	DBLP DOI BibTeX RDF
19	Yngvar Berg, Snorre Aunet, Omid Mirmotahari, Mats Høvin	Novel recharge semi-floating-gate CMOS logic for multiple-valued systems.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
19	Kazuo Aoyama, Hiroshi Sawada	Threshold Element-Based Symmetric Function Generators and Their Functional Extension.	FPL	2002	DBLP DOI BibTeX RDF
19	S. Ramanathan, V. Visvanathan, S. K. Nandy 0001	Architectural Synthesis of Computational Engines for Subband Adaptive Filtering.	J. VLSI Signal Process.	1999	DBLP DOI BibTeX RDF
19	Roy A. Sutton, Vason P. Srini, Jan M. Rabaey	A Multiprocessor DSP System Using PADDI-2.	DAC	1998	DBLP DOI BibTeX RDF
19	Hong-Shin Jun, Sun-Young Hwang	Design of a pipelined datapath synthesis system for digital signal processing.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF