|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 28 occurrences of 26 keywords
|
|
|
Results
Found 30 publication records. Showing 30 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
43 | Menghui Zheng, Alexander Albicki |
Low power and high speed multiplication design through mixed number representations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 566-576, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
high speed multiplication, mixed number representations, low power multiplication, reduced switching, Sign-Magnitude, Redundant Binary adder, Booth decoder, Carry-Propagation-Free, digital arithmetic, VLSI architecture, redundant number systems, Partial Products |
32 | Mi Lu, Jen-Shiun Chiang |
A Novel Division Algorithm for the Residue Number System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 41(8), pp. 1026-1032, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
sign magnitude arithmetic division, signed number division, overflow detection, digital arithmetic, search problems, residue number system, number theory, binary search, algorithm theory, dividing circuits, parity checking, sign detection, division algorithm |
32 | Stamatis Vassiliadis, Eric M. Schwarz, Baik Moon Sung |
Hard-Wired Multipliers with Encoded Partial Products. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 40(11), pp. 1181-1197, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
hardwired multipliers, encoded partial products, multibit overlapped scanning multiplication algorithm, sign-magnitude, encoding, digital arithmetic, multiplying circuits, two's complement |
23 | Oscal T.-C. Chen, Robin R.-B. Sheen, S. Wang |
A low-power adder operating on effective dynamic data ranges. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 10(4), pp. 435-453, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Hyochan An, Yu Chen 0070, Zichen Fan, Qirui Zhang 0001, Pierre Abillama, Hun-Seok Kim, David T. Blaauw, Dennis Sylvester |
An 8.09TOPS/W Neural Engine Leveraging Bit-Sparsified Sign-Magnitude Multiplications and Dual Adder Trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid- State Circuits Conference, ISSCC 2023, San Francisco, CA, USA, February 19-23, 2023, pp. 422-423, 2023, IEEE, 978-1-6654-9016-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
22 | Gennaro Di Meo, Davide De Caro, Nicola Petra, Antonio G. M. Strollo |
A novel low-power DLMS adaptive filter with sign-magnitude learning and approximated FIR section. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRIME ![In: 17th Conference on Ph.D Research in Microelectronics and Electronics, PRIME 2022, Villasimius, SU, Italy, June 12-15, 2022, pp. 217-220, 2022, IEEE, 978-1-6654-6700-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Oguz Meteer, Arvid B. Van Den Brink, Marco Jan Gerrit Bekooij |
Energy-Efficient Radix-4 Belief Propagation Polar Code Decoding Using an Efficient Sign-Magnitude Adder and Clock Gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 25th Euromicro Conference on Digital System Design, DSD 2022, Maspalomas, Spain, August 31 - Sept. 2, 2022, pp. 126-133, 2022, IEEE, 978-1-6654-7404-7. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Gayas Mohiuddin Sayed, Matthias Kuhl |
Miniaturized Sign-Magnitude Stochastic-Binary FIR Filter Architecture with Enhanced Accuracy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, SBCCI 2022, Porto Alegre, Brazil, August 22-26, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-8128-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Oguz Meteer, Marco Jan Gerrit Bekooij |
Low-Power Sign-Magnitude FFT Design for FMCW Radar Signal Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DASIP ![In: DASIP '21: Workshop on Design and Architectures for Signal and Image Processing (14th edition) - in conjunction with HiPEAC 2021, Budapest, Hungary, January 18-20, 2021, pp. 52-59, 2021, ACM, 978-1-4503-8901-3. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
22 | Francisco José Orts Gómez, Gloria Ortega López, Ester M. Garzón |
An optimized quantum circuit for converting from sign-magnitude to two's complement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Quantum Inf. Process. ![In: Quantum Inf. Process. 18(11), pp. 332, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
22 | Luc Waeijen, Hailong Jiao, Henk Corporaal, Yifan He |
Datawidth-Aware Energy-Efficient Multipliers: A Case for Going Sign Magnitude. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 21st Euromicro Conference on Digital System Design, DSD 2018, Prague, Czech Republic, August 29-31, 2018, pp. 54-61, 2018, IEEE Computer Society, 978-1-5386-7377-5. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
22 | Lukas Balles, Philipp Hennig |
Dissecting Adam: The Sign, Magnitude and Variance of Stochastic Gradients. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICML ![In: Proceedings of the 35th International Conference on Machine Learning, ICML 2018, Stockholmsmässan, Stockholm, Sweden, July 10-15, 2018, pp. 413-422, 2018, PMLR. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
22 | Aidyn Zhakatayev, Sugil Lee, Hyeon Uk Sim, Jongeun Lee |
Sign-magnitude SC: getting 10X accuracy for free in stochastic computing for deep neural networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 55th Annual Design Automation Conference, DAC 2018, San Francisco, CA, USA, June 24-29, 2018, pp. 158:1-158:6, 2018, ACM, 978-1-5386-4114-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
22 | Saeid Gorgin 0001, Ghassem Jaberipur |
Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 25(1), pp. 75-86, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
22 | Slava Voloshynovskiy, Taras Holotyak, Fokko Beekhof |
Soft Content Fingerprinting With Bit Polarization Based on Sign-Magnitude Decomposition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Inf. Forensics Secur. ![In: IEEE Trans. Inf. Forensics Secur. 10(10), pp. 2033-2047, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
22 | Svyatoslav Voloshynovskiy, Taras Holotyak, Oleksiy J. Koval, Fokko Beekhof, Farzad Farhadzadeh |
Sign-magnitude decomposition of mutual information with polarization effect in digital identification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITW ![In: 2011 IEEE Information Theory Workshop, ITW 2011, Paraty, Brazil, October 16-20, 2011, pp. 385-389, 2011, IEEE, 978-1-4577-0438-3. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
21 | Charles G. Boncelet Jr. |
Lossless Image Compression with BCTW. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIP ![In: Proceedings of the International Conference on Image Processing, ICIP 2006, October 8-11, Atlanta, Georgia, USA, pp. 2281-2284, 2006, IEEE, 1-4244-0480-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj |
Analytical estimation of signal transition activity from word-level statistics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(7), pp. 718-733, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
10 | Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis |
Built-in sequential fault self-testing of array multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(3), pp. 449-460, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
10 | Stuart F. Oberman, Michael Y. Siu |
A High-Performance Area-Efficient Multifunction Interpolator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 27-29 June 2005, Cape Cod, MA, USA, pp. 272-279, 2005, IEEE Computer Society, 0-7695-2366-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
10 | Peter-Michael Seidel, Guy Even |
Delay-Optimized Implementation of IEEE Floating-Point Addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(2), pp. 97-113, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
IEEE rounding, dual path algorithm, optimized gate sizing, buffer insertion, delay optimization, logical effort, Floating-point addition |
10 | Nikolaus Voß, Bärbel Mertsching |
A Framework for Low Power Audio Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 1048-, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Ahmet T. Erdogan, Tughrul Arslan |
Low power block based FIR filtering cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 341-344, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
10 | Chien-Chung Chua, Bah-Hwee Gwee, Joseph Sylvester Chang |
A low-voltage micropower asynchronous multiplier for a multiplierless FIR filter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 381-384, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
10 | Syed Mahfuzul Aziz, C. N. Basheer, Joarder Kamruzzaman |
A Synthesisable VHDL Model for an Easily Testable Generalised Multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 1st IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2002), 29-31 January 2002, Christchurch, New Zealand, pp. 504-506, 2002, IEEE Computer Society, 0-7695-1453-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Modified Booth, Generic, Synthesis, VHDL, Multiplier, C-Testable |
10 | Peter-Michael Seidel, Guy Even |
On the Design of Fast IEEE Floating-Point Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 11-17 June 2001, Vail, CO, USA, pp. 184-194, 2001, IEEE Computer Society, 0-7695-1150-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
10 | V. A. Bartlett, Eckhard Grass |
A Low-Power Asynchronous VLSI FIR Filter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 19th Conference on Advanced Research in VLSI (ARVLSI 2001), 14-16 March 2001, Salt Lake City, UT, USA, pp. 29-41, 2001, IEEE Computer Society, 0-7695-1037-X. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
10 | Parag K. Lala, Alvernon Walker |
On-Line Error Detectable Carry-Free Adder Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 24-26 October 2001, San Francisco, CA, USA, Proceedings, pp. 66-71, 2001, IEEE Computer Society, 0-7695-1203-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
carry-free adder, signed binary digits, 1-out-of-3 code, on-line error detection |
10 | Won Namgoong, Teresa H. Meng |
Power consumption of parallel spread spectrum correlator architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998, Monterey, California, USA, August 10-12, 1998, pp. 133-135, 1998, ACM, 1-58113-059-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
10 | K'Andrea C. Bickerstaff, Michael J. Schulte, Earl E. Swartzlander Jr. |
Parallel reduced area multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 9(3), pp. 181-191, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
Displaying result #1 - #30 of 30 (100 per page; Change: )
|
|