Search results for "SimpleScalar"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
97	Naraig Manjikian	More enhancements of the simplescalar tool set.	SIGARCH Comput. Archit. News	2001	DBLP DOI BibTeX RDF
77	Harold W. Cain, Kevin M. Lepak, Mikko H. Lipasti	A dynamic binary translation approach to architectural simulation.	SIGARCH Comput. Archit. News	2001	DBLP DOI BibTeX RDF
64	Gi-Ho Park, Sung Woo Chung, Han-Jong Kim, Jung-Bin Im, Jung-Wook Park, Shin-Dug Kim, Sung-Bae Park	Practice and Experience of an Embedded Processor Core Modeling.	HPCC	2006	DBLP DOI BibTeX RDF
58	Doug Burger, Todd M. Austin, Stephen W. Keckler	Recent extensions to the SimpleScalar tool suite.	SIGMETRICS Perform. Evaluation Rev.	2004	DBLP DOI BibTeX RDF
58	Todd M. Austin, Eric Larson, Dan Ernst	SimpleScalar: An Infrastructure for Computer System Modeling.	Computer	2002	DBLP DOI BibTeX RDF
58	Naraig Manjikian	Multiprocessor enhancements of the SimpleScalar tool set.	SIGARCH Comput. Archit. News	2001	DBLP DOI BibTeX RDF
45	Rongrong Zhong, Yongxin Zhu 0001, Weiwei Chen, Mingliang Lin, Weng-Fai Wong	An Inter-Core Communication Enabled Multi-Core Simulator Based on SimpleScalar.	AINA Workshops (1)	2007	DBLP DOI BibTeX RDF
44	Peng Chen 0012, Krishna M. Kavi, Robert Akl	Performance Enhancement by Eliminating Redundant Function Execution.	Annual Simulation Symposium	2006	DBLP DOI BibTeX RDF	Function reuse, Basic Block Reuse, SimpleScalar, Instruction Level Parallelism, Speculative Execution, Value Prediction, Instruction Reuse
44	Justin Teller, Charles B. Silio Jr., Bruce L. Jacob	Performance characteristics of MAUI: an intelligent memory system architecture.	Memory System Performance	2005	DBLP DOI BibTeX RDF	MAUI memory architecture, SimpleScalar simulator, data-intensive calculations, intelligent memory, memory architecture, vector processing, SIMD processing
32	Kleovoulos Kalaitzidis, Georgios Dimitriou, Georgios I. Stamoulis, Michael F. Dossis	Performance and power simulation of a functional-unit-network processor with simplescalar and wattch.	Panhellenic Conference on Informatics	2015	DBLP DOI BibTeX RDF
32	Zidong Du, Bingbing Xia, Fei Qiao, Huazhong Yang	System-Level Evaluation of Video Processing System Using SimpleScalar-Based Multi-core Processor Simulator.	ISADS	2011	DBLP DOI BibTeX RDF
32	Xiaoguang Ren, Yuhua Tang, Tao Tang, Sen Ye, Huiquan Wang, Jing Zhou	Sim-spm: A SimpleScalar-Based Simulator for Multi-level SPM Memory Hierarchy Architecture.	HPCC	2010	DBLP DOI BibTeX RDF
32	Toshihiro Hanawa, Toshiya Minai, Yasuki Tanabe, Hideharu Amano	Implementation of ISIS-SimpleScalar.	PDPTA	2005	DBLP BibTeX RDF
32	Naoman Abbas, Sumant Tambe, Jonathan E. Cook	Using DDL to Understand and Modify SimpleScalar.	WCRE	2004	DBLP DOI BibTeX RDF
32	Naraig Manjikian	Parallel simulation of multiprocessor execution: implementation and results for simplescalar.	ISPASS	2001	DBLP DOI BibTeX RDF
32	Naraig Manjikian	Enhancements and applications of the SimpleScalar simulator for undergraduate and graduate computer architecture education.	WCAE	2000	DBLP DOI BibTeX RDF
32	Todd M. Austin	The SimpleScalar tool set as an instructional tool: experiences and future directions.	WCAE@HPCA	1998	DBLP DOI BibTeX RDF
32	Doug Burger, Todd M. Austin	The SimpleScalar tool set, version 2.0.	SIGARCH Comput. Archit. News	1997	DBLP DOI BibTeX RDF
31	Chun-Ting Huang	Improving the Multimedia Processing of Relay Nodes in Mesh Wireless Networks.	IIH-MSP	2010	DBLP DOI BibTeX RDF	Relay node, SimpleScalar, Multimedia processing
26	Tarek M. Taha, D. Scott Wills	An Instruction Throughput Model of Superscalar Processors.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Modeling techniques, Pipeline processors, Modeling of computer architecture
26	James Donald, Margaret Martonosi	An Efficient, Practical Parallelization Methodology for Multicore Architecture Simulation.	IEEE Comput. Archit. Lett.	2006	DBLP DOI BibTeX RDF
26	José Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo, Guadalupe Miñana, Sonia López	Sim-async: An Architectural Simulator for Asynchronous Processor Modeling Using Distribution Functions.	Euro-Par	2006	DBLP DOI BibTeX RDF
26	Takashi Nakada, Hiroshi Nakashima	Design and Implementation of a High Speed Microprocessor Simulator BurstScalar.	MASCOTS	2004	DBLP DOI BibTeX RDF
26	André L. Sandri, Ronaldo Augusto Lara Gonçalves, João Angelo Martini	SMS - Tool for Development and Performance Analysis of Parallel Applications.	Annual Simulation Symposium	2004	DBLP DOI BibTeX RDF
26	Jason F. Cantin, Mark D. Hill	Cache performance for selected SPEC CPU2000 benchmarks.	SIGARCH Comput. Archit. News	2001	DBLP DOI BibTeX RDF
13	Jianwei Chen, Murali Annavaram, Michel Dubois 0001	SlackSim: a platform for parallel simulations of CMPs on CMPs.	SIGMETRICS Perform. Evaluation Rev.	2009	DBLP DOI BibTeX RDF
13	Mehrtash Manoochehri, Alireza Ejlali, Seyed Ghassem Miremadi	Fault Tolerant and Low Energy Write-Back Heterogeneous Set Associative Cache for DSM Technologies.	ARES	2009	DBLP DOI BibTeX RDF
13	Mehrtash Manoochehri, Alireza Ejlali, Seyed Ghassem Miremadi	Joint write policy and fault-tolerance mechanism selection for caches in DSM technologies: Energy-reliability trade-off.	ISQED	2009	DBLP DOI BibTeX RDF
13	Chung-Ming Chen, Chung-Ho Chen	Configurable VLSI Architecture for Deblocking Filter in H.264/AVC.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
13	Eriko Nurvitadhi, Jumnit Hong, Shih-Lien Lu	Active Cache Emulator.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
13	Asadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis	Versatility of extended subwords and the matrix register file.	ACM Trans. Archit. Code Optim.	2008	DBLP DOI BibTeX RDF	SIMD programming, SIMD architectures, multimedia standards
13	Francisco J. Jaime, Javier Hormigo, Julio Villalba, Emilio L. Zapata	New SIMD instructions set for image processing applications enhancement.	ICIP	2008	DBLP DOI BibTeX RDF
13	Jaejin Lee, Junghyun Kim, Choonki Jang, Seungkyun Kim, Bernhard Egger 0002, Kwangsub Kim, Sangyong Han	FaCSim: a fast and cycle-accurate architecture simulator for embedded systems.	LCTES	2008	DBLP DOI BibTeX RDF	virtual prototyping, architecture simulator, full-system simulation, simulator parallelization, cycle-accurate simulation
13	Aleksandar Ilic, Frederico Pratas, Leonel Sousa	Distributed Web-based Platform for Computer Architecture Simulation.	ISPDC	2008	DBLP DOI BibTeX RDF
13	Jianjun Xu, Qingping Tan, Rui Shen	A Novel Optimum Data Duplication Approach for Soft Error Detection.	APSEC	2008	DBLP DOI BibTeX RDF
13	Mohammed Abid Hussain, Madhu Mutyam	Block remap with turnoff: A variation-tolerant cache design technique.	ASP-DAC	2008	DBLP DOI BibTeX RDF
13	Nara Yang, Gilsang Yoon, Jeonghwan Lee, Intae Hwang, Cheol Hong Kim, Jong-Myon Kim	Loop Detection for Energy-Aware High Performance Embedded Processors.	APSCC	2008	DBLP DOI BibTeX RDF
13	Hashem Hashemi Najaf-abadi, Eric Rotenberg	Configurational Workload Characterization.	ISPASS	2008	DBLP DOI BibTeX RDF
13	Giancarlo Covolo Heck, Roberto A. Hexsel	The performance of pollution control victim cache for embedded systems.	SBCCI	2008	DBLP DOI BibTeX RDF	pollution control victim cache, embedded systems
13	Frederico Pratas, Georgi Gaydadjiev, Mladen Berekovic, Leonel Sousa, Stefanos Kaxiras	Low power microarchitecture with instruction reuse.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	loop reusing technique, reorder buffer optimization, superscalar processor, power reduction
13	Xuan Guan, Yunsi Fei	Reducing power consumption of embedded processors through register file partitioning and compiler support.	ASAP	2008	DBLP DOI BibTeX RDF
13	Linfeng Pan, Minyi Guo, Yanqin Yang, Meng Wang 0005, Zili Shao	A State-Based Predictive Approach for Leakage Reduction of Functional Units.	EUC (1)	2008	DBLP DOI BibTeX RDF
13	Hongbin Sun 0001, Nanning Zheng 0001, Tong Zhang 0002	Realization of L2 Cache Defect Tolerance Using Multi-bit ECC.	DFT	2008	DBLP DOI BibTeX RDF
13	William Enck, Kevin R. B. Butler, Thomas Richardson, Patrick D. McDaniel, Adam D. Smith	Defending Against Attacks on Main Memory Persistence.	ACSAC	2008	DBLP DOI BibTeX RDF
13	David H. Albonesi	Mixing It Up.	IEEE Micro	2007	DBLP DOI BibTeX RDF	photonic integration, self-reconfigurable hardware, simulation
13	Xian-He Sun, Surendra Byna, Yong Chen 0001	Server-Based Data Push Architecture for Multi-Processor Environments.	J. Comput. Sci. Technol.	2007	DBLP DOI BibTeX RDF	modeling, evaluation, performance measurement, cache memory, simulation of multiple-processor system
13	Partha Biswas, Nikil D. Dutt, Laura Pozzi, Paolo Ienne	Introduction of Architecturally Visible Storage in Instruction Set Extensions.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
13	Paolo Bonzini, Dilek Harmanci, Laura Pozzi	A Study of Energy Saving in Customizable Processors.	SAMOS	2007	DBLP DOI BibTeX RDF
13	Antonio Carlos Schneider Beck, Luigi Carro	Transparent acceleration of data dependent instructions for general purpose processors.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
13	Athanasios Milidonis, Nikolaos Alachiotis 0002, Vasileios Porpodas, Haralambos Michail, Athanasios Kakarountas, Constantinos E. Goutis	Interactive presentation: A decoupled architecture of processors with scratch-pad memory hierarchy.	DATE	2007	DBLP DOI BibTeX RDF
13	Peng Li 0031, Dongsheng Wang 0002, Haixia Wang 0001, Meijuan Lu, Weimin Zheng	LIRAC: Using Live Range Information to Optimize Memory Access.	ARCS	2007	DBLP DOI BibTeX RDF	LIRAC, Live Range, Cache, Memory Hierarchy, Write Buffer
13	Juan Chen 0001, Yong Dong, Huizhan Yi, Xuejun Yang	Power-Aware Software Prefetching.	ICESS	2007	DBLP DOI BibTeX RDF
13	Masahiro Yano, Toru Takasaki, Takashi Nakada, Hiroshi Nakashima	An Accurate and Efficient Time-Division Parallelization of Cycle Accurate Architectural Simulators.	Annual Simulation Symposium	2007	DBLP DOI BibTeX RDF
13	Mohsen Soryani, Mohsen Sharifi, Mohammad Hossein Rezvani	Performance Evaluation of Cache Memory Organizations in Embedded Systems.	ITNG	2007	DBLP DOI BibTeX RDF
13	Konrad Malkowski, Greg M. Link, Padma Raghavan, Mary Jane Irwin	Load Miss Prediction - Exploiting Power Performance Trade-offs.	IPDPS	2007	DBLP DOI BibTeX RDF
13	Liang-Kai Wang, Charles Tsen, Michael J. Schulte, Divya Jhalani	Benchmarks and performance analysis of decimal floating-point applications.	ICCD	2007	DBLP DOI BibTeX RDF
13	Koustav Bhattacharya, Soontae Kim, Nagarajan Ranganathan	Improving the reliability of on-chip L2 cache using redundancy.	ICCD	2007	DBLP DOI BibTeX RDF
13	Swaroop Ghosh, Patrick Ndai, Swarup Bhunia, Kaushik Roy 0001	Tolerance to Small Delay Defects by Adaptive Clock Stretching.	IOLTS	2007	DBLP DOI BibTeX RDF
13	Paolo Bonzini, Laura Pozzi	A Retargetable Framework for Automated Discovery of Custom Instructions.	ASAP	2007	DBLP DOI BibTeX RDF
13	Jude Angelo Ambrose, Roshan G. Ragel, Sri Parameswaran	RIJID: Random Code Injection to Mask Power Analysis based Side Channel Attacks.	DAC	2007	DBLP DOI BibTeX RDF
13	JoAnn M. Paul, Donald E. Thomas, Alex Bobrek	Scenario-oriented design for single-chip heterogeneous multiprocessors.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
13	Asadollah Shahbahrami, Ben H. H. Juurlink, Demid Borodin, Stamatis Vassiliadis	Avoiding Conversion and Rearrangement Overhead in SIMD Architectures.	Int. J. Parallel Program.	2006	DBLP DOI BibTeX RDF	Embedded media processors, multimedia kernels, register file, subword parallelism
13	Zili Shao, Chun Xue, Qingfeng Zhuge, Mei Kang Qiu, Bin Xiao 0001, Edwin Hsing-Mean Sha	Security Protection and Checking for Embedded System Integration against Buffer Overflow Attacks via Hardware/Software.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	hardware/software, Security, embedded system, protection, buffer overflow attack
13	Dmitry V. Ponomarev, Gurhan Kucuk, Kanad Ghose	Dynamic Resizing of Superscalar Datapath Components for Energy Efficiency.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	energy-efficient datapath, Superscalar processor, power reduction, dynamic instruction scheduling
13	Mehrdad Reshadi, Bita Gorjiara, Nikil D. Dutt	Generic Processor Modeling for Automatically Generating Very Fast Cycle-Accurate Simulators.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
13	Michael Penner, Viktor K. Prasanna	Cache-Friendly implementations of transitive closure.	ACM J. Exp. Algorithmics	2006	DBLP DOI BibTeX RDF	Floyd-Warshall algorithm, systolic array algorithms, Data structures
13	Gokhan Memik, William H. Mangione-Smith	Evaluating Network Processors using NetBench.	ACM Trans. Embed. Comput. Syst.	2006	DBLP DOI BibTeX RDF	Embedded systems, benchmarking, network processors
13	Kashif Ali, Mokhtar Aboelaze, Suprakash Datta	Modified Hotspot Cache Architecture: A Low Energy Fast Cache for Embedded Processors.	ICSAMOS	2006	DBLP DOI BibTeX RDF
13	Zenaide Carvalho da Silva, João Angelo Martini, Ronaldo Augusto Lara Gonçalves	Extending the PPM Branch Predictor.	PDP	2006	DBLP DOI BibTeX RDF
13	Antonio Carlos Schneider Beck, Victor F. Gomes, Luigi Carro	Automatic Dataflow Execution with Reconfiguration and Dynamic Instruction Merging.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
13	Jumnit Hong, Eriko Nurvitadhi, Shih-Lien Lu	Design, implementation, and verification of active cache emulator (ACE).	FPGA	2006	DBLP DOI BibTeX RDF	FPGA-based emulator, real-time emulation, cache modeling
13	Hossein Asadi 0001, Vilas Sridharan, Mehdi Baradaran Tahoori, David R. Kaeli	Vulnerability analysis of L2 cache elements to single event upsets.	DATE	2006	DBLP DOI BibTeX RDF
13	Partha Biswas, Nikil D. Dutt, Paolo Ienne, Laura Pozzi	Automatic identification of application-specific functional units with architecturally visible storage.	DATE	2006	DBLP DOI BibTeX RDF
13	José Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo, Guadalupe Miñana, Sonia López	Comparing the Performance of a 64-bit Fully-Asynchronous Superscalar Processor versus its Synchronous Counterpart.	DSD	2006	DBLP DOI BibTeX RDF
13	Ali R. Iranpour, Krzysztof Kuchcinski	Performance Improvement for H.264 Video Encoding using ILP Embedded Processor.	DSD	2006	DBLP DOI BibTeX RDF
13	Takashi Nakada, Tomoaki Tsumura, Hiroshi Nakashima	Design and Implementation of aWorkload Specific Simulator.	Annual Simulation Symposium	2006	DBLP DOI BibTeX RDF
13	Konrad Malkowski, Ingyu Lee, Padma Raghavan, Mary Jane Irwin	On improving performance and energy profiles of sparse scientific applications.	IPDPS	2006	DBLP DOI BibTeX RDF
13	Konrad Malkowski, Ingyu Lee, Padma Raghavan, Mary Jane Irwin	Conjugate gradient sparse solvers: performance-power characteristics.	IPDPS	2006	DBLP DOI BibTeX RDF
13	Wonbok Lee, Kimish Patel, Massoud Pedram	B2Sim: : a fast micro-architecture simulator based on basic block characterization.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	basic block, micro-architecture simulation, program behavior
13	Antonio Carlos Schneider Beck, Victor F. Gomes, Luigi Carro	Dynamic Instruction Merging and a Reconfigurable Array: Dataflow Execution with Software Compatibility.	ARC	2006	DBLP DOI BibTeX RDF
13	Peng Li 0031, Dongsheng Wang 0002, Songliu Guo, Tao Tian, Weimin Zheng	Live Range Aware Cache Architecture.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF	Live Range, Cache, Memory Hierarchy
13	Paolo Bonzini, Laura Pozzi	Code transformation strategies for extensible embedded processors.	CASES	2006	DBLP DOI BibTeX RDF	compilers, ASIPs, instruction-set extensions, customizable processors
13	Hiroshi Nakashima, Masahiro Konishi, Takashi Nakada	An accurate and efficient simulation-based analysis for worst case interruption delay.	CASES	2006	DBLP DOI BibTeX RDF	worst case interruption delay, cycle accurate simulation
13	Asadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis	Accelerating Color Space Conversion Using Extended Subwords and the Matrix Register File.	ISM	2006	DBLP DOI BibTeX RDF	Color space conversion, SIMD architectures, multimedia extensions
13	Konrad Malkowski, Padma Raghavan, Mary Jane Irwin	Poster reception - Toward a power efficient computer architecture for Barnes-Hut N-body simulations.	SC	2006	DBLP DOI BibTeX RDF
13	Jingfei Kong, Cliff Changchun Zou, Huiyang Zhou	Improving software security via runtime instruction-level taint checking.	ASID	2006	DBLP DOI BibTeX RDF	format string, hardware tagging, buffer overflow
13	Ying Chen, Karthik Ranganathan, Vasudev V. Pai, David J. Lilja, Kia Bazargan	A Novel Memory Structure for Embedded Systems: Flexible Sequential and Random Access Memory.	J. Comput. Sci. Technol.	2005	DBLP DOI BibTeX RDF	sequential access buffer, media benchmark, flexible sequential and random access memory, on-chip memory
13	Joshua J. Yi, David J. Lilja, Douglas M. Hawkins	Improving Computer Architecture Simulation Methodology by Adding Statistical Rigor.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	simulation output analysis, measurement techniques, Performance analysis and design aids
13	Shuo Chen 0001, Jun Xu 0003, Nithin Nakka, Zbigniew Kalbarczyk, Ravishankar K. Iyer	Defeating Memory Corruption Attacks via Pointer Taintedness Detection.	DSN	2005	DBLP DOI BibTeX RDF
13	Cheol Hong Kim, Sung-Hoon Shim, Jong Wook Kwak, Sung Woo Chung, Chu Shik Jhon	First-Level Instruction Cache Design for Reducing Dynamic Energy Consumption.	SAMOS	2005	DBLP DOI BibTeX RDF
13	Meuse N. Oliveira Jr., Paulo Romero Martins Maciel, Ricardo Massa Ferreira Lima, Angelo Ribeiro, César A. L. de Oliveira, Adilson Arcoverde, Raimundo S. Barreto, Eduardo Tavares, Leonardo Amorim	A Retargetable Environment for Power-Aware Code Evaluation: An Approach Based on Coloured Petri Net.	PATMOS	2005	DBLP DOI BibTeX RDF
13	Mehrdad Reshadi, Nikil D. Dutt	Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation.	DATE	2005	DBLP DOI BibTeX RDF
13	Divya Arora, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring.	DATE	2005	DBLP DOI BibTeX RDF
13	Mehrdad Reshadi, Prabhat Mishra 0001	Memory access optimizations in instruction-set simulators.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	memory address-space mapping, instruction-set simulator
13	Divya Arora, Anand Raghunathan, Srivaths Ravi 0001, Niraj K. Jha	Enhancing security through hardware-assisted run-time validation of program data properties.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	data tagging, secure architectures, run-time checks
13	Trevor N. Mudge	Performance and power analysis of computer systems.	CODES+ISSS	2005	DBLP DOI BibTeX RDF
13	Zhiqiang Ma, Zhenzhou Ji, Mingzeng Hu, Yi Ji	Energy Efficient United L2 Cache Design with Instruction/Data Filter Scheme.	APPT	2005	DBLP DOI BibTeX RDF
13	Cheol Kim, Sung Chung, Chu Shik Jhon	An Innovative Instruction Cache for Embedded Processors.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
13	Jorgen Peddersen, Seng Lin Shee, Andhi Janapsatya, Sri Parameswaran	Rapid Embedded Hardware/Software System Generation.	VLSI Design	2005	DBLP DOI BibTeX RDF
13	Qing Zhao, David J. Lilja	Static Classification of Value Predictability Using Compiler Hints.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF