Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
89 | Seung-Min Lee, Stefan Lachowicz, David Lucas, A. M. Rassau, Kamran Eshraghian, Mike Myung-Ok Lee, Kamal E. Alameh |
A Novel Design of Beam Steering n-phase OPTO-ULSI Processor for IIPS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 2nd IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2004), 28-30 January 2004, Perth, Australia, pp. 395-402, 2004, IEEE Computer Society, 0-7695-2081-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
73 | M. K. Kidambi, Akhilesh Tyagi, Mohammed R. Madani, Magdy A. Bayoumi |
Three-dimensional defect sensitivity modeling for open circuits in ULSI structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(4), pp. 366-371, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
67 | Stephan P. Athan, David L. Landis, Sami A. Al-Arian |
A novel built-in current sensor for IDDQ testing of deep submicron CMOS ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 118-123, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
deep submicron CMOS ICs, fault diagnosability, ULSI CMOS, fault diagnosis, integrated circuit testing, fault detectability, CMOS integrated circuits, leakage currents, built-in current sensor, I/sub DDQ/ testing, electric current measurement, ULSI, electric sensing devices |
67 | Imtiaz P. Shaik, Michael L. Bushnell |
A graph approach to DFT hardware placement for robust delay fault BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 177-182, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
graph heuristic, DFT hardware placement, robust delay fault BIST, ULSI circuit, built-in self-testing model, design for testability hardware, hazard free structure, graph theory, logic testing, delays, built-in self test, integrated circuit testing, design for testability, fault location, digital integrated circuits, ULSI |
67 | Payam Heydari, Massoud Pedram |
Interconnect Energy Dissipation in High-Speed ULSI Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 132-, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Ultra-large integrated (ULSI) circuits, Energy dissipation CMOS circuits, RLC circuits, Interconnect, Transmission lines |
64 | Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand |
Interpretation of rent's rule for ultralarge-scale integrated circuit designs, with an application to wirelength distribution models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 12(12), pp. 1330-1347, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
57 | Seung-Min Lee, David Lucas, Mike Myung-Ok Lee, Kamran Eshraghian, Dae-Ik Kim, Kamal E. Alameh |
High Density and Low Power Beam Steering Opto-ULSI Processor for IIPS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HSNMC ![In: High Speed Networks and Multimedia Communications, 7th IEEE International Conference, HSNMC 2004, Toulouse, France, June 30 - July 2, 2004, Proceedings, pp. 894-902, 2004, Springer, 3-540-22262-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
57 | Yi-Kan Cheng, Sung-Mo Kang |
Temperature-driven power and timing analysis for CMOS ULSI circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 214-217, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
51 | Eiji Harada, Janak H. Patel |
Overhead reduction techniques for hierarchical fault simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 79-85, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
overhead reduction techniques, hierarchical fault simulation, simulation overhead, concurrent method, multi-list-traversal method, one-pass fault simulation strategy, characteristic vectors, contiguous concurrent machines, ISCAS benchmark circuits, fault ordering, logic test sequences, fault diagnosis, logic testing, combinational circuits, logic CAD, digital simulation, circuit analysis computing, concurrent engineering, multivalued logic circuits, ULSI, ULSI |
48 | Mary Y. L. Wisniewski, Emmanuel Yashchin, Robert L. Franch, David P. Conrady, Daniel N. Maynard, Giovanni Fiorenza, I. Cevdet Noyan |
The physical design of on-chip interconnections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(3), pp. 254-276, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
42 | Bogdan M. Maziarz, Vijay K. Jain |
Automatic Reconfiguration and Yield of the TESH Multicomputer Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 51(8), pp. 963-972, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
TESH, fault-tolerance, routing, VLSI, Interconnection networks, reconfiguration, redundancy, yield, hierarchical networks, manufacturing defects, parallel computing systems, ULSI |
41 | Ron Ho |
High-performance ULSI: the real limiter to interconnect scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings, pp. 3, 2005, ACM, 1-59593-033-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
VLSI, wireless, 3D, scaling, proximity, repeaters, wires |
41 | Yin Wang, Xianlong Hong, Tong Jing, Yang Yang 0040, Xiaodong Hu 0001, Guiying Yan |
An Efficient Low-Degree RMST Algorithm for VLSI/ULSI Physical Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, pp. 442-452, 2004, Springer, 3-540-23095-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
41 | Pasi Liljeberg, Juha Plosila, Jouni Isoaho |
Asynchronous interface for locally clocked modules in ULSI systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 170-173, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
41 | Yi-Kan Cheng, Sung-Mo Kang |
A temperature-aware simulation environment for reliable ULSI chipdesign. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(10), pp. 1211-1220, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
41 | Yi-Kan Cheng, Sung-Mo Kang |
An efficient method for hot-spot identification in ULSI circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 124-127, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
41 | Daniel Audet, Yvon Savaria, N. Arel |
Pipelining communications in large VLSI/ULSI systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 2(1), pp. 1-10, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
41 | Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsuhiro Suma, Kazuyasu Fujishima |
Highly Reliable Testing of ULSI Memories with On-Chip Voltage-Down Converters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 10(2), pp. 6-12, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
41 | Sanae Fukuda, Naoyuki Shigyo, Koichi Kato, Shin Nakamura |
A ULSI 2-D capacitance simulator for complex structures based on actual processes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(1), pp. 39-47, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
41 | Armen H. Zemanian, Reginald P. Tewarson, Chi Ping Ju, Juif Frank Jen |
Three-dimensional capacitance computations for VLSI/ULSI interconnections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(12), pp. 1319-1326, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
32 | Baohua Wang, Pinaki Mazumder |
Accelerated Chip-Level Thermal Analysis Using Multilayer Green's Function. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(2), pp. 325-344, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
32 | Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand |
Assessment of on-chip wire-length distribution models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 12(10), pp. 1108-1112, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
32 | Yves Quéré, Thierry LeGouguec, Pierre-Marie Martin, Fabrice Huret |
Interconnect Mode Conversion in High-Speed VLSI Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 5th International Symposium on Quality of Electronic Design (ISQED 2004), 22-24 March 2004, San Jose, CA, USA, pp. 265-270, 2004, IEEE Computer Society, 0-7695-2093-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
32 | Kevin T. Tang, Eby G. Friedman |
Simultaneous switching noise in on-chip CMOS power distribution networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 10(4), pp. 487-493, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
32 | Bogdan M. Maziarz, Vijay K. Jain |
Yield Estimates for the TESH Multicomputer Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 6-8 November 2002, Vancouver, BC, Canada, Proceedings, pp. 20-30, 2002, IEEE Computer Society, 0-7695-1831-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
32 | Hannu Tenhunen, Elena Dubrova |
SoC Masters: An International M.Sc. Program in System-on-Chip Design at KTH. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: 2001 International Conference on Microelectronics Systems Education, MSE 2001, Las Vegas, NV, USA, July 17-18, 2001, pp. 64-66, 2001, IEEE Computer Society, 0-7695-1156-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
32 | R. P. Suresh, P. Venugopal, S. Tamizh Selvam, S. Potla |
Combined Effect of Grain Boundary Depletion and PolySi/Oxide Interface Depletion on Drain Characteristics of a p-MOSFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 156-161, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
26 | Tobias Bjerregaard, Shankar Mahadevan |
A survey of research and practices of Network-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Comput. Surv. ![In: ACM Comput. Surv. 38(1), pp. 1, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Chip-area networks, GSI design, OCP, ULSI design, communication-centric design, SoC, system-on-chip, network-on-chip, interconnects, NoC, GALS, sockets, on-chip communication, communication abstractions |
25 | George Mekhael, Nathaniel Morgan, Mounica Patnala, Trond Ytterdal, Maher E. Rizkalla |
GNRFET-Based DC-DC Converters for Low Power Data Management in ULSI System, a Feasibility Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2021, Daegu, South Korea, May 22-28, 2021, pp. 1-5, 2021, IEEE, 978-1-7281-9201-7. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
25 | Ajay Kumar 0004, Neha Gupta 0003, Samarth Singh, Balark Tiwari, Madan Mohan Tripathi, Rishu Chaujar |
Carbon Nanotube Recessed Channel (CNT-RC) MOSFET for High Linearity/ULSI Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TENCON ![In: TENCON 2019 - 2019 IEEE Region 10 Conference (TENCON), Kochi, India, October 17-20, 2019, pp. 2564-2567, 2019, IEEE, 978-1-7281-1895-6. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
25 | Michihiro Sato, Yosuke Takahashi |
Simulation of Dislocation Accumulation in Impurity Doped-ULSI Cells and Electric Characteristic Evaluations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Autom. Technol. ![In: Int. J. Autom. Technol. 10(2), pp. 195-200, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
25 | Pascal Nsame, Guy Bois, Yvon Savaria |
A data-driven energy efficient and flexible compute fabric architecture: For adaptive computing applied to ULSI of FFT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 21st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2014, Marseille, France, December 7-10, 2014, pp. 750-753, 2014, IEEE, 978-1-4799-4242-8. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
25 | Chun-Min Zhang, Qing-Qing Sun, Peng-Fei Wang, David Wei Zhang |
PEALD Ru/RuOx films for ULSI applications and its transition control between metal and metal oxide. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: IEEE 10th International Conference on ASIC, ASICON 2013, Shenzhen, China, October 28-31, 2013, pp. 1-4, 2013, IEEE, 978-1-4673-6415-7. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
25 | Cher Ming Tan, Wei Li, Zhenghao Gan |
Applications of finite element methods for reliability study of ULSI interconnections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 52(8), pp. 1539-1545, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
25 | Carles Hernández 0001, Federico Silla, José Duato |
Addressing Link Degradation in NoC-Based ULSI Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par Workshops ![In: Euro-Par 2012: Parallel Processing Workshops - BDMC, CGWS, HeteroPar, HiBB, OMHI, Paraphrase, PROPER, Resilience, UCHPC, VHPC, Rhodes Islands, Greece, August 27-31, 2012. Revised Selected Papers, pp. 327-336, 2012, Springer, 978-3-642-36948-3. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
25 | Cher Ming Tan |
Electromigration in ULSI Interconnections ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2010 |
DOI RDF |
|
25 | Tong Boon Tang, Alan F. Murray, Binjie Cheng, Asen Asenov |
Statistical NBTI-effect prediction for ULSI circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France, pp. 2494-2497, 2010, IEEE, 978-1-4244-5308-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
25 | Byung-Gook Park, Jae Young Song, Jong Pil Kim, Hoon Jeong, Jung Hoon Lee, Seongjae Cho |
Nanosculpture: Three-dimensional CMOS device structures for the ULSI era. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 40(4-5), pp. 769-772, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
25 | Md. Sajjad Rahaman, Masud H. Chowdhury |
Multi-Carrier CDMA-Interconnect for Inter- and Intra-ULSI Communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 14th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2007, Marrakech, Morocco, December 11-14, 2007, pp. 1059-1062, 2007, IEEE, 978-1-4244-1377-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Xia Xiao, Xueyi You, Suying Yao |
Theoretical study of mechanical properties of multi-layer ULSI interconnect dielectrics by surface acoustic wave method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 37(10), pp. 1052-1055, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Jae Eun Jang, Seung Nam Cha, Youngjin Choi, Dae Joon Kang, Tim P. Butler, David G. Hasko, Jong Min Kim, Gehan A. J. Amaratunga |
CNT based mechanical devices for ULSI memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006, DoubleTree Hotel, San Jose, California, USA, September 10-13, 2006, pp. 461-464, 2006, IEEE, 1-4244-0075-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Amir H. Ajami, Kaustav Banerjee, Massoud Pedram |
Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(6), pp. 849-861, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
25 | M. Frank Chang |
CDMA/FDMA-interconnects for future ULSI communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2005 International Conference on Computer-Aided Design, ICCAD 2005, San Jose, CA, USA, November 6-10, 2005, pp. 975-978, 2005, IEEE Computer Society, 0-7803-9254-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
25 | Payam Heydari, Soroush Abbaspour, Massoud Pedram |
Interconnect energy dissipation in high-speed ULSI circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(8), pp. 1501-1514, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
25 | Hidenari Nakashima, Junpei Inoue, Kenichi Okada, Kazuya Masu |
ULSI Interconnect Length Distribution Model Considering Core Utilization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 1210-1217, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
25 | Michael W. Ruprecht, Guenther Benstetter, Douglas B. Hunt |
A review of ULSI failure analysis techniques for DRAMs. Part II: Defect isolation and visualization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 43(1), pp. 17-41, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
25 | Ulrich Rückert 0001 |
ULSI Architectures for Artificial Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 22(3), pp. 10-19, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
25 | Guenther Benstetter, Michael W. Ruprecht, Douglas B. Hunt |
A review of ULSI failure analysis techniques for DRAMs 1. Defect localization and verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 42(3), pp. 307-316, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
25 | Shuzhou Fang, Zeyi Wang, Xianlong Hong |
A 3-D Minimum-Order Boundary Integral Equation Technique to Extract Frequency-Dependant Inductance and Resistance in ULSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 305-310, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
25 | Yutao Ma, Zhijian Li, Litian Liu |
New strategy of modeling inversion layer characteristics in MOS structure for ULSI applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Ser. F Inf. Sci. ![In: Sci. China Ser. F Inf. Sci. 44(3), pp. 176-183, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
25 | Ulrich Rückert 0001 |
ULSI Architectures for Artificial Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: Ninth Euromicro Workshop on Parallel and Distributed Processing, PDP 2001, 7-9 February 2001, Mantova, Italy, pp. 436-442, 2001, IEEE Computer Society, 0-7695-0987-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
25 | TingYen Chiang, Kaustav Banerjee, Krishna Saraswat |
Compact Modeling and SPICE-Based Simulation for Electrothermal Analysis of Multilevel ULSI Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2001, San Jose, CA, USA, November 4-8, 2001, pp. 165-, 2001, IEEE Computer Society, 0-7803-7249-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
25 | Kaustav Banerjee, Amit Mehrotra |
Coupled Analysis of Electromigration Reliability and Performance in ULSI Signal Nets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2001, San Jose, CA, USA, November 4-8, 2001, pp. 158-164, 2001, IEEE Computer Society, 0-7803-7249-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
25 | Martin Bächtold, Mirko Spasojevic, Christian Lage, Per B. Ljung |
A system for full-chip and critical net parasitic extraction for ULSI interconnects using a fast 3-D field solver. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(3), pp. 325-338, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
25 | Andreas Hieke |
A Monte Carlo / FEM investigation on optimal cross-section of high speed ULSI interconnects with respect to RC-delay. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CATA ![In: Proceedings of the ISCA 15th International Conference Computers and Their Applications, March 29-31, 2000, New Orleans, Louisiana, USA, pp. 223-227, 2000, ISCA, 1-880843-32-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP BibTeX RDF |
|
25 | Dinesh Pamunuwa, Li-Rong Zheng 0001, Hannu Tenhunen |
Combating digital noise in high speed ULSI circuits using binary BCH encoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2000, Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31 May 2000, Proceedings, pp. 13-16, 2000, IEEE. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
25 | Kathirgamar Aingaran, Fabian Klass, Chin-Man Kim, Chaim Amir, Joydeep Mitra, Eileen You, Jamil Mohd, Sai-keung Dong |
Coupling Noise Analysis for VLIS and ULSI Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 485-490, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Crosstalk Analysis, Crosstalk Modeling, Noise |
25 | Michael Armacost, Peter D. Hoh, Richard Wise, Wendy Yan, Jeffrey J. Brown, John H. Keller, George A. Kaplita, Scott D. Halle, K. Paul Muller, Munir D. Naeem, Senthil Srinivasan, Hung Y. Ng, Martin Gutsche, Alois Gutmann, Bruno Spuler |
Plasma-etching processes for ULSI semiconductor circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IBM J. Res. Dev. ![In: IBM J. Res. Dev. 43(1), pp. 39-72, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
25 | Donna R. Cote, Son Van Nguyen, Anthony K. Stamper, Douglas S. Armbrust, Dirk Tobben, Richard A. Conti, Gill Yong Lee |
Plasma-assisted chemical vapor deposition of dielectric thin films for ULSI semiconductor circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IBM J. Res. Dev. ![In: IBM J. Res. Dev. 43(1), pp. 5-38, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
25 | D. Stroobannt |
PIN count prediction in ratio cut partitioning for VLSI and ULSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 262-265, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
25 | Eliane França |
Projeto de um circuito integrado dedicado a simulação de circuitos ULSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1999 |
RDF |
|
25 | Hoan H. Pham, Arokia Nathan |
A new formulation for accurate numerical extraction of interconnect capacitance in ULSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 5th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1998, Surfing the Waves of Science and Technology, Lisbon, Portugal, September 7-10, 1998, pp. 99-102, 1998, IEEE, 0-7803-5008-1. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
25 | Tomofumi lima, Masayuki Mizuno, Tadahiko Horiuchi, Masakazu Yamashina |
Capacitance coupling immune, transient sensitive accelerator for resistive interconnect signals of subquarter micron ULSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 31(4), pp. 531-536, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
25 | Tadato Yamagata, Hirotoshi Sato, Kore-aki Fujita, Yasumasa Nishimura, Kenji Anami |
A distributed globally replaceable redundancy scheme for sub-half-micron ULSI memories and beyond. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 31(2), pp. 195-201, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
25 | Hiroyuki Yamauchi, Hironori Akamatsu, Tsutomu Fujita |
An asymptotically zero power charge-recycling bus architecture for battery-operated ultrahigh data rate ULSI's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 30(4), pp. 423-431, April 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
25 | Daisaburo Takashima, Shigeyoshi Watanabe, Hiroalu Nakano, Yukihito Oowaki, Kazunori Ohuchi, Hiroyuki Tango |
Standby/active mode logic for sub-1-V operating ULSI memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 29(4), pp. 441-447, April 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
25 | R. Kent Smith, William M. Coughran Jr. |
Computational Challenges in Simulations of ULSI Semiconductor Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (1) ![In: 27th Annual Hawaii International Conference on System Sciences (HICSS-27), January 4-7, 1994, Maui, Hawaii, USA, pp. 7-15, 1994, IEEE Computer Society, 0-8186-5090-7. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP BibTeX RDF |
|
25 | S. K. Lahiri 0001, M. K. Das, A. Das Gupta, I. Manna |
3D Effects in VLSI/ULSI MOSFETs: A Novel Analytical Approach to Model Threshold Voltage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Seventh International Conference on VLSI Design, VLSI Design 1994, Calcutta, India, January 5-8, 1994, pp. 328-332, 1994, IEEE Computer Society, 0-8186-4990-9. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
25 | Yoshiharu Ichikawa, Jun-ichiro Toriwaki |
A Digital ULSI Inspection Method Using Parallel Scanning Confocal Microscope. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVA ![In: Proceedings of IAPR Workshop on Machine Vision Applications, MVA 1994, December 13-15, 1994, Kawasaki, Japan, pp. 568-570, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP BibTeX RDF |
|
25 | Tadahiro Ohmi |
ULSI reliability through ultraclean processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Proc. IEEE ![In: Proc. IEEE 81(5), pp. 716-729, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
25 | Mohamed Nekili, Yvon Savaria |
Parallel Regeneration of Interconnections in VLSI & ULSI Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 1993 IEEE International Symposium on Circuits and Systems, ISCAS 1993, Chicago, Illinois, USA, May 3-6, 1993, pp. 2023-2026, 1993, IEEE, 0-7803-1281-3. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
25 | Soo-Young Oh, Keh-Jeng Chang, Norman Chang, Ken Lee |
Interconnect Modeling and Design in High-Speed VLSI/ULSI Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD '92, Cambridge, MA, USA, October 11-14, 1992, pp. 184-189, 1992, IEEE Computer Society, 0-8186-3110-4. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
25 | Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsunori Suma, Kazuyasu Fujishima |
A Testing Technique for ULSI Memory with On-Chip Voltage Down Converter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1992, Discover the New World of Test and Design, Baltimore, Maryland, USA, September 20-24, 1992, pp. 615-622, 1992, IEEE Computer Society, 0-7803-0760-7. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
25 | Nobuhiro Tomabechi |
A defect recovery method for ulsi/ wsi arithmetic operation systems based on residue number systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Syst. Comput. Jpn. ![In: Syst. Comput. Jpn. 22(5), pp. 13-20, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
25 | Moshe Shahaf |
DesignFab: A Methodology for ULSI Microprocessor Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD '91, Cambridge, MA, USA, October 14-16, 1991, pp. 136-139, 1991, IEEE Computer Society, 0-8186-2270-9. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
25 | Gopi Ganapathy, Jacob A. Abraham |
Hardware Acceleration Alone Will Not Make Fault Grading ULSI a Reality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1991, Test: Faster, Better, Sooner, Nashville, TN, USA, October 26-30, 1991, pp. 848-857, 1991, IEEE Computer Society, 0-8186-9156-5. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
25 | A. Reisman |
Ionizing radiation effects on ULSI device yield and reliability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 4(3), pp. 301-310, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
25 | Sandro Solmi, Renato Angelucci, Marco Merli |
Shallow junctions for ULSI technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Eur. Trans. Telecommun. ![In: Eur. Trans. Telecommun. 1(2), pp. 159-165, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
25 | Arnaldo Hilário Viegas de Lima, Raul César B. Martins, Ronaldo Stern, Luiza Maria F. Carneiro |
GARDEN - An Integrated and Evolving Environment for ULSI/VLSI CAD Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IBM Syst. J. ![In: IBM Syst. J. 28(4), pp. 580-599, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
25 | F. Gourdy, Alain Greiner, M. Guillemet, Roland Marbot, J. Murzin |
NOISY: an electrical noise checker for ULSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 1988 IEEE International Conference on Computer-Aided Design, ICCAD 1988, Santa Clara, CA, USA, November 7-10, 1988. Digest of Technical Papers, pp. 226-229, 1988, IEEE Computer Society, 0-8186-0869-2. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
16 | Md. Sajjad Rahaman, Masud H. Chowdhury |
BER performance comparison between CDMA and UWB for RF/wireless interconnect application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EIT ![In: 2008 IEEE International Conference on Electro/Information Technology, EIT 2008, held at Iowa State University, Ames, Iowa, USA, May 18-20, 2008, pp. 494-497, 2008, IEEE, 978-1-4244-2030-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | João M. S. Silva, Joel R. Phillips, Luís Miguel Silveira |
Efficient Representation and Analysis of Power Grids. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 420-425, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Saurabh Jain, W. Robert Daasch, David Armbrust |
Analyzing the Impact of Fault Tolerant BIST for VLSI Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA, pp. 152-160, 2008, IEEE Computer Society, 978-0-7695-3365-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Ray T. Chen |
Optical interconnects: a viable solution for interconnection beyond 10 gbit/sec. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2007 International Symposium on Physical Design, ISPD 2007, Austin, Texas, USA, March 18-21, 2007, pp. 85-86, 2007, ACM, 978-1-59593-613-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
PCB interconnects, optical bus architecture, optical interconnects |
16 | Yiyu Shi 0001, Lei He 0001 |
Empire: an efficient and compact multiple-parameterized model order reduction method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2007 International Symposium on Physical Design, ISPD 2007, Austin, Texas, USA, March 18-21, 2007, pp. 51-58, 2007, ACM, 978-1-59593-613-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
reduction, sensitivity, parameter |
16 | Deepak C. Sekar, Azad Naeemi, Reza Sarvari, Jeffrey A. Davis, James D. Meindl |
IntSim: A CAD tool for optimization of multilevel interconnect networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 560-567, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand |
Impact of interconnect length changes on effective materials properties (dielectric constant). ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings, pp. 73-80, 2007, ACM, 978-1-59593-622-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
performance, routing, interconnect, cycle time, interconnect model, rent, path delay |
16 | Zhe Feng 0002, Yu Hu 0002, Tong Jing, Xianlong Hong, Xiaodong Hu 0001, Guiying Yan |
An O(nlogn) algorithm for obstacle-avoiding routing tree construction in the lambda-geometry plane. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2006 International Symposium on Physical Design, ISPD 2006, San Jose, California, USA, April 9-12, 2006, pp. 48-55, 2006, ACM, 1-59593-299-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
?-geometry, O(nlogn), Steiner tree construction, obstacle-avoiding |
16 | Qi Zhu 0002, Hai Zhou 0001, Tong Jing, Xianlong Hong, Yang Yang 0040 |
Spanning graph-based nonrectilinear steiner tree algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(7), pp. 1066-1075, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Yu Hu 0002, Tong Jing, Xianlong Hong, Zhe Feng 0002, Xiaodong Hu 0001, Guiying Yan |
An-OARSMan: obstacle-avoiding routing tree construction with good length performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 7-12, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Yin Wang, Xianlong Hong, Tong Jing, Yang Yang 0040, Xiaodong Hu 0001, Guiying Yan |
The polygonal contraction heuristic for rectilinear Steiner tree construction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 1-6, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Yaw-Jen Chang |
Fault Detection for Plasma Etching Processes Using RBF Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISNN (3) ![In: Advances in Neural Networks - ISNN 2005, Second International Symposium on Neural Networks, Chongqing, China, May 30 - June 1, 2005, Proceedings, Part III, pp. 538-543, 2005, Springer, 3-540-25914-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand |
Predicting interconnect requirements in ultra-large-scale integrated control logic circuitry. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings, pp. 43-50, 2005, ACM, 1-59593-033-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
wire-length distribution model, routing, interconnect, rent |
16 | Gerald G. Lopez, Giovanni Fiorenza, Thomas J. Bucelot, Phillip J. Restle, Mary Yvonne Lanzerotti |
Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 38-43, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
load capacitance, routing, application specific integrated circuit (ASIC), clock, power dissipation |
16 | Joohyung Lee 0004, Yogesh B. Gianchandani |
A scanning thermal microscopy system with a temperature dithering, servo-controlled interface circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 812-815, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Vijay K. Jain, Glenn H. Chapman |
Level-Hybrid Optoelectronic TESH Interconnection Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 3-5 November 2003, Boston, MA, USA, Proceedings, pp. 45-52, 2003, IEEE Computer Society, 0-7695-2042-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Abhisek Dixit, V. Ramgopal Rao |
A Novel Dynamic Threshold Operation Using Electrically Induced Junction MOSFET in the Deep Sub-micrometer CMOS Regime. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 16th International Conference on VLSI Design (VLSI Design 2003), 4-8 January 2003, New Delhi, India, pp. 499-503, 2003, IEEE Computer Society, 0-7695-1868-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Adrian M. Ionescu, Michel J. Declercq, Santanu Mahapatra, Kaustav Banerjee, Jacques Gautier |
Few electron devices: towards hybrid CMOS-SET integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 88-93, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Iinverter, hybrid CMOS-SET Circuits, single-Electron transistors, ultimate CMOS, low power, quantizer, nanoelectronics |
16 | Gerard A. Allan |
Yield prediction by sampling IC layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(3), pp. 359-371, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Yi-Kan Cheng, David Bearden, Kanti Suryadevara |
Application-Based, Transistor-Level Full-Chip Power Analysis for 700 MHz PowerPCTM Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000, pp. 215-220, 2000, IEEE Computer Society, 0-7695-0801-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|