Search results for "VBSME"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
81	Stephen Warrington, Wai-Yip Chan, Subramania Sudharsanan	Scalable high-throughput architecture for H.264/AVC variable block size motion estimation.	ISCAS	2006	DBLP DOI BibTeX RDF
77	Seung-Man Pyen, Kyeong-Yuk Min, Jong-Wha Chong	An Efficient VLSI Architecture for Full-Search Variable Block Size Motion Estimation in H.264/AVC.	MMM (2)	2007	DBLP DOI BibTeX RDF	VBSME, VLSI, motion estimation, H.264/AVC, block matching algorithm
73	Cao Wei, Mao Zhi Gang	A novel VLSI architecture for VBSME in MPEG-4 AVC/H.264.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
61	Jarno Vanne, Eero Aho, Timo D. Hämäläinen, Kimmo Kuusilinna	A Parallel Memory System for Variable Block-Size Motion Estimation Algorithms.	IEEE Trans. Circuits Syst. Video Technol.	2008	DBLP DOI BibTeX RDF
61	Yang Song 0002, Zhenyu Liu 0001, Takeshi Ikenaga, Satoshi Goto	Ultra Low-Complexity Fast Variable Block Size Motion Estimation Algorithm in H.264/AVC.	ICME	2007	DBLP DOI BibTeX RDF
53	Asral Bahari, Tughrul Arslan, Ahmet T. Erdogan	Low Power Hardware Architecture for VBSME Using Pixel Truncation.	VLSI Design	2008	DBLP DOI BibTeX RDF
53	Mohammed Sayed, Ihab Amer, Wael M. Badawy	Towards an H.264/AVC full encoder on chip: an efficient real-time VBSME ASIC chip.	ISCAS	2006	DBLP DOI BibTeX RDF
40	Wonchul Lee, Hyojin Choi, Wonyong Sung	Algorithm and Software Optimization of Variable Block Size Motion Estimation for H.264/AVC on a VLIW-SIMD DSP.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	variable block size motion estimation, H.264/AVC encoder, VLIW (very long instruction word), SIMD (single instruction multiple data)
40	Stephen Warrington, Subramania Sudharsanan, Wai-Yip Chan	Architecture for Multiple Reference Frame Variable Block Size Motion Estimation.	ISCAS	2007	DBLP DOI BibTeX RDF
40	Seung-Man Pyen, Kyeong-Yuk Min, Jong-Wha Chong, Satoshi Goto	An Efficient Hardware Architecture for Full-Search Variable Block Size Motion Estimation in H.264/AVC.	ISVC (2)	2006	DBLP DOI BibTeX RDF
40	Chuan-Yu Cho, Shiang-Yang Huang, Jeng-Neng Hwang, Jia-Shung Wang	An embedded merging scheme for VLSI implementation of H.264/AVC motion estimation modules.	ICIP (3)	2005	DBLP DOI BibTeX RDF
40	Minho Kim, Ingu Hwang, Soo-Ik Chae	A fast VLSI architecture for full-search variable block size motion estimation in MPEG-4 AVC/H.264.	ASP-DAC	2005	DBLP DOI BibTeX RDF
40	Su-Jin Lee, Cheong-Ghil Kim, Shin-Dug Kim	A Pipelined Hardware Architecture for Motion Estimation of H.264/AVC.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF	array architecture, H.264/AVC and video coding, Motion estimation, variable block size, full search
40	Swee Yeow Yap, John V. McCanny	A VLSI Architecture for Advanced Video Coding Motion Estimation.	ASAP	2003	DBLP DOI BibTeX RDF
32	Amira Yahi, Salah Toumi, El-Bay Bourennane, Kamel Messaoudi	A speed FPGA hardware accelerator based FSBMA-VBSME used in H.264/AVC.	Evol. Syst.	2016	DBLP DOI BibTeX RDF
32	Amira Yahi, Kamel Messaoudi, Salah Toumi, El-Bey Bourennane	Hardware implementation for a new design of the VBSME Used in H.264/AVC.	CoDIT	2014	DBLP DOI BibTeX RDF
32	Joaquín Olivares 0001	Reconfigurable architecture for VBSME with variable pixel precision.	ACM Trans. Reconfigurable Technol. Syst.	2012	DBLP DOI BibTeX RDF
32	Joaquín Olivares 0001	Reconfigurable VBSME Architecture Using RBSAD.	J. Univers. Comput. Sci.	2012	DBLP DOI BibTeX RDF
32	Xing Wen, Oscar C. Au, Jiang Xu 0001, Lu Fang 0001, Run Cha, Jiali Li	Novel RD-Optimized VBSME With Matching Highly Data Re-Usable Hardware Architecture.	IEEE Trans. Circuits Syst. Video Technol.	2011	DBLP DOI BibTeX RDF
32	S. S. Mohite	Hardware architecture for VBSME using pixel truncation.	ICWET	2010	DBLP DOI BibTeX RDF
32	Qin Liu 0002, Yiqing Huang 0002, Satoshi Goto, Takeshi Ikenaga	Edge Block Detection and Motion Vector Information Based Fast VBSME Algorithm.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2008	DBLP DOI BibTeX RDF
32	Wei Cao 0002, Hui Hou, Jiarong Tong, Jinmei Lai, Hao Min	A high-performance reconfigurable VLSI architecture for vbsme in H.264.	IEEE Trans. Consumer Electron.	2008	DBLP DOI BibTeX RDF
32	Mohammed Sayed, Wael M. Badawy, Graham A. Jullien	Towards an H.264/AVC HW/SW Integrated Solution: An Efficient VBSME Architecture.	IEEE Trans. Circuits Syst. II Express Briefs	2008	DBLP DOI BibTeX RDF
32	Asral Bahari, Tughrul Arslan, Ahmet T. Erdogan	Reduced computation and memory access for VBSME using pixel truncation.	SoCC	2007	DBLP DOI BibTeX RDF
20	Ruchika Verma, Ali Akoglu	A coarse grained and hybrid reconfigurable architecture with flexible NoC router for variable block size motion estimation.	IPDPS	2008	DBLP DOI BibTeX RDF
20	Tsung-Han Tsai 0001, Yu-Nan Pan	High Efficiency Architecture of Fast Block Motion Estimation with Real-Time QFHD on H.264 Video Coding.	ISM	2008	DBLP DOI BibTeX RDF
20	Liang Lu, John V. McCanny, Sakir Sezer	Systolic Array Based Architecture for Variable Block-Size Motion Estimation.	AHS	2007	DBLP DOI BibTeX RDF
20	Mahdi Nazm Bojnordi, Mehdi Semsarzadeh, Mahmoud Reza Hashemi, Omid Fatemi	Efficient Hardware Implementation for H.264/AVC Motion Estimation.	APCCAS	2006	DBLP DOI BibTeX RDF