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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 13 occurrences of 10 keywords
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Results
Found 8 publication records. Showing 8 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
82 | Chetan Patel, Anthony Cozzie, Herman Schmit, Lawrence T. Pileggi |
An architectural exploration of via patterned gate arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2003 International Symposium on Physical Design, ISPD 2003, Monterey, CA, USA, April 6-9, 2003, pp. 184-189, 2003, ACM, 1-58113-650-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
VPGA, lookup table, interconnect architectures, gate array |
76 | Aneesh Koorapaty, V. Kheterpal, Padmini Gopalakrishnan, M. Fu, Lawrence T. Pileggi |
Exploring Logic Block Granularity for Regular Fabrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 468-473, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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76 | Aneesh Koorapaty, Lawrence T. Pileggi, Herman Schmit |
Heterogeneous Logic Block Architectures for Via-Patterned Programmable Fabrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings, pp. 426-436, 2003, Springer, 3-540-40822-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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56 | R. Reed Taylor, Herman Schmit |
Enabling energy efficiency in via-patterned gate array devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 874-878, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
VPGA, optimization, low-power, power, voltage scaling, structured ASIC |
42 | Abdelwahab Boualouache, Ridha Soua, Thomas Engel 0001 |
VPGA: An SDN-based Location Privacy Zones Placement Scheme for Vehicular Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPCCC ![In: 38th IEEE International Performance Computing and Communications Conference, IPCCC 2019, London, United Kingdom, October 29-31, 2019, pp. 1-8, 2019, IEEE, 978-1-7281-1025-7. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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42 | Kim Yaw Tong, V. Kheterpal, Vyacheslav Rovner, Lawrence T. Pileggi, Herman Schmit |
Regular logic fabrics for a via patterned gate array (VPGA). ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE Custom Integrated Circuits Conference, CICC 2003, San Jose, CA, USA, September 21 - 24, 2003, pp. 53-56, 2003, IEEE, 0-7803-7842-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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31 | R. Reed Taylor, Herman Schmit |
Creating a power-aware structured ASIC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 74-77, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
VPGA, low-power, voltage scaling, power optimization, gate sizing, structured ASIC |
25 | Thomas C. P. Chau, Philip Heng Wai Leong, Sam M. H. Ho, Brian P. W. Chan, Steve C. L. Yuen, Kong-Pang Pun, Oliver C. S. Choy, Xinan Wang |
A comparison of via-programmable gate array logic cell circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 53-62, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
logic cell, via-programmable gate arrays |
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