Search results for "area-constrained"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
43	David L. Foster, Darrin M. Hanna	Maximizing area-constrained partial fault tolerance in reconfigurable logic.	FPGA	2010	DBLP DOI BibTeX RDF	area-constrained, FPGA
30	Sridhar Rajagopal, Srikrishna Bhashyam, Joseph R. Cavallaro, Behnaam Aazhang	Efficient VLSI Architectures for Baseband Signal Processing in Wireless Base-Station Receivers.	ASAP	2000	DBLP DOI BibTeX RDF	real-time, Wireless communications, DSP, VLSI architecture, wideband CDMA, channel estimation
20	Ruibing Lu, Cheng-Kok Koh	Interconnect Planning with Local Area Constrained Retiming.	DATE	2003	DBLP DOI BibTeX RDF
14	Sridhar Rajagopal, Srikrishna Bhashyam, Joseph R. Cavallaro, Behnaam Aazhang	Efficient VLSI Architectures for Multiuser Channel Estimation in Wireless Base-Station Receivers.	J. VLSI Signal Process.	2002	DBLP DOI BibTeX RDF	multiuser channel estimation, VLSI, DSP, fixed-point, dependence graphs, W-CDMA, real-time implementation
12	Ajay Joshi, Gerald G. Lopez, Jeffrey A. Davis	Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed Routing.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
11	Xiangwan Fu, Anfeng Liu, Neal N. Xiong, Tian Wang 0001, Shaobo Zhang 0001	ATWR-SMR: An Area-Constrained Truthful-Worker Recruitment-Based Sensing Map Recovery Scheme for Sparse MCS in Extreme-Environment Internet of Things.	IEEE Internet Things J.	2024	DBLP DOI BibTeX RDF
11	P. V. N. Mohan Krishna, P. C. Sekhar	Area Constrained Optimal Planning Model of Renewable-Rich Hybrid Microgrid.	IEEE Access	2023	DBLP DOI BibTeX RDF
11	Nima D. Badizadegan	Newton-Raphson Integer Division for Area-Constrained Microcontrollers.	ARITH	2023	DBLP DOI BibTeX RDF
11	Angelito A. Silverio	Forward Body Bias Technique for Low Voltage and Area Constrained LDO Design in Deep Submicron Technologies.	ICECS	2021	DBLP DOI BibTeX RDF
11	Hsin-Tsung Lee, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang	On Synthesizing Memristor-Based Logic Circuits in Area-Constrained Crossbar Arrays.	ISQED	2021	DBLP DOI BibTeX RDF
11	Zihao Wang, Zhenzhou Wang	A generic approach for cell segmentation based on Gabor filtering and area-constrained ultimate erosion.	Artif. Intell. Medicine	2020	DBLP DOI BibTeX RDF
11	Toshiharu Sugie, Fei Tong, Brian D. O. Anderson, Zhiyong Sun	On global convergence of area-constrained formations of hierarchical multi-agent systems.	CoRR	2020	DBLP BibTeX RDF
11	Debjyoti Bhattacharjee, Anupam Chattopadhyay, Srijit Dutta, Ronny Ronen, Shahar Kvatinsky	CONTRA: Area-Constrained Technology Mapping Framework For Memristive Memory Processing Unit.	CoRR	2020	DBLP BibTeX RDF
11	Toshiharu Sugie, Fei Tong, Brian D. O. Anderson, Zhiyong Sun	On global convergence of area-constrained formations of hierarchical multi-agent systems.	CDC	2020	DBLP DOI BibTeX RDF
11	Maximilian Reuter, Johannes Pfau, Tillmann A. Krauss, Mahdi Moradinasab, Udo Schwalke, Jürgen Becker 0001, Klaus Hofmann	Towards Ambipolar Planar Devices: The DeFET Device in Area Constrained XOR Applications.	LASCAS	2020	DBLP DOI BibTeX RDF
11	Debjyoti Bhattacharjee, Anupam Chattopadhyay, Srijit Dutta, Ronny Ronen, Shahar Kvatinsky	CONTRA: Area-Constrained Technology Mapping Framework For Memristive Memory Processing Unit.	ICCAD	2020	DBLP DOI BibTeX RDF
11	Sergi Abadal, Eduard Alarcón	Data Conversion in Area-Constrained Applications: the Wireless Network-on-Chip Case.	CoRR	2019	DBLP BibTeX RDF
11	Yue Cao, Zhiyong Sun, Brian D. O. Anderson, Toshiharu Sugie	Almost Global Convergence For Distance- and Area-Constrained Hierarchical Formations Without Reflection.	ICCA	2019	DBLP DOI BibTeX RDF
11	Jacob Göppert, Simon Braun, David Pellhammer, Mohammad Amayreh, Joachim Leicht, Matthias Keller, Yiannos Manoli	Area Constrained Multi-Source Power Management for Thermoelectric Energy Harvesting.	ESSCIRC	2019	DBLP DOI BibTeX RDF
11	Priyajit Mukherjee, Sandeep D'Souza, Santanu Chattopadhyay	Area Constrained Performance Optimized ASNoC Synthesis with Thermal‐aware White Space Allocation and Redistribution.	Integr.	2018	DBLP DOI BibTeX RDF
11	Sachin Taneja, Massimo Alioto	Ultra-Low Power Crypto-Engine Based on Simon 32/64 for Energy- and Area-Constrained Integrated Systems.	CoRR	2018	DBLP BibTeX RDF
11	Sergi Abadal, Seyed Ehsan Hosseininejad, Albert Cabellos-Aparicio, Eduard Alarcón	Graphene-Based terahertz antennas for area-constrained applications.	CoRR	2018	DBLP BibTeX RDF
11	Sergi Abadal, Eduard Alarcón	Data Conversion in Area-Constrained Applications: the Wireless Network-on-Chip Case.	DCIS	2018	DBLP DOI BibTeX RDF
11	Manuel Strobel, Marcus Eggenberger, Martin Radetzki	Low power memory allocation and mapping for area-constrained systems-on-chips.	EURASIP J. Embed. Syst.	2017	DBLP DOI BibTeX RDF
11	Xiaoyang Mi, Hesam Fathi Moghadam, Jae-sun Seo	Flying and decoupling capacitance optimization for area-constrained on-chip switched-capacitor voltage regulators.	DATE	2017	DBLP DOI BibTeX RDF
11	Debjyoti Bhattacharjee, Arvind Easwaran, Anupam Chattopadhyay	Area-constrained technology mapping for in-memory computing using ReRAM devices.	ASP-DAC	2017	DBLP DOI BibTeX RDF
11	Sergi Abadal, Seyed Ehsan Hosseininejad, Albert Cabellos-Aparicio, Eduard Alarcón	Graphene-Based terahertz antennas for area-constrained applications.	TSP	2017	DBLP DOI BibTeX RDF
11	Jian Kang 0007, Sujaya Rao, Patrick Chiang 0001, Arun Natarajan 0001	Area-constrained wirelessly-powered UWB SoC design for small insect localization.	WiSNet	2016	DBLP DOI BibTeX RDF
11	Alfred Uwitonze, Jiaqing Huang, Yuanqing Ye, Wenqing Cheng	Area Constrained Space Information Flow.	GRMSE (2)	2016	DBLP DOI BibTeX RDF
11	David L. Foster, Darrin M. Hanna	Maximising area-constrained partial fault tolerance in reconfigurable logic using selection criteria.	Int. J. Embed. Syst.	2013	DBLP DOI BibTeX RDF
11	Javier Navaridas, Steve B. Furber, Jim D. Garside, Xin Jin 0003, Mukaram M. Khan, David R. Lester, Mikel Luján, José Miguel-Alonso, Eustace Painkras, Cameron Patterson, Luis A. Plana, Alexander D. Rast, Dominic Richards, Yebin Shi, Steve Temple, Jian Wu, Shufan Yang	SpiNNaker: Fault tolerance in a power- and area- constrained large-scale neuromimetic architecture.	Parallel Comput.	2013	DBLP DOI BibTeX RDF
11	Alok Prakash, Siew Kei Lam, Christopher T. Clarke, Thambipillai Srikanthan	Instruction set customization for area-constrained FPGA designs.	SoCC	2011	DBLP DOI BibTeX RDF
11	Basel Halak, Alexandre Yakovlev	Throughput Optimization for Area-Constrained Links With Crosstalk Avoidance Methods.	IEEE Trans. Very Large Scale Integr. Syst.	2010	DBLP DOI BibTeX RDF
11	Alpana Agarwal, Chandra Shekhar 0001	Figure-of-Merit-Based Area-Constrained Design of Differential Amplifiers.	VLSI Design	2008	DBLP DOI BibTeX RDF
11	Basel Halak, Alexandre Yakovlev	Bandwidth-Centric Optimisation for Area-Constrained Links with Crosstalk Avoidance Methods.	DATE	2008	DBLP DOI BibTeX RDF
11	Jorge Cortés 0001	Area-constrained coverage optimization by robotic sensor networks.	CDC	2008	DBLP DOI BibTeX RDF
11	Sharath Jayaprakash, Nihar R. Mahapatra	Energy-optimal signaling and ordering of bits for area-constrained interconnects.	SoCC	2008	DBLP DOI BibTeX RDF
11	Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy 0001	A Statistical Approach to Area-Constrained Yield Enhancement for Pipelined Circuits under Parameter Variations.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
11	Rajeev Murgai	Improved Layout-Driven Area-Constrained Timing Optimization by Net Buffering.	VLSI Design	2005	DBLP DOI BibTeX RDF
11	Rajeev Murgai	Layout-Driven Area-Constrained Timing Optimization by Net Buffering.	ICCAD	2000	DBLP DOI BibTeX RDF
11	Karam S. Chatha, Ranga Vemuri	An Iterative Algorithm for Partitioning and Scheduling of Area Constrained HW-SW Systems.	IEEE International Workshop on Rapid System Prototyping	1999	DBLP DOI BibTeX RDF	HW-SW Codesign, HW-SW Partitioning, Scheduling
10	Kanwar Jit Singh, Alberto L. Sangiovanni-Vincentelli	A Heuristic Algorithm for the Fanout Problem.	DAC	1990	DBLP DOI BibTeX RDF
9	Vishal Khandelwal, Ankur Srivastava 0001	Leakage Control Through Fine-Grained Placement and Sizing of Sleep Transistors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
9	Vishal Khandelwal, Ankur Srivastava 0001	Leakage control through fine-grained placement and sizing of sleep transistors.	ICCAD	2004	DBLP DOI BibTeX RDF
7	Lukasz Strozek, David M. Brooks	Energy- and area-efficient architectures through application clustering and architectural heterogeneity.	ACM Trans. Archit. Code Optim.	2009	DBLP DOI BibTeX RDF	Efficient custom architectures, heterogeneous ISA processors
7	Yongxin Ma, Xiaoyang Zeng, Min Wu, Chengshou Sun	A new low cost and reconfigurable RSA crypto-processor.	ISCAS	2006	DBLP DOI BibTeX RDF
7	Xin Cai, Martin A. Brooke	A compact CPU architecture for sensor signal processing.	ISCAS	2006	DBLP DOI BibTeX RDF
7	Ana Azevedo, Arun Kejariwal, Alexander V. Veidenbaum, Alexandru Nicolau	High performance annotation-aware JVM for Java cards.	EMSOFT	2005	DBLP DOI BibTeX RDF	superoperators, virtual machine, high performance, Java card
7	Wai-Kei Mak	Min-cut partitioning with functional replication fortechnology-mapped circuits using minimum area overhead.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
7	T. Vinod Kumar Gupta, Roberto E. Ko, Rajeev Barua	Compiler-directed customization of ASIP cores.	CODES	2002	DBLP DOI BibTeX RDF	soft cores, embedded, customization, ASIP
7	Wai-Kei Mak	Min-cut partitioning with functional replication for technology mapped circuits using minimum area overhead.	ISPD	2001	DBLP DOI BibTeX RDF	minimum cut, circuit partitioning, logic replication
7	En-Cheng Liu, Ming-Shiun Lin, Jianbang Lai, Ting-Chi Wang	Slicing floorplan design with boundary-constrained modules.	ISPD	2001	DBLP DOI BibTeX RDF
5	Tao Xu 0002, Krishnendu Chakrabarty	Integrated droplet routing and defect tolerance in the synthesis of digital microfluidic biochips.	ACM J. Emerg. Technol. Comput. Syst.	2008	DBLP DOI BibTeX RDF	Physical design automation, microfluidics, biochips, module placement
5	Lei He 0001, Andrew B. Kahng, King Ho Tam, Jinjun Xiong	Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random Leff Variation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
5	Tao Xu 0002, Krishnendu Chakrabarty	Integrated Droplet Routing in the Synthesis of Microfluidic Biochips.	DAC	2007	DBLP DOI BibTeX RDF
5	Guerric Meurice de Dormale, Jean-Jacques Quisquater	Iterative Modular Division over GF(2m): Novel Algorithm and Implementations on FPGA.	ARC	2006	DBLP DOI BibTeX RDF
5	Guerric Meurice de Dormale, Renaud Ambroise, David Bol, Jean-Jacques Quisquater, Jean-Didier Legat	Low-Cost Elliptic Curve Digital Signature Coprocessor for Smart Cards.	ASAP	2006	DBLP DOI BibTeX RDF
5	Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy 0001	Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
5	Cliff C. N. Sze, Ting-Chi Wang	Optimal circuit clustering for delay minimization under a more general delay model.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
5	Dinesh Pamunuwa, Hannu Tenhunen	On Dynamic Delay and Repeater Insertion in Distributed Capacitively Coupled Interconnects.	ISQED	2002	DBLP DOI BibTeX RDF	Cross-talk, Delay minimisation, Static timing, Repeater insertion, Deep sub-micron