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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 28 occurrences of 27 keywords
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Results
Found 60 publication records. Showing 60 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
43 | David L. Foster, Darrin M. Hanna |
Maximizing area-constrained partial fault tolerance in reconfigurable logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 259-262, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
area-constrained, FPGA |
30 | Sridhar Rajagopal, Srikrishna Bhashyam, Joseph R. Cavallaro, Behnaam Aazhang |
Efficient VLSI Architectures for Baseband Signal Processing in Wireless Base-Station Receivers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 12th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2000), 10-12 July 2000, Boston, MA, USA, pp. 173-184, 2000, IEEE Computer Society, 0-7695-0716-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
real-time, Wireless communications, DSP, VLSI architecture, wideband CDMA, channel estimation |
20 | Ruibing Lu, Cheng-Kok Koh |
Interconnect Planning with Local Area Constrained Retiming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 10442-10447, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
14 | Sridhar Rajagopal, Srikrishna Bhashyam, Joseph R. Cavallaro, Behnaam Aazhang |
Efficient VLSI Architectures for Multiuser Channel Estimation in Wireless Base-Station Receivers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 31(2), pp. 143-156, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
multiuser channel estimation, VLSI, DSP, fixed-point, dependence graphs, W-CDMA, real-time implementation |
12 | Ajay Joshi, Gerald G. Lopez, Jeffrey A. Davis |
Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed Routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(9), pp. 990-1002, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Xiangwan Fu, Anfeng Liu, Neal N. Xiong, Tian Wang 0001, Shaobo Zhang 0001 |
ATWR-SMR: An Area-Constrained Truthful-Worker Recruitment-Based Sensing Map Recovery Scheme for Sparse MCS in Extreme-Environment Internet of Things. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Internet Things J. ![In: IEEE Internet Things J. 11(3), pp. 3711-3724, February 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
11 | P. V. N. Mohan Krishna, P. C. Sekhar |
Area Constrained Optimal Planning Model of Renewable-Rich Hybrid Microgrid. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 11, pp. 70873-70883, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
11 | Nima D. Badizadegan |
Newton-Raphson Integer Division for Area-Constrained Microcontrollers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARITH ![In: 30th IEEE Symposium on Computer Arithmetic, ARITH 2023, Portland, OR, USA, September 4-6, 2023, pp. 9-15, 2023, IEEE, 979-8-3503-1922-4. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
11 | Angelito A. Silverio |
Forward Body Bias Technique for Low Voltage and Area Constrained LDO Design in Deep Submicron Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 28th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2021, Dubai, United Arab Emirates, November 28 - Dec. 1, 2021, pp. 1-4, 2021, IEEE, 978-1-7281-8281-0. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
11 | Hsin-Tsung Lee, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang |
On Synthesizing Memristor-Based Logic Circuits in Area-Constrained Crossbar Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 22nd International Symposium on Quality Electronic Design, ISQED 2021, Santa Clara, CA, USA, April 7-9, 2021, pp. 316, 2021, IEEE, 978-1-7281-7641-3. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
11 | Zihao Wang, Zhenzhou Wang |
A generic approach for cell segmentation based on Gabor filtering and area-constrained ultimate erosion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Artif. Intell. Medicine ![In: Artif. Intell. Medicine 107, pp. 101929, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
11 | Toshiharu Sugie, Fei Tong, Brian D. O. Anderson, Zhiyong Sun |
On global convergence of area-constrained formations of hierarchical multi-agent systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2009.03048, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
|
11 | Debjyoti Bhattacharjee, Anupam Chattopadhyay, Srijit Dutta, Ronny Ronen, Shahar Kvatinsky |
CONTRA: Area-Constrained Technology Mapping Framework For Memristive Memory Processing Unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2009.00881, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
|
11 | Toshiharu Sugie, Fei Tong, Brian D. O. Anderson, Zhiyong Sun |
On global convergence of area-constrained formations of hierarchical multi-agent systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CDC ![In: 59th IEEE Conference on Decision and Control, CDC 2020, Jeju Island, South Korea, December 14-18, 2020, pp. 2805-2810, 2020, IEEE, 978-1-7281-7447-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
11 | Maximilian Reuter, Johannes Pfau, Tillmann A. Krauss, Mahdi Moradinasab, Udo Schwalke, Jürgen Becker 0001, Klaus Hofmann |
Towards Ambipolar Planar Devices: The DeFET Device in Area Constrained XOR Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LASCAS ![In: 11th IEEE Latin American Symposium on Circuits & Systems, LASCAS 2020, San Jose, Costa Rica, February 25-28, 2020, pp. 1-4, 2020, IEEE, 978-1-7281-3427-7. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
11 | Debjyoti Bhattacharjee, Anupam Chattopadhyay, Srijit Dutta, Ronny Ronen, Shahar Kvatinsky |
CONTRA: Area-Constrained Technology Mapping Framework For Memristive Memory Processing Unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: IEEE/ACM International Conference On Computer Aided Design, ICCAD 2020, San Diego, CA, USA, November 2-5, 2020, pp. 150:1-150:9, 2020, IEEE. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
11 | Sergi Abadal, Eduard Alarcón |
Data Conversion in Area-Constrained Applications: the Wireless Network-on-Chip Case. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1906.05351, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
11 | Yue Cao, Zhiyong Sun, Brian D. O. Anderson, Toshiharu Sugie |
Almost Global Convergence For Distance- and Area-Constrained Hierarchical Formations Without Reflection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCA ![In: 15th IEEE International Conference on Control and Automation, ICCA 2019, Edinburgh, United Kingdom, July 16-19, 2019, pp. 1534-1539, 2019, IEEE, 978-1-7281-1164-3. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
11 | Jacob Göppert, Simon Braun, David Pellhammer, Mohammad Amayreh, Joachim Leicht, Matthias Keller, Yiannos Manoli |
Area Constrained Multi-Source Power Management for Thermoelectric Energy Harvesting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: 45th IEEE European Solid State Circuits Conference, ESSCIRC 2019, Cracow, Poland, September 23-26, 2019, pp. 141-144, 2019, IEEE, 978-1-7281-1550-4. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
11 | Priyajit Mukherjee, Sandeep D'Souza, Santanu Chattopadhyay |
Area Constrained Performance Optimized ASNoC Synthesis with Thermal‐aware White Space Allocation and Redistribution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 60, pp. 167-189, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
11 | Sachin Taneja, Massimo Alioto |
Ultra-Low Power Crypto-Engine Based on Simon 32/64 for Energy- and Area-Constrained Integrated Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1811.08507, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
11 | Sergi Abadal, Seyed Ehsan Hosseininejad, Albert Cabellos-Aparicio, Eduard Alarcón |
Graphene-Based terahertz antennas for area-constrained applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1801.03695, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
11 | Sergi Abadal, Eduard Alarcón |
Data Conversion in Area-Constrained Applications: the Wireless Network-on-Chip Case. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DCIS ![In: Conference on Design of Circuits and Integrated Systems, DCIS 2018, Lyon, France, November 14-16, 2018, pp. 1-6, 2018, IEEE, 978-1-7281-0171-2. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
11 | Manuel Strobel, Marcus Eggenberger, Martin Radetzki |
Low power memory allocation and mapping for area-constrained systems-on-chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURASIP J. Embed. Syst. ![In: EURASIP J. Embed. Syst. 2017, pp. 2, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Xiaoyang Mi, Hesam Fathi Moghadam, Jae-sun Seo |
Flying and decoupling capacitance optimization for area-constrained on-chip switched-capacitor voltage regulators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, pp. 1269-1272, 2017, IEEE, 978-3-9815370-8-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Debjyoti Bhattacharjee, Arvind Easwaran, Anupam Chattopadhyay |
Area-constrained technology mapping for in-memory computing using ReRAM devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017, Chiba, Japan, January 16-19, 2017, pp. 69-74, 2017, IEEE, 978-1-5090-1558-0. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Sergi Abadal, Seyed Ehsan Hosseininejad, Albert Cabellos-Aparicio, Eduard Alarcón |
Graphene-Based terahertz antennas for area-constrained applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TSP ![In: 40th International Conference on Telecommunications and Signal Processing, TSP 2017, Barcelona, Spain, July 5-7, 2017, pp. 817-820, 2017, IEEE, 978-1-5090-3982-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Jian Kang 0007, Sujaya Rao, Patrick Chiang 0001, Arun Natarajan 0001 |
Area-constrained wirelessly-powered UWB SoC design for small insect localization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WiSNet ![In: IEEE Topical Conference on Wireless Sensors and Sensor Networks, WiSNet 2016, Austin, TX, USA, January 24-27, 2016, pp. 18-20, 2016, IEEE, 978-1-5090-1691-4. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
11 | Alfred Uwitonze, Jiaqing Huang, Yuanqing Ye, Wenqing Cheng |
Area Constrained Space Information Flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GRMSE (2) ![In: Geo-Spatial Knowledge and Intelligence - 4th International Conference on Geo-Informatics in Resource Management and Sustainable Ecosystem, GRMSE 2016, Hong Kong, China, November 18-20, 2016, Revised Selected Papers, Part II, pp. 254-259, 2016, Springer, 978-981-10-3968-3. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
11 | David L. Foster, Darrin M. Hanna |
Maximising area-constrained partial fault tolerance in reconfigurable logic using selection criteria. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Embed. Syst. ![In: Int. J. Embed. Syst. 5(1/2), pp. 81-94, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
11 | Javier Navaridas, Steve B. Furber, Jim D. Garside, Xin Jin 0003, Mukaram M. Khan, David R. Lester, Mikel Luján, José Miguel-Alonso, Eustace Painkras, Cameron Patterson, Luis A. Plana, Alexander D. Rast, Dominic Richards, Yebin Shi, Steve Temple, Jian Wu, Shufan Yang |
SpiNNaker: Fault tolerance in a power- and area- constrained large-scale neuromimetic architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Parallel Comput. ![In: Parallel Comput. 39(11), pp. 693-708, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
11 | Alok Prakash, Siew Kei Lam, Christopher T. Clarke, Thambipillai Srikanthan |
Instruction set customization for area-constrained FPGA designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, September 26-28, 2011, pp. 329-334, 2011, IEEE, 978-1-4577-1616-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
11 | Basel Halak, Alexandre Yakovlev |
Throughput Optimization for Area-Constrained Links With Crosstalk Avoidance Methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 18(6), pp. 1016-1019, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
11 | Alpana Agarwal, Chandra Shekhar 0001 |
Figure-of-Merit-Based Area-Constrained Design of Differential Amplifiers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2008, pp. 847932:1-847932:5, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Basel Halak, Alexandre Yakovlev |
Bandwidth-Centric Optimisation for Area-Constrained Links with Crosstalk Avoidance Methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 438-443, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Jorge Cortés 0001 |
Area-constrained coverage optimization by robotic sensor networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CDC ![In: Proceedings of the 47th IEEE Conference on Decision and Control, CDC 2008, December 9-11, 2008, Cancún, Mexico, pp. 1018-1023, 2008, IEEE, 978-1-4244-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Sharath Jayaprakash, Nihar R. Mahapatra |
Energy-optimal signaling and ordering of bits for area-constrained interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 21st Annual IEEE International SoC Conference, SoCC 2008, September 17-20, 2008, Radisson Hotel, Newport Beach, CA, USA, Proceedings, pp. 9-12, 2008, IEEE, 978-1-4244-2596-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy 0001 |
A Statistical Approach to Area-Constrained Yield Enhancement for Pipelined Circuits under Parameter Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 170-175, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
11 | Rajeev Murgai |
Improved Layout-Driven Area-Constrained Timing Optimization by Net Buffering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp. 97-102, 2005, IEEE Computer Society, 0-7695-2264-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
11 | Rajeev Murgai |
Layout-Driven Area-Constrained Timing Optimization by Net Buffering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000, San Jose, California, USA, November 5-9, 2000, pp. 379-386, 2000, IEEE Computer Society, 0-7803-6448-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
11 | Karam S. Chatha, Ranga Vemuri |
An Iterative Algorithm for Partitioning and Scheduling of Area Constrained HW-SW Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping (RSP 1999), Clearwater, Florida, USA, June 16-18, 1999, pp. 134-139, 1999, IEEE Computer Society, 0-7695-0246-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
HW-SW Codesign, HW-SW Partitioning, Scheduling |
10 | Kanwar Jit Singh, Alberto L. Sangiovanni-Vincentelli |
A Heuristic Algorithm for the Fanout Problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, Florida, USA, June 24-28, 1990., pp. 357-360, 1990, IEEE Computer Society Press, 0-89791-363-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
9 | Vishal Khandelwal, Ankur Srivastava 0001 |
Leakage Control Through Fine-Grained Placement and Sizing of Sleep Transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7), pp. 1246-1255, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Vishal Khandelwal, Ankur Srivastava 0001 |
Leakage control through fine-grained placement and sizing of sleep transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 533-536, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
7 | Lukasz Strozek, David M. Brooks |
Energy- and area-efficient architectures through application clustering and architectural heterogeneity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 6(1), pp. 4:1-4:31, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Efficient custom architectures, heterogeneous ISA processors |
7 | Yongxin Ma, Xiaoyang Zeng, Min Wu, Chengshou Sun |
A new low cost and reconfigurable RSA crypto-processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
7 | Xin Cai, Martin A. Brooke |
A compact CPU architecture for sensor signal processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
7 | Ana Azevedo, Arun Kejariwal, Alexander V. Veidenbaum, Alexandru Nicolau |
High performance annotation-aware JVM for Java cards. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMSOFT ![In: EMSOFT 2005, September 18-22, 2005, Jersey City, NJ, USA, 5th ACM International Conference On Embedded Software, Proceedings, pp. 52-61, 2005, ACM, 1-59593-091-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
superoperators, virtual machine, high performance, Java card |
7 | Wai-Kei Mak |
Min-cut partitioning with functional replication fortechnology-mapped circuits using minimum area overhead. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(4), pp. 491-497, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
7 | T. Vinod Kumar Gupta, Roberto E. Ko, Rajeev Barua |
Compiler-directed customization of ASIP cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Tenth International Symposium on Hardware/Software Codesign, CODES 2002, Estes Park, Colorado, USA, May 6-8, 2002, pp. 97-102, 2002, ACM, 1-58113-542-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
soft cores, embedded, customization, ASIP |
7 | Wai-Kei Mak |
Min-cut partitioning with functional replication for technology mapped circuits using minimum area overhead. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2001 International Symposium on Physical Design, ISPD 2001, Sonoma County, CA, USA, April 1-4, 2001, pp. 100-105, 2001, ACM, 1-58113-347-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
minimum cut, circuit partitioning, logic replication |
7 | En-Cheng Liu, Ming-Shiun Lin, Jianbang Lai, Ting-Chi Wang |
Slicing floorplan design with boundary-constrained modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2001 International Symposium on Physical Design, ISPD 2001, Sonoma County, CA, USA, April 1-4, 2001, pp. 124-129, 2001, ACM, 1-58113-347-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
5 | Tao Xu 0002, Krishnendu Chakrabarty |
Integrated droplet routing and defect tolerance in the synthesis of digital microfluidic biochips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 4(3), pp. 11:1-11:24, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Physical design automation, microfluidics, biochips, module placement |
5 | Lei He 0001, Andrew B. Kahng, King Ho Tam, Jinjun Xiong |
Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random Leff Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(5), pp. 845-857, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
5 | Tao Xu 0002, Krishnendu Chakrabarty |
Integrated Droplet Routing in the Synthesis of Microfluidic Biochips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 948-953, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
5 | Guerric Meurice de Dormale, Jean-Jacques Quisquater |
Iterative Modular Division over GF(2m): Novel Algorithm and Implementations on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures and Applications, Second International Workshop, ARC 2006, Delft, The Netherlands, March 1-3, 2006, Revised Selected Papers, pp. 370-382, 2006, Springer. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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5 | Guerric Meurice de Dormale, Renaud Ambroise, David Bol, Jean-Jacques Quisquater, Jean-Didier Legat |
Low-Cost Elliptic Curve Digital Signature Coprocessor for Smart Cards. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 2006 IEEE International Conference on Application-Specific Systems, Architecture and Processors (ASAP 2006), 11-13 September 2006, Steamboat Springs, Colorado, USA, pp. 347-353, 2006, IEEE Computer Society, 0-7695-2682-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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5 | Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy 0001 |
Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(11), pp. 1286-1295, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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5 | Cliff C. N. Sze, Ting-Chi Wang |
Optimal circuit clustering for delay minimization under a more general delay model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(5), pp. 646-651, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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5 | Dinesh Pamunuwa, Hannu Tenhunen |
On Dynamic Delay and Repeater Insertion in Distributed Capacitively Coupled Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002, pp. 240-245, 2002, IEEE Computer Society, 0-7695-1561-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Cross-talk, Delay minimisation, Static timing, Repeater insertion, Deep sub-micron |
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