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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 32 occurrences of 29 keywords
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Results
Found 37 publication records. Showing 37 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
39 | Pankaj Golani, Peter A. Beerel |
Back Annotation in High Speed Asynchronous Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings, pp. 227-236, 2005, Springer, 3-540-29013-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
32 | Kui Wang, Lian Duan, Xu Cheng |
ExtensiveSlackBalance: an approach to make front-end tools aware of clock skew scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 951-954, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
back-annotation, skew scheduling, logic synthesis, clock skew |
16 | Rezgar Sadeghi, Nooshin Nosrati, Katayoon Basharkhah, Zainalabedin Navabi |
Back-annotation of Interconnect Physical Properties for System-Level Crosstalk Modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 24th IEEE European Test Symposium, ETS 2019, Baden-Baden, Germany, May 27-31, 2019, pp. 1-6, 2019, IEEE, 978-1-7281-1173-5. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Dongwook Lee, Lizy K. John, Andreas Gerstlauer |
Dynamic power and performance back-annotation for fast and accurate functional hardware simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, DATE 2015, Grenoble, France, March 9-13, 2015, pp. 1126-1131, 2015, ACM, 978-3-9815370-4-8. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP BibTeX RDF |
|
16 | Ábel Hegedüs |
Back-Annotation of Execution Sequences by Advanced Search and Traceability Techniques ![Search on Bibsonomy](Pics/bibsonomy.png) |
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2015 |
RDF |
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16 | Najmeh Farajipour Ghohroud, Zainalabedin Navabi |
Back-annotation of gate-level power properties into system level descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NEWCAS ![In: IEEE 12th International New Circuits and Systems Conference, NEWCAS 2014, Trois-Rivieres, QC, Canada, June 22-25, 2014, pp. 237-240, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Suhas Chakravarty, Zhuoran Zhao, Andreas Gerstlauer |
Automated, retargetable back-annotation for host compiled performance and power modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2013, Montreal, QC, Canada, September 29 - October 4, 2013, pp. 36:1-36:10, 2013, IEEE, 978-1-4799-1417-3. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Trevor Harmon, Martin Schoeberl, Raimund Kirner, Raymond Klefstad, Kwang-Hae (Kane) Kim, Michael R. Lowry |
Fast, Interactive Worst-Case Execution Time Analysis With Back-Annotation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Ind. Informatics ![In: IEEE Trans. Ind. Informatics 8(2), pp. 366-377, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Ábel Hegedüs, Gábor Bergmann, István Ráth, Dániel Varró |
Back-annotation of Simulation Traces with Change-Driven Model Transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SEFM ![In: 8th IEEE International Conference on Software Engineering and Formal Methods, SEFM 2010, Pisa, Italy, 13-18 September 2010, pp. 145-155, 2010, IEEE Computer Society, 978-0-7695-4153-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Trevor Harmon, Raymond Klefstad |
Interactive Back-annotation of Worst-case Execution Time Analysis for Java Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007), 21-24 August 2007, Daegu, Korea, pp. 209-216, 2007, IEEE Computer Society, 0-7695-2975-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Pankaj Golani, Peter A. Beerel |
Back-Annotation in High-Speed Asynchronous Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 2(1), pp. 37-44, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli |
Post-synthesis back-annotation of timing information in behavioral VHDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Archit. ![In: J. Syst. Archit. 42(9-10), pp. 725-741, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
16 | Mario Calha, Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira 0001 |
Back Annotation of Physical Defects into Gate-Level, Realistic Faults in Digital ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1994, TEST: The Next 25 Years, Washington, DC, USA, October 2-6, 1994, pp. 720-728, 1994, IEEE Computer Society, 0-7803-2103-0. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
16 | Zainalabedin Navabi, Mehran Massoumi |
Investigating simulation of hardware at various levels of abstraction and timing back-annotation of dataflow descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Simul. ![In: Simul. 57(5), pp. 321-332, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
13 | Jay K. Adams, John Alan Miller, Donald E. Thomas |
Execution-time profiling for multiple-process behavioral synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 144-149, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
execution-time profiling, multiple-process behavioral synthesis, back-annotating, source description, behavioral simulation model, annotated behavioral simulation, high level synthesis, high-level synthesis, timing, timing, logic CAD, digital simulation, circuit analysis computing, hardware design, software profiling, register-transfer level model |
9 | Zhonglei Wang, Andreas Herkersdorf |
An efficient approach for system-level timing simulation of compiler-optimized embedded software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 220-225, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
iSciSim, software timing simulation, system level design |
9 | Kevin Camera, Robert W. Brodersen |
An integrated debugging environment for FPGA computing platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008, pp. 260, 2008, ACM, 978-1-59593-934-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
simulation, FPGA, design, verification |
9 | Kevin Camera, Robert W. Brodersen |
An integrated debugging environment for FPGA computing platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, pp. 311-316, 2008, IEEE, 978-1-4244-1961-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Angelo Gargantini, Elvinia Riccobene, Patrizia Scandurra |
A model-driven validation & verification environment for embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIES ![In: IEEE Third International Symposium on Industrial Embedded Systems, SIES 2008, Montpellier / La Grande Motte, France, June 11-13, 2008, pp. 241-244, 2008, IEEE, 978-1-4244-1994-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Esther Guerra, Daniel Sanz, Paloma Díaz 0001, Ignacio Aedo |
A Transformation-Driven Approach to the Verification of Security Policies in Web Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICWE ![In: Web Engineering, 7th International Conference, ICWE 2007, Como, Italy, July 16-20, 2007, Proceedings, pp. 269-284, 2007, Springer, 978-3-540-73596-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Mauri Kuorilehto, Mikko Kohvakka, Marko Hännikäinen, Timo D. Hämäläinen |
High Abstraction Level Design and Implementation Framework for Wireless Sensor Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation 5th International Workshop, SAMOS 2005, Samos, Greece, July 18-20, 2005, Proceedings, pp. 384-393, 2005, Springer, 3-540-26969-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
9 | Sotiris Bantas, Yorgos Koutsoyannopoulos, Apostolos Liapis |
An Inductance Modeling Flow Seamlessly Integrated in the RF IC Design Chain. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 39-45, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
9 | Cliff C. N. Sze, Ting-Chi Wang |
Optimal circuit clustering for delay minimization under a more general delay model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(5), pp. 646-651, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
9 | Silvia Brini, Doha Benjelloun, Fabien Castanier |
A Flexible Virtual Platform for Computational and Communication Architecture Exploration of DMT VDSL Modems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 20164-20169, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
9 | Imed Moussa, Thierry Grellier, Giang Nguyen |
Exploring SW Performance Using SoC Transaction-Level Modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 20120-20125, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
9 | Abdelaziz Ammari, Régis Leveugle, Matteo Sonza Reorda, Massimo Violante |
Detailed Comparison of Dependability Analyses Performed at RT and Gate Levels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 3-5 November 2003, Boston, MA, USA, Proceedings, pp. 336-343, 2003, IEEE Computer Society, 0-7695-2042-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
9 | Luca Benini, Luca Macchiarulo, Alberto Macii, Massimo Poncino |
Layout-driven memory synthesis for embedded systems-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 10(2), pp. 96-105, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
9 | Jordi Cortadella, Michael Kishinevsky, Steven M. Burns, Alex Kondratyev, Luciano Lavagno, Ken S. Stevens, Alexander Taubin, Alexandre Yakovlev |
Lazy transition systems and asynchronous circuit synthesis withrelative timing assumptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(2), pp. 109-130, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
9 | Davide Bertozzi, Luca Benini, Bruno Riccò |
Parametric timing and power macromodels for high level simulation of low-swing interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002, pp. 307-312, 2002, ACM, 1-58113-475-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
delay, interconnect, power, macromodel, low-swing |
9 | Cliff C. N. Sze, Ting-Chi Wang |
Optimal circuit clustering with variable interconnect delay. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 707-710, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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9 | Klaus Harbich, Erich Barke |
PuMA++: From Behavioral Specification to Multi-FPGA-Prototype. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001, Proceedings, pp. 133-141, 2001, Springer, 3-540-42499-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
9 | Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai |
Timing optimization on routed designs with incremental placementand routing characterization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(2), pp. 188-196, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
9 | Crina Anton, Pierluigi Civera, Ionel Colonescu, Enrico Macii, Massimo Poncino, Alessandro Bogliolo |
RTL Estimation of Steering Logic Power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation, 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000, Proceedings, pp. 36-46, 2000, Springer, 3-540-41068-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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9 | Marco A. Peña, Jordi Cortadella, Enric Pastor, Alex Kondratyev |
Formal Verification of Safety Properties in Timed Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2-6 April 2000, Eilat, Israel, pp. 2-11, 2000, IEEE Computer Society, 0-7695-0586-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Formal verification, asynchronous circuits, timing analysis |
9 | Andrew R. Conn, Paula K. Coulman, Ruud A. Haring, Gregory L. Morrill, Chandramouli Visweswariah, Chai Wah Wu |
JiffyTune: circuit optimization using time-domain sensitivities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(12), pp. 1292-1309, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
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9 | Toshihiro Hattori, Yusuke Nitta, Mitsuho Seki, Susumu Narita, Kunio Uchiyama, Tsuyoshi Takahashi, Ryuichi Satomura |
Design Methodology of a 200MHz Superscalar Microprocessor: SH-4. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 246-249, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
verification, timing, design methodology, microprocessor |
9 | Andrew R. Conn, Paula K. Coulman, Ruud A. Haring, Gregory L. Morrill, Chandramouli Visweswariah |
Optimization of custom MOS circuits by transistor sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 174-180, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
simulation, optimization, Circuits, gradients, transistor sizing |
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