Search results for "back-annotation"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
39	Pankaj Golani, Peter A. Beerel	Back Annotation in High Speed Asynchronous Design.	PATMOS	2005	DBLP DOI BibTeX RDF
32	Kui Wang, Lian Duan, Xu Cheng	ExtensiveSlackBalance: an approach to make front-end tools aware of clock skew scheduling.	DAC	2006	DBLP DOI BibTeX RDF	back-annotation, skew scheduling, logic synthesis, clock skew
16	Rezgar Sadeghi, Nooshin Nosrati, Katayoon Basharkhah, Zainalabedin Navabi	Back-annotation of Interconnect Physical Properties for System-Level Crosstalk Modeling.	ETS	2019	DBLP DOI BibTeX RDF
16	Dongwook Lee, Lizy K. John, Andreas Gerstlauer	Dynamic power and performance back-annotation for fast and accurate functional hardware simulation.	DATE	2015	DBLP BibTeX RDF
16	Ábel Hegedüs	Back-Annotation of Execution Sequences by Advanced Search and Traceability Techniques		2015	RDF
16	Najmeh Farajipour Ghohroud, Zainalabedin Navabi	Back-annotation of gate-level power properties into system level descriptions.	NEWCAS	2014	DBLP DOI BibTeX RDF
16	Suhas Chakravarty, Zhuoran Zhao, Andreas Gerstlauer	Automated, retargetable back-annotation for host compiled performance and power modeling.	CODES+ISSS	2013	DBLP DOI BibTeX RDF
16	Trevor Harmon, Martin Schoeberl, Raimund Kirner, Raymond Klefstad, Kwang-Hae (Kane) Kim, Michael R. Lowry	Fast, Interactive Worst-Case Execution Time Analysis With Back-Annotation.	IEEE Trans. Ind. Informatics	2012	DBLP DOI BibTeX RDF
16	Ábel Hegedüs, Gábor Bergmann, István Ráth, Dániel Varró	Back-annotation of Simulation Traces with Change-Driven Model Transformations.	SEFM	2010	DBLP DOI BibTeX RDF
16	Trevor Harmon, Raymond Klefstad	Interactive Back-annotation of Worst-case Execution Time Analysis for Java Microprocessors.	RTCSA	2007	DBLP DOI BibTeX RDF
16	Pankaj Golani, Peter A. Beerel	Back-Annotation in High-Speed Asynchronous Design.	J. Low Power Electron.	2006	DBLP DOI BibTeX RDF
16	Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli	Post-synthesis back-annotation of timing information in behavioral VHDL.	J. Syst. Archit.	1997	DBLP DOI BibTeX RDF
16	Mario Calha, Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira 0001	Back Annotation of Physical Defects into Gate-Level, Realistic Faults in Digital ICs.	ITC	1994	DBLP DOI BibTeX RDF
16	Zainalabedin Navabi, Mehran Massoumi	Investigating simulation of hardware at various levels of abstraction and timing back-annotation of dataflow descriptions.	Simul.	1991	DBLP DOI BibTeX RDF
13	Jay K. Adams, John Alan Miller, Donald E. Thomas	Execution-time profiling for multiple-process behavioral synthesis.	ICCD	1995	DBLP DOI BibTeX RDF	execution-time profiling, multiple-process behavioral synthesis, back-annotating, source description, behavioral simulation model, annotated behavioral simulation, high level synthesis, high-level synthesis, timing, timing, logic CAD, digital simulation, circuit analysis computing, hardware design, software profiling, register-transfer level model
9	Zhonglei Wang, Andreas Herkersdorf	An efficient approach for system-level timing simulation of compiler-optimized embedded software.	DAC	2009	DBLP DOI BibTeX RDF	iSciSim, software timing simulation, system level design
9	Kevin Camera, Robert W. Brodersen	An integrated debugging environment for FPGA computing platforms.	FPGA	2008	DBLP DOI BibTeX RDF	simulation, FPGA, design, verification
9	Kevin Camera, Robert W. Brodersen	An integrated debugging environment for FPGA computing platforms.	FPL	2008	DBLP DOI BibTeX RDF
9	Angelo Gargantini, Elvinia Riccobene, Patrizia Scandurra	A model-driven validation & verification environment for embedded systems.	SIES	2008	DBLP DOI BibTeX RDF
9	Esther Guerra, Daniel Sanz, Paloma Díaz 0001, Ignacio Aedo	A Transformation-Driven Approach to the Verification of Security Policies in Web Designs.	ICWE	2007	DBLP DOI BibTeX RDF
9	Mauri Kuorilehto, Mikko Kohvakka, Marko Hännikäinen, Timo D. Hämäläinen	High Abstraction Level Design and Implementation Framework for Wireless Sensor Networks.	SAMOS	2005	DBLP DOI BibTeX RDF
9	Sotiris Bantas, Yorgos Koutsoyannopoulos, Apostolos Liapis	An Inductance Modeling Flow Seamlessly Integrated in the RF IC Design Chain.	DATE	2004	DBLP DOI BibTeX RDF
9	Cliff C. N. Sze, Ting-Chi Wang	Optimal circuit clustering for delay minimization under a more general delay model.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
9	Silvia Brini, Doha Benjelloun, Fabien Castanier	A Flexible Virtual Platform for Computational and Communication Architecture Exploration of DMT VDSL Modems.	DATE	2003	DBLP DOI BibTeX RDF
9	Imed Moussa, Thierry Grellier, Giang Nguyen	Exploring SW Performance Using SoC Transaction-Level Modeling.	DATE	2003	DBLP DOI BibTeX RDF
9	Abdelaziz Ammari, Régis Leveugle, Matteo Sonza Reorda, Massimo Violante	Detailed Comparison of Dependability Analyses Performed at RT and Gate Levels.	DFT	2003	DBLP DOI BibTeX RDF
9	Luca Benini, Luca Macchiarulo, Alberto Macii, Massimo Poncino	Layout-driven memory synthesis for embedded systems-on-chip.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
9	Jordi Cortadella, Michael Kishinevsky, Steven M. Burns, Alex Kondratyev, Luciano Lavagno, Ken S. Stevens, Alexander Taubin, Alexandre Yakovlev	Lazy transition systems and asynchronous circuit synthesis withrelative timing assumptions.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
9	Davide Bertozzi, Luca Benini, Bruno Riccò	Parametric timing and power macromodels for high level simulation of low-swing interconnects.	ISLPED	2002	DBLP DOI BibTeX RDF	delay, interconnect, power, macromodel, low-swing
9	Cliff C. N. Sze, Ting-Chi Wang	Optimal circuit clustering with variable interconnect delay.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
9	Klaus Harbich, Erich Barke	PuMA++: From Behavioral Specification to Multi-FPGA-Prototype.	FPL	2001	DBLP DOI BibTeX RDF
9	Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai	Timing optimization on routed designs with incremental placementand routing characterization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
9	Crina Anton, Pierluigi Civera, Ionel Colonescu, Enrico Macii, Massimo Poncino, Alessandro Bogliolo	RTL Estimation of Steering Logic Power.	PATMOS	2000	DBLP DOI BibTeX RDF
9	Marco A. Peña, Jordi Cortadella, Enric Pastor, Alex Kondratyev	Formal Verification of Safety Properties in Timed Circuits.	ASYNC	2000	DBLP DOI BibTeX RDF	Formal verification, asynchronous circuits, timing analysis
9	Andrew R. Conn, Paula K. Coulman, Ruud A. Haring, Gregory L. Morrill, Chandramouli Visweswariah, Chai Wah Wu	JiffyTune: circuit optimization using time-domain sensitivities.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
9	Toshihiro Hattori, Yusuke Nitta, Mitsuho Seki, Susumu Narita, Kunio Uchiyama, Tsuyoshi Takahashi, Ryuichi Satomura	Design Methodology of a 200MHz Superscalar Microprocessor: SH-4.	DAC	1998	DBLP DOI BibTeX RDF	verification, timing, design methodology, microprocessor
9	Andrew R. Conn, Paula K. Coulman, Ruud A. Haring, Gregory L. Morrill, Chandramouli Visweswariah	Optimization of custom MOS circuits by transistor sizing.	ICCAD	1996	DBLP DOI BibTeX RDF	simulation, optimization, Circuits, gradients, transistor sizing