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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 304 occurrences of 226 keywords
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Results
Found 1032 publication records. Showing 1032 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
146 | Juan A. Carrasco |
Failure Transition Distance-Based Importance Sampling Schemes for theSimulation of Repairable Fault-Tolerant Computer Systems. |
IEEE Trans. Reliab. |
2006 |
DBLP DOI BibTeX RDF |
|
109 | Marvin K. Nakayama |
A Characterization of the Simple Failure-Biasing Method for Simulations of Highly Reliable Markovian Systems. |
ACM Trans. Model. Comput. Simul. |
1994 |
DBLP DOI BibTeX RDF |
balanced failure biasing, highly reliable systems, simple failure biasing, importance sampling, likelihood ratios, gradient estimation |
78 | Jun Yuan 0007, Kurt Shultz, Carl Pixley, Hillel Miller, Adnan Aziz |
Modeling design constraints and biasing in simulation using BDDs. |
ICCAD |
1999 |
DBLP DOI BibTeX RDF |
|
78 | Alyssa Bonnoit, Lawrence T. Pileggi |
Reducing variability in chip-multiprocessors with adaptive body biasing. |
ISLPED |
2010 |
DBLP DOI BibTeX RDF |
dynamic voltage/frequency scaling, body biasing |
78 | Po-Yuan Chen, Chiao-Chen Fang, TingTing Hwang, Hsi-Pin Ma |
Leakage reduction, delay compensation using partition-based tunable body-biasing techniques. |
ACM Trans. Design Autom. Electr. Syst. |
2009 |
DBLP DOI BibTeX RDF |
low-power design, process variations, leakage current, Body biasing |
78 | Jun Yuan 0007, Kurt Shultz, Carl Pixley, Hillel Miller, Adnan Aziz |
Automatic Vector Generation Using Constraints and Biasing. |
J. Electron. Test. |
2000 |
DBLP DOI BibTeX RDF |
constraint, probability, partitioning, BDD, biasing, vector generation |
73 | Jinseob Jeong, Seungwhun Paik, Youngsoo Shin |
Statistical mixed Vt allocation of body-biased circuits for reduced leakage variation. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
68 | Puneet Gupta 0001, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester |
Gate-length biasing for runtime-leakage control. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
68 | Andrew B. Kahng, Swamy Muddu, Puneet Sharma |
Impact of Gate-Length Biasing on Threshold-Voltage Selection. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
68 | Aleksandar Tasic, Wouter A. Serdijn, John R. Long |
Low-noise biasing of voltage-controlled oscillators by means of resonant inductive degeneration. |
ISCAS (1) |
2003 |
DBLP DOI BibTeX RDF |
|
67 | Pradip Mandal, V. Visvanathan |
Design of high performance two stage CMOS cascode op-amps with stable biasing. |
VLSI Design |
1996 |
DBLP DOI BibTeX RDF |
two stage CMOS cascode op-amps, stable biasing, mirror biasing, output voltage, bias variations, low frequency common mode rejection ratios, power supply rejection ratios, systematic offset, circuit analysis computing, performance metrics, integrated circuit design, circuit simulations, operational amplifiers, CMOS analogue integrated circuits, slew rate, circuit stability |
63 | Juan A. Carrasco |
Adapted Importance Sampling Schemes for the Simulation of Dependability Models of Fault-Tolerant Systems with Deferred Repair. |
Annual Simulation Symposium |
2006 |
DBLP DOI BibTeX RDF |
|
57 | Sunwoo Kwon, Hoi Lee |
A 1.2V, 3.5µW, 20MS/s, 8-bit comparator with dynamic-biasing preamplifier. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
57 | Claude R. Gauthier, Jayakumaran Sivagnaname, Richard B. Brown |
Dynamic Receiver Biasing For Inter-Chip Communication. |
ARVLSI |
2001 |
DBLP DOI BibTeX RDF |
|
57 | Rino Micheloni, Matteo Zammattio, Giovanni Campardo, Osama Khouri, Guido Torelli |
Hierarchical Sector Biasing Organization for Flash Memories. |
MTDT |
2000 |
DBLP DOI BibTeX RDF |
|
57 | Sumanth Amarchinta, Dhireesha Kudithipudi |
Performance enhancement of subthreshold circuits using substrate biasing and charge-boosting buffers. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
charge-boosters, subthreshold design, biasing |
57 | Zhenhua Wang |
Adaptive analog biasing: a robustness-enhanced low-power technique for analog baseband design. |
ISLPED |
2007 |
DBLP DOI BibTeX RDF |
robustness enhancement, sensitivity reduction, low-power, low-energy, analog integrated circuits, biasing |
57 | Sergio Gagliolo, Giacomo Pruzzo, Daniele D. Caviglia |
Phase noise performances of a cross-coupled CMOS VCO with resistor tail biasing. |
SBCCI |
2005 |
DBLP DOI BibTeX RDF |
resistor biasing, low power, wireless, CMOS, low voltage, voltage controlled oscillator (VCO), phase noise |
52 | Tom W. Chen, Justin Gregg |
A Low Cost Individual-Well Adaptive Body Bias (IWABB) Scheme for Leakage Power Reduction and Performance Enhancement in the Presence of Intra-Die Variations. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
52 | Saumil Shah, Puneet Gupta 0001, Andrew B. Kahng |
Standard cell library optimization for leakage reduction. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
gate-length biasing, library optimization, leakage reduction |
47 | Reza Hashemian |
Use of local biasing in designing analog integrated circuits. |
EIT |
2008 |
DBLP DOI BibTeX RDF |
|
47 | Liviu Panait, Sean Luke, R. Paul Wiegand |
Biasing Coevolutionary Search for Optimal Multiagent Behaviors. |
IEEE Trans. Evol. Comput. |
2006 |
DBLP DOI BibTeX RDF |
|
47 | Leonard A. MacEachern, Eyad Abou-Allam, L. Wang, Tajinder Manku |
Low voltage mixer biasing using monolithic integrated transformer dc-coupling. |
ISCAS (2) |
1999 |
DBLP DOI BibTeX RDF |
|
46 | Alyssa Bonnoit, Sebastian Herbert, Diana Marculescu, Lawrence T. Pileggi |
Integrating dynamic voltage/frequency scaling and adaptive body biasing using test-time voltage selection. |
ISLPED |
2009 |
DBLP DOI BibTeX RDF |
dynamic voltage / frequency scaling, body biasing |
46 | Vishal Khandelwal, Ankur Srivastava 0001 |
Active mode leakage reduction using fine-grained forward body biasing strategy. |
ISLPED |
2004 |
DBLP DOI BibTeX RDF |
forward body biasing, leakage power optimization |
42 | Liviu Panait, R. Paul Wiegand, Sean Luke |
A Sensitivity Analysis of a Cooperative Coevolutionary Algorithm Biased for Optimization. |
GECCO (1) |
2004 |
DBLP DOI BibTeX RDF |
|
41 | Amlan Ghosh, Rahul M. Rao, Richard B. Brown |
A centralized supply voltage and local body bias-based compensation approach to mitigate within-die process variation. |
ISLPED |
2009 |
DBLP DOI BibTeX RDF |
fine-grain body-biasing, process variation compensation, slewrate |
41 | Jabulani Nyathi, Brent Bero |
Logic circuits operating in subthreshold voltages. |
ISLPED |
2006 |
DBLP DOI BibTeX RDF |
logic styles, medium-to-high speed, off current, ultra-low power, noise margins, subthreshold, body biasing |
41 | Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy 0001 |
A forward body-biased low-leakage SRAM cache: device and architecture considerations. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
forward body-biasing, super high VT, SRAM, leakage power |
36 | Koichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye |
Experimental study on body-biasing layout style-- negligible area overhead enables sufficient speed controllability --. |
ACM Great Lakes Symposium on VLSI |
2008 |
DBLP DOI BibTeX RDF |
layout, body bias |
36 | Radu Teodorescu, Jun Nakano, Abhishek Tiwari 0002, Josep Torrellas |
Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing. |
MICRO |
2007 |
DBLP DOI BibTeX RDF |
|
36 | Chun-Kit Au, Ho-fung Leung |
Biasing mutations in cooperative coevolution. |
IEEE Congress on Evolutionary Computation |
2007 |
DBLP DOI BibTeX RDF |
|
36 | Alexander Fish, Tomer Rothschild, Avichay Hodes, Yonatan Shoshan, Orly Yadid-Pecht |
Low Power CMOS Image Sensors Employing Adaptive Bulk Biasing Control (AB2C) Approach. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
36 | Dongkyu Park, Byunghoo Jung |
Low power LC-VCO design using direct cross-coupled cell biasing. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
36 | Keng Hoong Wee, Ji-Jon Sit, Rahul Sarpeshkar |
Biasing techniques for subthreshold MOS resistive grids. |
ISCAS (3) |
2005 |
DBLP DOI BibTeX RDF |
|
36 | Walid Elgharbawy, Pradeep Golconda, Ashok Kumar 0001, Magdy A. Bayoumi |
A new gate-level body biasing technique for PMOS transistors in subthreshold CMOS circuits. |
ISCAS (5) |
2005 |
DBLP DOI BibTeX RDF |
|
36 | Puneet Gupta 0001, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester |
Selective gate-length biasing for cost-effective runtime leakage control. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
power, layout, manufacturability, leakage, OPC, lithography |
36 | Arturo Sarmiento-Reyes, Erhan Yildiz, Chris J. M. Verhoeven, Arie van Staveren |
A CAD-oriented method for optimal biasing of amplifiers. |
ISCAS (1) |
2002 |
DBLP DOI BibTeX RDF |
|
36 | Chris J. M. Verhoeven, Arie van Staveren |
Systematic Biasing of Negative Feedback Amplifiers. |
DATE |
1999 |
DBLP DOI BibTeX RDF |
|
36 | Yan Zhang 0028, Mircea R. Stan |
Temperature-aware circuit design using adaptive body biasing. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
adaptive body biasing, temperature-aware design |
31 | Bipul C. Paul, Kaushik Roy 0001 |
Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits. |
J. Electron. Test. |
2006 |
DBLP DOI BibTeX RDF |
adaptive body bias design, statistical analysis, process variation, delay fault testing |
31 | Bo Fu, Paul Ampadu |
Techniques for robust energy efficient subthreshold domino CMOS circuits. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Andrea Lodi 0002, Luca Ciccarelli, Roberto Giansante |
Combining low-leakage techniques for FPGA routing design. |
FPGA |
2005 |
DBLP DOI BibTeX RDF |
low leakage, FPGA, power |
31 | Scott McCoy, Peter V. Marks, Christopher L. Carr, Victor Wacham A. Mbarika |
Electronic Versus Paper Surveys: Analysis of Potential Psychometric Biases. |
HICSS |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Bipul Chandra Paul, Cassondra Neau, Kaushik Roy 0001 |
Impact of Body Bias on Delay Fault Testing of Nanoscale CMOS Circuits. |
ITC |
2004 |
DBLP DOI BibTeX RDF |
|
31 | S. V. Gopalaiah, A. P. Shivaprasad, Sukanta K. Panigrahi |
Design of Low Voltage Low Power CMOS OP-AMPS with Rail-to-Rail Input/Output Swing. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Mahipal Dargupally, Lomash Chandra Acharya, Khoirom Johnson Singh, Neha Gupta, Arvind K. Sharma, Sudeb Dasgupta, Anand Bulusu |
An Efficient Standard Cell Design Methodology by Exploiting Body Biasing and Poly Biasing in FDSOI for NTV Regime. |
APCCAS |
2023 |
DBLP DOI BibTeX RDF |
|
31 | Andrew Whetzel, Mircea R. Stan |
Gate Overdrive with Split-Circuit Biasing to Substitute for Body Biasing in FinFET and UTB FDSOI Circuits. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
31 | Yuan Cai, Marcus T. Schmitz, Bashir M. Al-Hashimi, Sudhakar M. Reddy |
Workload-ahead-driven online energy minimization techniques for battery-powered embedded systems with time-constraints. |
ACM Trans. Design Autom. Electr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
adaptive body biasing, embedded systems, Dynamic voltage scaling, battery |
31 | Domenik Helms, Olaf Meyer, Marko Hoyer, Wolfgang Nebel |
Voltage- and ABB-island optimization in high level synthesis. |
ISLPED |
2007 |
DBLP DOI BibTeX RDF |
adaptive body biasing, process variation, leakage, voltage islands |
31 | Swaroop Ghosh, Saibal Mukhopadhyay, Keejong Kim, Kaushik Roy 0001 |
Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
adaptive source biasing, hold failures, low power SRAM |
31 | Nikhil Jayakumar, Sandeep Dhar, Sunil P. Khatri |
A self-adjusting scheme to determine the optimum RBB by monitoring leakage currents. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
leakage power, self-adjusting, body-biasing |
31 | Le Yan, Lin Zhong 0001, Niraj K. Jha |
User-perceived latency driven voltage scaling for interactive applications. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
adaptive body biasing, computer responsiveness, dynamic voltage scaling, power consumption |
31 | Tsung-Chu Huang, Min-Cheng Huang, Kuen-Jong Lee |
Built-in current sensor designs based on the bulk-driven technique. |
Asian Test Symposium |
1997 |
DBLP DOI BibTeX RDF |
bulk-driven current mirror, biasing schemes, low power dissipation, power supply voltage drop, circuit speed degradation, external power supply, 0.3 V, 0.3 ns, accuracy, flexibility, simplicity, built-in current sensor, area overhead, I/sub DDQ/ testing, electric current measurement |
31 | A. B. Bhattacharyya, Ram Singh Rana, S. K. Guha, Rajendar Bahl, R. Anand, M. J. Zarabi, P. A. Govindacharyulu, U. Gupta, V. Mohan, Jatin Roy, Amul Atri |
A micropower analog hearing aid on low voltage CMOS digital process. |
VLSI Design |
1996 |
DBLP DOI BibTeX RDF |
differential amplifiers, automatic gain control, micropower analog hearing aid, low voltage CMOS digital process, adaptive biasing, MOS translinear loop circuit, degenerating linearising resistor, input differential stage, AGC block, conversion efficiency, 3 micron, 1.0 V, power consumption, CMOS analogue integrated circuits, hearing aids |
31 | Guido Rovetta, Patrizia Monteforte, Gerolamo Bianchi, Stefano Rovetta, Rodolfo Zunino |
Validation of a Large Medical Database. |
CBMS |
1995 |
DBLP DOI BibTeX RDF |
large medical database, database validation, clinical problems, experimental evidence, observed data validation, incorrect sampling, sample distribution, data-inherent regularities, unsupervised models, clinical records analysis, osteoporosis, data distribution uniformity, unbiased sampling, neural networks, data integrity, probability, unsupervised learning, neural nets, medical information systems, very large databases, biasing |
26 | Xin He, Syed Al-Kadry, Afshin Abdollahi |
Adaptive leakage control on body biasing for reducing power consumption in CMOS VLSI circuit. |
ISQED |
2009 |
DBLP DOI BibTeX RDF |
|
26 | Matthew Zucker 0001, James Kuffner, James A. Bagnell |
Adaptive workspace biasing for sampling-based planners. |
ICRA |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Zhenyu Qi, Mircea R. Stan |
NBTI resilient circuits using adaptive body biasing. |
ACM Great Lakes Symposium on VLSI |
2008 |
DBLP DOI BibTeX RDF |
reliability, body bias, nbti |
26 | Justin Gregg, Tom W. Chen |
Post Silicon Power/Performance Optimization in the Presence of Process Variations Using Individual Well-Adaptive Body Biasing. |
IEEE Trans. Very Large Scale Integr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Shawna L. Thomas, Marco Morales 0001, Xinyu Tang, Nancy M. Amato |
Biasing Samplers to Improve Motion Planning Performance. |
ICRA |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Kyung Ki Kim, Yong-Bin Kim |
Optimal Body Biasing for Minimum Leakage Power in Standby Mode. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Afshin Nourivand, Chunyan Wang 0004, M. Omair Ahmad |
An Adaptive Sleep Transistor Biasing Scheme for Low Leakage SRAM. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Byunghee Choi, Youngsoo Shin |
Lookup Table-Based Adaptive Body Biasing of Multiple Macros. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Rajiv V. Joshi, Keunwoo Kim, Richard Q. Williams, Edward J. Nowak, Ching-Te Chuang |
A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Po-Kuan Huang, Soheil Ghiasi |
Power-aware compilation for embedded processors with dynamic voltage scaling and adaptive body biasing capabilities. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Byungsub Kim, Soumyajit Mandal, Rahul Sarpeshkar |
Power-adaptive operational amplifier with positive-feedback self biasing. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Le Yan, Jiong Luo, Niraj K. Jha |
Joint dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Giridhar Kumaran, Rosie Jones, Omid Madani |
Biasing web search results for topic familiarity. |
CIKM |
2005 |
DBLP DOI BibTeX RDF |
personalization, web search, familiarity |
26 | Kiyotaka Imai, Yasushi Yamagata, Sadaaki Masuoka, Naohiko Kimuzuka, Yuri Yasuda, Mitsuhiro Togo, Masahiro Ikeda, Yasutaka Nakashiba |
Device technology for body biasing scheme. |
ISCAS (1) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Maurice Meijer, Francesco Pessolano, José Pineda de Gyvez |
Limits to performance spread tuning using adaptive voltage and body biasing. |
ISCAS (1) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Louie Pylarinos, Khoman Phang |
Low-voltage programmable gm-C filter for hearing aids using dynamic gate biasing. |
ISCAS (3) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Sean Nicolson, Khoman Phang |
Improvements in biasing and compensation of CMOS opamps. |
ISCAS (1) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Le Yan, Jiong Luo, Niraj K. Jha |
Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-time Embedded Systems. |
ICCAD |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Steven M. Martin, Krisztián Flautner, Trevor N. Mudge, David T. Blaauw |
Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads. |
ICCAD |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Esteban Tlelo-Cuautle |
An efficient biasing technique suitable for any kind of the four basic amplifiers designed at or level. |
ISCAS (3) |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Martin V. Butz |
Biasing Exploration in an Anticipatory Learning Classifier System. |
IWLCS |
2001 |
DBLP DOI BibTeX RDF |
|
26 | Giuseppe Palmisano, Salvatore Pennisi |
Low-voltage continuous-time CMOS current amplifier with dynamic biasing. |
ISCAS (1) |
2001 |
DBLP DOI BibTeX RDF |
|
21 | Anuj Pushkarna, Hamid Mahmoodi |
Reliability analysis of power gated SRAM under combined effects of NBTI and PBTI in nano-scale CMOS. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
reliability, aging, SRAM, power gating |
21 | Martin Pelikan, Kumara Sastry |
Initial-population bias in the univariate estimation of distribution algorithm. |
GECCO |
2009 |
DBLP DOI BibTeX RDF |
noisy onemax, onemax, population bias, time to convergence, scalability, estimation of distribution algorithms, population size, edas, univariate marginal distribution algorithm, umda |
21 | Kwangok Jeong, Andrew B. Kahng, Hailong Yao |
Revisiting the linear programming framework for leakage power vs. performance optimization. |
ISQED |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Ashish Srivastava, Kaviraj Chopra, Saumil Shah, Dennis Sylvester, David T. Blaauw |
A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Andrew B. Kahng, Sudhakar Muddu, Puneet Sharma |
Defocus-Aware Leakage Estimation and Control. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Josef Haid, Bernd Zimek, Thomas Leutgeb, Thomas Künemund |
Impact of Leakage Current on Data Retention of RF-powered Devices During Amplitude-Modulation-based Communication. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Vinay Agarwal, Sameer R. Sonkusale |
A PVT independent subthreshold constant-Gm stage for very low frequency applications. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin |
Substrate Noise Reduction Based On Noise Aware Cell Design. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Guochen Hua, Meng Wang 0005, Zili Shao, Hui Liu 0006, Chun Xue |
Real-Time Loop Scheduling with Energy Optimization Via DVS and ABB for Multi-core Embedded System. |
EUC |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Günther R. Raidl, Gabriele Koller, Bryant A. Julstrom |
Biased Mutation Operators for Subgraph-Selection Problems. |
IEEE Trans. Evol. Comput. |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Tianbin Wo, Peter Adam Hoeher, Ansgar Scherb, Karl-Dirk Kammeyer |
Performance Analysis of Maximum-Likelihood Semiblind Estimation of MIMO Channels. |
VTC Spring |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Dan Kamosny, Vit Novotyny, Miroslav Balík |
Bandwidth Redistribution Algorithm for Single Source Multicast. |
ICN/ICONS/MCL |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Xian Ping Fan, Pak Kwong Chan |
Improving Source-Follower Buffer for High-Speed ADC Testing. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Andrew B. Kahng, Swamy Muddu, Puneet Sharma |
Defocus-aware leakage estimation and control. |
ISLPED |
2005 |
DBLP DOI BibTeX RDF |
ACLV, yield, leakage, lithography |
21 | Philomena C. Brady, Paul E. Hasler |
Offset compensation in flash ADCs using floating-gate circuits. |
ISCAS (6) |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Xiaohui Cui, C. Tim Hardin, Rammohan K. Ragade, Adel Said Elmaghraby |
A Swarm Approach for Emission Sources Localization. |
ICTAI |
2004 |
DBLP DOI BibTeX RDF |
|
21 | S. V. Gopalaiah, A. P. Shivaprasad |
Low Voltage CMOS op-amp with Rail-to-Rail Input/Output Swing. |
DELTA |
2004 |
DBLP DOI BibTeX RDF |
|
21 | Daniela De Venuto, Michael J. Ohletz |
On-Chip Test for Mixed-Signal ASICs using Two-Mode Comparators with Bias-Programmable Reference Voltages. |
J. Electron. Test. |
2001 |
DBLP DOI BibTeX RDF |
mixed-signal ASIC, hardware conversion, GO/NOGO test, bias programming, DfT, power consumption, overhead |
21 | Tommy Kwong-Kin Tsang, Mourad N. El-Gamal |
A fully integrated 1 V 5.8 GHz bipolar LNA. |
ISCAS (4) |
2001 |
DBLP DOI BibTeX RDF |
|
21 | Damon S. Love, Sudhakar Yalamanchili, José Duato, María Blanca Caminero, Francisco J. Quiles 0001 |
Switch Scheduling in the Multimedia Router (MMR). |
IPDPS |
2000 |
DBLP DOI BibTeX RDF |
Quality of Service (QoS), Multimedia traffic, Router architecture, Switch scheduling |
21 | Yu-Chuan Shih, Chung-Yu Wu |
The design of high-performance 128×128 CMOS image sensors using new current-readout techniques. |
ISCAS (5) |
1999 |
DBLP DOI BibTeX RDF |
|
21 | Ashok K. Chandra, Vijay S. Iyengar, D. Jameson, R. V. Jawalekar, Indira Nair, Barry K. Rosen, Michael P. Mullen, J. Yoon, R. Armoni, Daniel Geist, Yaron Wolfsthal |
AVPGEN-A test generator for architecture verification. |
IEEE Trans. Very Large Scale Integr. Syst. |
1995 |
DBLP DOI BibTeX RDF |
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