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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 304 occurrences of 226 keywords
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Results
Found 1032 publication records. Showing 1032 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
146 | Juan A. Carrasco |
Failure Transition Distance-Based Importance Sampling Schemes for theSimulation of Repairable Fault-Tolerant Computer Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Reliab. ![In: IEEE Trans. Reliab. 55(2), pp. 207-236, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
109 | Marvin K. Nakayama |
A Characterization of the Simple Failure-Biasing Method for Simulations of Highly Reliable Markovian Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Model. Comput. Simul. ![In: ACM Trans. Model. Comput. Simul. 4(1), pp. 52-88, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
balanced failure biasing, highly reliable systems, simple failure biasing, importance sampling, likelihood ratios, gradient estimation |
78 | Jun Yuan 0007, Kurt Shultz, Carl Pixley, Hillel Miller, Adnan Aziz |
Modeling design constraints and biasing in simulation using BDDs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 584-590, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
78 | Alyssa Bonnoit, Lawrence T. Pileggi |
Reducing variability in chip-multiprocessors with adaptive body biasing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010, pp. 73-78, 2010, ACM, 978-1-4503-0146-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
dynamic voltage/frequency scaling, body biasing |
78 | Po-Yuan Chen, Chiao-Chen Fang, TingTing Hwang, Hsi-Pin Ma |
Leakage reduction, delay compensation using partition-based tunable body-biasing techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 14(4), pp. 53:1-53:22, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
low-power design, process variations, leakage current, Body biasing |
78 | Jun Yuan 0007, Kurt Shultz, Carl Pixley, Hillel Miller, Adnan Aziz |
Automatic Vector Generation Using Constraints and Biasing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(1-2), pp. 107-120, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
constraint, probability, partitioning, BDD, biasing, vector generation |
73 | Jinseob Jeong, Seungwhun Paik, Youngsoo Shin |
Statistical mixed Vt allocation of body-biased circuits for reduced leakage variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 629-634, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
68 | Puneet Gupta 0001, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester |
Gate-length biasing for runtime-leakage control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(8), pp. 1475-1485, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
68 | Andrew B. Kahng, Swamy Muddu, Puneet Sharma |
Impact of Gate-Length Biasing on Threshold-Voltage Selection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 747-754, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
68 | Aleksandar Tasic, Wouter A. Serdijn, John R. Long |
Low-noise biasing of voltage-controlled oscillators by means of resonant inductive degeneration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 673-676, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
67 | Pradip Mandal, V. Visvanathan |
Design of high performance two stage CMOS cascode op-amps with stable biasing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 234-237, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
two stage CMOS cascode op-amps, stable biasing, mirror biasing, output voltage, bias variations, low frequency common mode rejection ratios, power supply rejection ratios, systematic offset, circuit analysis computing, performance metrics, integrated circuit design, circuit simulations, operational amplifiers, CMOS analogue integrated circuits, slew rate, circuit stability |
63 | Juan A. Carrasco |
Adapted Importance Sampling Schemes for the Simulation of Dependability Models of Fault-Tolerant Systems with Deferred Repair. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Annual Simulation Symposium ![In: Proceedings 39th Annual Simulation Symposium (ANSS-39 2006), 2-6 April 2006, Huntsville, Alabama, USA, pp. 107-117, 2006, IEEE Computer Society, 0-7695-2559-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
57 | Sunwoo Kwon, Hoi Lee |
A 1.2V, 3.5µW, 20MS/s, 8-bit comparator with dynamic-biasing preamplifier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
57 | Claude R. Gauthier, Jayakumaran Sivagnaname, Richard B. Brown |
Dynamic Receiver Biasing For Inter-Chip Communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 19th Conference on Advanced Research in VLSI (ARVLSI 2001), 14-16 March 2001, Salt Lake City, UT, USA, pp. 101-111, 2001, IEEE Computer Society, 0-7695-1037-X. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
57 | Rino Micheloni, Matteo Zammattio, Giovanni Campardo, Osama Khouri, Guido Torelli |
Hierarchical Sector Biasing Organization for Flash Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 8th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2000), 7-8 August 2000, San Jose, CA, USA, pp. 29-33, 2000, IEEE Computer Society, 0-7695-0689-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
57 | Sumanth Amarchinta, Dhireesha Kudithipudi |
Performance enhancement of subthreshold circuits using substrate biasing and charge-boosting buffers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 369-372, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
charge-boosters, subthreshold design, biasing |
57 | Zhenhua Wang |
Adaptive analog biasing: a robustness-enhanced low-power technique for analog baseband design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 383-386, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
robustness enhancement, sensitivity reduction, low-power, low-energy, analog integrated circuits, biasing |
57 | Sergio Gagliolo, Giacomo Pruzzo, Daniele D. Caviglia |
Phase noise performances of a cross-coupled CMOS VCO with resistor tail biasing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2005, Florianolpolis, Brazil, September 4-7, 2005, pp. 149-153, 2005, ACM. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
resistor biasing, low power, wireless, CMOS, low voltage, voltage controlled oscillator (VCO), phase noise |
52 | Tom W. Chen, Justin Gregg |
A Low Cost Individual-Well Adaptive Body Bias (IWABB) Scheme for Leakage Power Reduction and Performance Enhancement in the Presence of Intra-Die Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 240-245, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
52 | Saumil Shah, Puneet Gupta 0001, Andrew B. Kahng |
Standard cell library optimization for leakage reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 983-986, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
gate-length biasing, library optimization, leakage reduction |
47 | Reza Hashemian |
Use of local biasing in designing analog integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EIT ![In: 2008 IEEE International Conference on Electro/Information Technology, EIT 2008, held at Iowa State University, Ames, Iowa, USA, May 18-20, 2008, pp. 123-127, 2008, IEEE, 978-1-4244-2030-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
47 | Liviu Panait, Sean Luke, R. Paul Wiegand |
Biasing Coevolutionary Search for Optimal Multiagent Behaviors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Evol. Comput. ![In: IEEE Trans. Evol. Comput. 10(6), pp. 629-645, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
47 | Leonard A. MacEachern, Eyad Abou-Allam, L. Wang, Tajinder Manku |
Low voltage mixer biasing using monolithic integrated transformer dc-coupling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 180-183, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
46 | Alyssa Bonnoit, Sebastian Herbert, Diana Marculescu, Lawrence T. Pileggi |
Integrating dynamic voltage/frequency scaling and adaptive body biasing using test-time voltage selection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 207-212, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
dynamic voltage / frequency scaling, body biasing |
46 | Vishal Khandelwal, Ankur Srivastava 0001 |
Active mode leakage reduction using fine-grained forward body biasing strategy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 150-155, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
forward body biasing, leakage power optimization |
42 | Liviu Panait, R. Paul Wiegand, Sean Luke |
A Sensitivity Analysis of a Cooperative Coevolutionary Algorithm Biased for Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GECCO (1) ![In: Genetic and Evolutionary Computation - GECCO 2004, Genetic and Evolutionary Computation Conference, Seattle, WA, USA, June 26-30, 2004, Proceedings, Part I, pp. 573-584, 2004, Springer, 3-540-22344-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
41 | Amlan Ghosh, Rahul M. Rao, Richard B. Brown |
A centralized supply voltage and local body bias-based compensation approach to mitigate within-die process variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 45-50, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
fine-grain body-biasing, process variation compensation, slewrate |
41 | Jabulani Nyathi, Brent Bero |
Logic circuits operating in subthreshold voltages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 131-134, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
logic styles, medium-to-high speed, off current, ultra-low power, noise margins, subthreshold, body biasing |
41 | Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy 0001 |
A forward body-biased low-leakage SRAM cache: device and architecture considerations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 6-9, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
forward body-biasing, super high VT, SRAM, leakage power |
36 | Koichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye |
Experimental study on body-biasing layout style-- negligible area overhead enables sufficient speed controllability --. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 387-390, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
layout, body bias |
36 | Radu Teodorescu, Jun Nakano, Abhishek Tiwari 0002, Josep Torrellas |
Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 1-5 December 2007, Chicago, Illinois, USA, pp. 27-42, 2007, IEEE Computer Society, 0-7695-3047-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
36 | Chun-Kit Au, Ho-fung Leung |
Biasing mutations in cooperative coevolution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Congress on Evolutionary Computation ![In: Proceedings of the IEEE Congress on Evolutionary Computation, CEC 2007, 25-28 September 2007, Singapore, pp. 828-835, 2007, IEEE, 978-1-4244-1339-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
36 | Alexander Fish, Tomer Rothschild, Avichay Hodes, Yonatan Shoshan, Orly Yadid-Pecht |
Low Power CMOS Image Sensors Employing Adaptive Bulk Biasing Control (AB2C) Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 2834-2837, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
36 | Dongkyu Park, Byunghoo Jung |
Low power LC-VCO design using direct cross-coupled cell biasing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
36 | Keng Hoong Wee, Ji-Jon Sit, Rahul Sarpeshkar |
Biasing techniques for subthreshold MOS resistive grids. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2164-2167, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
36 | Walid Elgharbawy, Pradeep Golconda, Ashok Kumar 0001, Magdy A. Bayoumi |
A new gate-level body biasing technique for PMOS transistors in subthreshold CMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 4697-4700, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
36 | Puneet Gupta 0001, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester |
Selective gate-length biasing for cost-effective runtime leakage control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 327-330, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
power, layout, manufacturability, leakage, OPC, lithography |
36 | Arturo Sarmiento-Reyes, Erhan Yildiz, Chris J. M. Verhoeven, Arie van Staveren |
A CAD-oriented method for optimal biasing of amplifiers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 741-744, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
36 | Chris J. M. Verhoeven, Arie van Staveren |
Systematic Biasing of Negative Feedback Amplifiers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 318-322, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
36 | Yan Zhang 0028, Mircea R. Stan |
Temperature-aware circuit design using adaptive body biasing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 84-89, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
adaptive body biasing, temperature-aware design |
31 | Bipul C. Paul, Kaushik Roy 0001 |
Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 22(2), pp. 115-124, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
adaptive body bias design, statistical analysis, process variation, delay fault testing |
31 | Bo Fu, Paul Ampadu |
Techniques for robust energy efficient subthreshold domino CMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Andrea Lodi 0002, Luca Ciccarelli, Roberto Giansante |
Combining low-leakage techniques for FPGA routing design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005, pp. 208-214, 2005, ACM, 1-59593-029-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
low leakage, FPGA, power |
31 | Scott McCoy, Peter V. Marks, Christopher L. Carr, Victor Wacham A. Mbarika |
Electronic Versus Paper Surveys: Analysis of Potential Psychometric Biases. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS ![In: 37th Hawaii International Conference on System Sciences (HICSS-37 2004), CD-ROM / Abstracts Proceedings, 5-8 January 2004, Big Island, HI, USA, 2004, IEEE Computer Society, 0-7695-2056-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Bipul Chandra Paul, Cassondra Neau, Kaushik Roy 0001 |
Impact of Body Bias on Delay Fault Testing of Nanoscale CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 1269-1275, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
31 | S. V. Gopalaiah, A. P. Shivaprasad, Sukanta K. Panigrahi |
Design of Low Voltage Low Power CMOS OP-AMPS with Rail-to-Rail Input/Output Swing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 57-, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Mahipal Dargupally, Lomash Chandra Acharya, Khoirom Johnson Singh, Neha Gupta, Arvind K. Sharma, Sudeb Dasgupta, Anand Bulusu |
An Efficient Standard Cell Design Methodology by Exploiting Body Biasing and Poly Biasing in FDSOI for NTV Regime. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023, Hyderabad, India, November 19-22, 2023, pp. 105-109, 2023, IEEE, 979-8-3503-8119-1. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
31 | Andrew Whetzel, Mircea R. Stan |
Gate Overdrive with Split-Circuit Biasing to Substitute for Body Biasing in FinFET and UTB FDSOI Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016, Pittsburgh, PA, USA, July 11-13, 2016, pp. 467-472, 2016, IEEE Computer Society, 978-1-4673-9039-2. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
31 | Yuan Cai, Marcus T. Schmitz, Bashir M. Al-Hashimi, Sudhakar M. Reddy |
Workload-ahead-driven online energy minimization techniques for battery-powered embedded systems with time-constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 12(1), pp. 5:1-5:24, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
adaptive body biasing, embedded systems, Dynamic voltage scaling, battery |
31 | Domenik Helms, Olaf Meyer, Marko Hoyer, Wolfgang Nebel |
Voltage- and ABB-island optimization in high level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 153-158, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
adaptive body biasing, process variation, leakage, voltage islands |
31 | Swaroop Ghosh, Saibal Mukhopadhyay, Keejong Kim, Kaushik Roy 0001 |
Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 971-976, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
adaptive source biasing, hold failures, low power SRAM |
31 | Nikhil Jayakumar, Sandeep Dhar, Sunil P. Khatri |
A self-adjusting scheme to determine the optimum RBB by monitoring leakage currents. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 43-46, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
leakage power, self-adjusting, body-biasing |
31 | Le Yan, Lin Zhong 0001, Niraj K. Jha |
User-perceived latency driven voltage scaling for interactive applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 624-627, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
adaptive body biasing, computer responsiveness, dynamic voltage scaling, power consumption |
31 | Tsung-Chu Huang, Min-Cheng Huang, Kuen-Jong Lee |
Built-in current sensor designs based on the bulk-driven technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 384-, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
bulk-driven current mirror, biasing schemes, low power dissipation, power supply voltage drop, circuit speed degradation, external power supply, 0.3 V, 0.3 ns, accuracy, flexibility, simplicity, built-in current sensor, area overhead, I/sub DDQ/ testing, electric current measurement |
31 | A. B. Bhattacharyya, Ram Singh Rana, S. K. Guha, Rajendar Bahl, R. Anand, M. J. Zarabi, P. A. Govindacharyulu, U. Gupta, V. Mohan, Jatin Roy, Amul Atri |
A micropower analog hearing aid on low voltage CMOS digital process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 85-89, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
differential amplifiers, automatic gain control, micropower analog hearing aid, low voltage CMOS digital process, adaptive biasing, MOS translinear loop circuit, degenerating linearising resistor, input differential stage, AGC block, conversion efficiency, 3 micron, 1.0 V, power consumption, CMOS analogue integrated circuits, hearing aids |
31 | Guido Rovetta, Patrizia Monteforte, Gerolamo Bianchi, Stefano Rovetta, Rodolfo Zunino |
Validation of a Large Medical Database. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CBMS ![In: Eighth Annual IEEE Symposium on Computer-Based Medical Systems (CBMS'95), June 9-10, 1995, Lubbock, Texas, USA, pp. 57-64, 1995, IEEE Computer Society, 0-8186-7117-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
large medical database, database validation, clinical problems, experimental evidence, observed data validation, incorrect sampling, sample distribution, data-inherent regularities, unsupervised models, clinical records analysis, osteoporosis, data distribution uniformity, unbiased sampling, neural networks, data integrity, probability, unsupervised learning, neural nets, medical information systems, very large databases, biasing |
26 | Xin He, Syed Al-Kadry, Afshin Abdollahi |
Adaptive leakage control on body biasing for reducing power consumption in CMOS VLSI circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 465-470, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
26 | Matthew Zucker 0001, James Kuffner, James A. Bagnell |
Adaptive workspace biasing for sampling-based planners. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICRA ![In: 2008 IEEE International Conference on Robotics and Automation, ICRA 2008, May 19-23, 2008, Pasadena, California, USA, pp. 3757-3762, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Zhenyu Qi, Mircea R. Stan |
NBTI resilient circuits using adaptive body biasing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 285-290, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
reliability, body bias, nbti |
26 | Justin Gregg, Tom W. Chen |
Post Silicon Power/Performance Optimization in the Presence of Process Variations Using Individual Well-Adaptive Body Biasing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(3), pp. 366-376, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Shawna L. Thomas, Marco Morales 0001, Xinyu Tang, Nancy M. Amato |
Biasing Samplers to Improve Motion Planning Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICRA ![In: 2007 IEEE International Conference on Robotics and Automation, ICRA 2007, 10-14 April 2007, Roma, Italy, pp. 1625-1630, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Kyung Ki Kim, Yong-Bin Kim |
Optimal Body Biasing for Minimum Leakage Power in Standby Mode. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1161-1164, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Afshin Nourivand, Chunyan Wang 0004, M. Omair Ahmad |
An Adaptive Sleep Transistor Biasing Scheme for Low Leakage SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 2790-2793, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Byunghee Choi, Youngsoo Shin |
Lookup Table-Based Adaptive Body Biasing of Multiple Macros. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 533-538, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Rajiv V. Joshi, Keunwoo Kim, Richard Q. Williams, Edward J. Nowak, Ching-Te Chuang |
A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 665-672, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Po-Kuan Huang, Soheil Ghiasi |
Power-aware compilation for embedded processors with dynamic voltage scaling and adaptive body biasing capabilities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 943-944, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Byungsub Kim, Soumyajit Mandal, Rahul Sarpeshkar |
Power-adaptive operational amplifier with positive-feedback self biasing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Le Yan, Jiong Luo, Niraj K. Jha |
Joint dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(7), pp. 1030-1041, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Giridhar Kumaran, Rosie Jones, Omid Madani |
Biasing web search results for topic familiarity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIKM ![In: Proceedings of the 2005 ACM CIKM International Conference on Information and Knowledge Management, Bremen, Germany, October 31 - November 5, 2005, pp. 271-272, 2005, ACM, 1-59593-140-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
personalization, web search, familiarity |
26 | Kiyotaka Imai, Yasushi Yamagata, Sadaaki Masuoka, Naohiko Kimuzuka, Yuri Yasuda, Mitsuhiro Togo, Masahiro Ikeda, Yasutaka Nakashiba |
Device technology for body biasing scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 13-16, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Maurice Meijer, Francesco Pessolano, José Pineda de Gyvez |
Limits to performance spread tuning using adaptive voltage and body biasing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 5-8, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Louie Pylarinos, Khoman Phang |
Low-voltage programmable gm-C filter for hearing aids using dynamic gate biasing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1984-1987, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Sean Nicolson, Khoman Phang |
Improvements in biasing and compensation of CMOS opamps. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 665-668, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Le Yan, Jiong Luo, Niraj K. Jha |
Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-time Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2003 International Conference on Computer-Aided Design, ICCAD 2003, San Jose, CA, USA, November 9-13, 2003, pp. 30-38, 2003, IEEE Computer Society / ACM, 1-58113-762-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Steven M. Martin, Krisztián Flautner, Trevor N. Mudge, David T. Blaauw |
Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 721-725, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Esteban Tlelo-Cuautle |
An efficient biasing technique suitable for any kind of the four basic amplifiers designed at or level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 535-538, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Martin V. Butz |
Biasing Exploration in an Anticipatory Learning Classifier System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWLCS ![In: Advances in Learning Classifier Systems, 4th International Workshop, IWLCS 2001, San Francisco, CA, USA, July 7-8, 2001, Revised Papers, pp. 3-22, 2001, Springer, 3-540-43793-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
26 | Giuseppe Palmisano, Salvatore Pennisi |
Low-voltage continuous-time CMOS current amplifier with dynamic biasing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 312-315, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
21 | Anuj Pushkarna, Hamid Mahmoodi |
Reliability analysis of power gated SRAM under combined effects of NBTI and PBTI in nano-scale CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 373-376, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
reliability, aging, SRAM, power gating |
21 | Martin Pelikan, Kumara Sastry |
Initial-population bias in the univariate estimation of distribution algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GECCO ![In: Genetic and Evolutionary Computation Conference, GECCO 2009, Proceedings, Montreal, Québec, Canada, July 8-12, 2009, pp. 429-436, 2009, ACM, 978-1-60558-325-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
noisy onemax, onemax, population bias, time to convergence, scalability, estimation of distribution algorithms, population size, edas, univariate marginal distribution algorithm, umda |
21 | Kwangok Jeong, Andrew B. Kahng, Hailong Yao |
Revisiting the linear programming framework for leakage power vs. performance optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 127-134, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Ashish Srivastava, Kaviraj Chopra, Saumil Shah, Dennis Sylvester, David T. Blaauw |
A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(2), pp. 272-285, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Andrew B. Kahng, Sudhakar Muddu, Puneet Sharma |
Defocus-Aware Leakage Estimation and Control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(2), pp. 230-240, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Josef Haid, Bernd Zimek, Thomas Leutgeb, Thomas Künemund |
Impact of Leakage Current on Data Retention of RF-powered Devices During Amplitude-Modulation-based Communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 784-787, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Vinay Agarwal, Sameer R. Sonkusale |
A PVT independent subthreshold constant-Gm stage for very low frequency applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 2909-2912, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin |
Substrate Noise Reduction Based On Noise Aware Cell Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3227-3230, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Guochen Hua, Meng Wang 0005, Zili Shao, Hui Liu 0006, Chun Xue |
Real-Time Loop Scheduling with Energy Optimization Via DVS and ABB for Multi-core Embedded System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC ![In: Embedded and Ubiquitous Computing, International Conference, EUC 2007, Taipei, Taiwan, December 17-20, 2007, Proceedings, pp. 1-12, 2007, Springer, 978-3-540-77091-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Günther R. Raidl, Gabriele Koller, Bryant A. Julstrom |
Biased Mutation Operators for Subgraph-Selection Problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Evol. Comput. ![In: IEEE Trans. Evol. Comput. 10(2), pp. 145-156, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Tianbin Wo, Peter Adam Hoeher, Ansgar Scherb, Karl-Dirk Kammeyer |
Performance Analysis of Maximum-Likelihood Semiblind Estimation of MIMO Channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTC Spring ![In: Proceedings of the 63rd IEEE Vehicular Technology Conference, VTC Spring 2006, 7-10 May 2006, Melbourne, Australia, pp. 1738-1742, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Dan Kamosny, Vit Novotyny, Miroslav Balík |
Bandwidth Redistribution Algorithm for Single Source Multicast. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICN/ICONS/MCL ![In: Fifth International Conference on Networking and the International Conference on Systems (ICN / ICONS / MCL 2006), 23-29 April 2006, Mauritius, pp. 147, 2006, IEEE Computer Society, 0-7695-2552-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Xian Ping Fan, Pak Kwong Chan |
Improving Source-Follower Buffer for High-Speed ADC Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 21-24, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Andrew B. Kahng, Swamy Muddu, Puneet Sharma |
Defocus-aware leakage estimation and control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 263-268, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
ACLV, yield, leakage, lithography |
21 | Philomena C. Brady, Paul E. Hasler |
Offset compensation in flash ADCs using floating-gate circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 6154-6157, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Xiaohui Cui, C. Tim Hardin, Rammohan K. Ragade, Adel Said Elmaghraby |
A Swarm Approach for Emission Sources Localization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICTAI ![In: 16th IEEE International Conference on Tools with Artificial Intelligence (ICTAI 2004), 15-17 November 2004, Boca Raton, FL, USA, pp. 424-430, 2004, IEEE Computer Society, 0-7695-2236-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
21 | S. V. Gopalaiah, A. P. Shivaprasad |
Low Voltage CMOS op-amp with Rail-to-Rail Input/Output Swing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 2nd IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2004), 28-30 January 2004, Perth, Australia, pp. 349-354, 2004, IEEE Computer Society, 0-7695-2081-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
21 | Daniela De Venuto, Michael J. Ohletz |
On-Chip Test for Mixed-Signal ASICs using Two-Mode Comparators with Bias-Programmable Reference Voltages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 17(3-4), pp. 243-253, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
mixed-signal ASIC, hardware conversion, GO/NOGO test, bias programming, DfT, power consumption, overhead |
21 | Tommy Kwong-Kin Tsang, Mourad N. El-Gamal |
A fully integrated 1 V 5.8 GHz bipolar LNA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 842-845, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
21 | Damon S. Love, Sudhakar Yalamanchili, José Duato, María Blanca Caminero, Francisco J. Quiles 0001 |
Switch Scheduling in the Multimedia Router (MMR). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), Cancun, Mexico, May 1-5, 2000, pp. 5-12, 2000, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Quality of Service (QoS), Multimedia traffic, Router architecture, Switch scheduling |
21 | Yu-Chuan Shih, Chung-Yu Wu |
The design of high-performance 128×128 CMOS image sensors using new current-readout techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 168-171, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
21 | Ashok K. Chandra, Vijay S. Iyengar, D. Jameson, R. V. Jawalekar, Indira Nair, Barry K. Rosen, Michael P. Mullen, J. Yoon, R. Armoni, Daniel Geist, Yaron Wolfsthal |
AVPGEN-A test generator for architecture verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 3(2), pp. 188-200, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
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