Search results for "charge-recycling"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
118	Kimish Patel, Wonbok Lee, Massoud Pedram	In-order pulsed charge recycling in off-chip data buses.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	data buses, power, charge recycling
100	Keejong Kim, Chris H. Kim, Kaushik Roy 0001	TFT-LCD Application Specific Low Power SRAM Using Charge-Recycling Technique.	ISQED	2005	DBLP DOI BibTeX RDF
100	Byung-Do Yang, Lee-Sup Kim	A low-power charge-recycling ROM architecture.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
87	Keejong Kim, Hamid Mahmoodi, Kaushik Roy 0001	A low-power SRAM using bit-line charge-recycling technique.	ISLPED	2007	DBLP DOI BibTeX RDF	write margin, write power, low power, process variation, SRAM, charge-recycling
87	Zhiyu Liu, Volkan Kursun	Charge Recycling Between Virtual Power and Ground Lines for Low Energy MTCMOS.	ISQED	2007	DBLP DOI BibTeX RDF	Multi-threshold voltage CMOS, gated power, gated ground, sleep switch, subthreshold leakage, charge recycling
81	Ehsan Pakbaznia, Farzan Fallah, Massoud Pedram	Sizing and placement of charge recycling transistors in MTCMOS circuits.	ICCAD	2007	DBLP DOI BibTeX RDF
80	Ehsan Pakbaznia, Farzan Fallah, Massoud Pedram	Charge recycling in MTCMOS circuits: concept and analysis.	DAC	2006	DBLP DOI BibTeX RDF	low power design, MTCMOS, charge recycling
69	Ka-Ming Keung, Akhilesh Tyagi	SRAM CP: A Charge Recycling Design Schema for SRAM.	PATMOS	2006	DBLP DOI BibTeX RDF
68	Seung-Moon Yoo, Sung-Mo Kang	CMOS Pass-gate No-race Charge-recycling Logic (CPNCL).	ISCAS (1)	1999	DBLP DOI BibTeX RDF
62	Ali Abbasian, S. H. Rasouli, Ali Afzali-Kusha, Mehrdad Nourani	No-race charge recycling complementary pass transistor logic (NCRCPL) for low power applications.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
62	Byung-Do Yang, Lee-Sup Kim	A low power charge-recycling ROM architecture.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
62	Xiaohui Wang, Wolfgang Porod	A Low Power Charge-Recycling CMOS Clock Buffer.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
62	Seung-Moon Yoo, Sung-Mo Kang	No-Race Charge-Recycling Differential Logic (NCDL).	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
56	Jouko Marjonen, Markku Åberg	A Single Clocked Adiabatic Static Logic - A Proposal for Digital Low Power Applications.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	sinisoidal power source, non-existing DC-path, load capacitance, LC-oscillator, charge recycling
49	Zhiyu Liu, Volkan Kursun	Charge Recycling MTCMOS for Low Energy Active/Sleep Mode Transitions.	ISCAS	2007	DBLP DOI BibTeX RDF
45	Shao-Sheng Yang, Pao-Lin Guo, Tsin-Yuan Chang, Jin-Hua Hong	A multi-phase charge-sharing technique without external capacitor for low-power TFT-LCD column drivers.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
43	Masayuki Kitamura, Masaaki Iijima, Kenji Hamada, Masahiro Numa, Hiromi Notani, Akira Tada, Shigeto Maegawa	High Performance CMOS Circuit by Using Charge Recycling Active Body-Bias Controlled SOI.	PATMOS	2006	DBLP DOI BibTeX RDF
43	Peter Celinski, Derek Abbott, Sorin Dan Cotofana	Area efficient, high speed parallel counter circuits using charge recycling threshold logic.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
43	Peter Celinski, Said F. Al-Sarawi, Derek Abbott, José Francisco López	Low depth carry lookahead addition using charge recycling threshold logic.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
39	Dan Li, Tingcun Wei, Wei Wu	A novel charge recycler for TFT-LCD source driver IC.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	dot-inversion, source driver, space correlation, time correlation, TFT-LCD, charge recycler
38	K. Y. Cheung	CRRDL: a novel charge recovery-recycling differential logic.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
34	Keonhee Cho, Giseok Kim, Ji Sang Oh, Ki-Ryong Kim, Changsu Sim, Younmee Bae, Mijung Kim, Sangyeop Baeck, Taejoong Song, Seong-Ook Jung	A 14-nm Low Voltage SRAM with Charge-Recycling and Charge Self-Saving Techniques for Low-Power Applications.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
34	Hui Peng, Herbert De Pauw, Pieter Bauwens, Jan Doutreloigne	A high-efficiency charge pump with charge recycling scheme and finger boost capacitor.	Integr.	2020	DBLP DOI BibTeX RDF
34	Hui Peng, Pieter Bauwens, Herbert De Pauw, Jan Doutreloigne	Implementation of a 16-Phase 8-Branch Charge Pump with Advanced Charge Recycling Strategy.	IEICE Trans. Electron.	2020	DBLP DOI BibTeX RDF
34	Ka-Ming Keung, Vineela Manne, Akhilesh Tyagi	A Novel Charge Recycling Design Scheme Based on Adiabatic Charge Pump.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
34	Byung-Do Yang, Lee-Sup Kim	A low-power ROM using charge recycling and charge sharing techniques.	IEEE J. Solid State Circuits	2003	DBLP DOI BibTeX RDF
34	Vineela Manne, Akhilesh Tyagi	An Adiabatic Charge Pump Based Charge Recycling Design Style.	PATMOS	2003	DBLP DOI BibTeX RDF
24	Han Wu 0003, Jeong Hoan Park, Rucheng Jiang, Jung-Hwan Choi, Jerald Yoo	A Charge Recycling Logic Data Links for Single- and Multiple-Channel I/Os.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
24	Sang-Hoon Kim, Yongsung Cho, Jiwon Lee, Jung-Hoon Chun, Jaehyuk Choi 0001	A 2.03-mW CMOS Image Sensor With an Integrated Four-Stacked Charge-Recycling Driver for Image Signal Transmission.	IEEE Access	2022	DBLP DOI BibTeX RDF
24	Qurat Ul Ain, Danial Khan, Muhammad Basim, SeongJin Oh, Khuram Shehzad, Byeong Gi Jang, Syed Adil Ali Shah, JongWan Jo, YoungGun Pu, Keum-Cheol Hwang, Youngoo Yang, Kang-Yoon Lee	A High-Efficiency Triple-Mode Active Rectifier With Gate Charge Recycling Technique for Wireless Power Transfer System.	IEEE Access	2022	DBLP DOI BibTeX RDF
24	Cece Huang, Fei Liu, Qianqian Wang, Zongliang Huo	Low Power Program Scheme With Capacitance-Less Charge Recycling for 3D NAND Flash Memory.	IEEE Trans. Circuits Syst. II Express Briefs	2021	DBLP DOI BibTeX RDF
24	Jonas Pelgrims, Kris Myny, Wim Dehaene	A 36V Ultrasonic Driver for Haptic Feedback Using Advanced Charge Recycling Achieving 0.20CV2f Power Consumption.	ESSDERC	2021	DBLP DOI BibTeX RDF
24	Jonas Pelgrims, Kris Myny, Wim Dehaene	A 36V Ultrasonic Driver for Haptic Feedback Using Advanced Charge Recycling Achieving 0.20CV2f Power Consumption.	ESSCIRC	2021	DBLP DOI BibTeX RDF
24	Abdullah Abdulslam, Patrick P. Mercier	17.5 A 98.2%-Efficiency Reciprocal Direct Charge Recycling Inductor-First DC-DC Converter.	ISSCC	2021	DBLP DOI BibTeX RDF
24	Takefumi Yoshikawa, Tatsuya Iwata, Junji Shibazaki, Sho Muroga, Hiroaki Ikeda	A charge recycling stacked I/O in standard CMOS technology for wide TSV data bus.	IEICE Electron. Express	2020	DBLP DOI BibTeX RDF
24	Hanwool Jeong, Se Hyeok Oh, Tae Woo Oh, Hoonki Kim, Changnam Park, Woojin Rim, Taejoong Song, Seong-Ook Jung	Bitline Charge-Recycling SRAM Write Assist Circuitry for $V_{\mathrm{MIN}}$ Improvement and Energy Saving.	IEEE J. Solid State Circuits	2019	DBLP DOI BibTeX RDF
24	Yaqub Mahnashi, Fang Z. Peng	A Monolithic Voltage-Scalable Fibonacci Switched-Capacitor DC-DC Converter With Intrinsic Parasitic Charge Recycling.	IEEE Trans. Very Large Scale Integr. Syst.	2019	DBLP DOI BibTeX RDF
24	Gyuseong Kang, Jongsun Park 0001	Charge-Recycling-Based Redundant Write Prevention Technique for Low-Power SOT-MRAM.	IEEE Trans. Very Large Scale Integr. Syst.	2019	DBLP DOI BibTeX RDF
24	Jihee Lee, Kyoung-Rog Lee, Benjamin E. Eovino, Jeong Hoan Park, Liwei Lin, Hoi-Jun Yoo, Jerald Yoo	A 5.37mW/Channel Pitch-Matched Ultrasound ASIC with Dynamic-Bit-Shared SAR ADC and 13.2V Charge-Recycling TX in Standard CMOS for Intracardiac Echocardiography.	ISSCC	2019	DBLP DOI BibTeX RDF
24	Meysam Akbari, Omid Hashemipour, Fabian Khateb, Farshad Moradi	An energy-efficient DAC switching algorithm based on charge recycling method for SAR ADCs.	Microelectron. J.	2018	DBLP DOI BibTeX RDF
24	José C. García 0001, Juan A. Montiel-Nelson, Saeid Nooshabadi	Low Swing Charge Recycling Driver for On-Chip Interconnect.	J. Low Power Electron.	2018	DBLP DOI BibTeX RDF
24	Gyuseong Kang, Yunho Jang, Jongsun Park 0001	Charge-Recycling based Redundant Write Prevention Technique for Low Power SOT-MRAM.	ISCAS	2018	DBLP DOI BibTeX RDF
24	An Zou, Jingwen Leng, Xin He, Yazhou Zu, Vijay Janapa Reddi, Xuan Zhang 0001	Efficient and reliable power delivery in voltage-stacked manycore system with hybrid charge-recycling regulators.	DAC	2018	DBLP DOI BibTeX RDF
24	Kristof Blutman, Ajay Kapoor, Arjun Majumdar, Jacinto Garcia Martinez, Juan Diego Echeverri, Leo Sevat, Arnoud P. van der Wel, Hamed Fatemi, Kofi A. A. Makinwa, José Pineda de Gyvez	A Low-Power Microcontroller in a 40-nm CMOS Using Charge Recycling.	IEEE J. Solid State Circuits	2017	DBLP DOI BibTeX RDF
24	Jung-Woo Ha 0002, Byung-Ha Park, Jung-Hoon Chun	A 7-MHz Integrated Peak-Current-Mode Buck Regulator With a Charge-Recycling Technique.	IEEE Trans. Circuits Syst. II Express Briefs	2017	DBLP DOI BibTeX RDF
24	Jinhui Wang, Na Gong, Eby G. Friedman	PNS-FCR: Flexible Charge Recycling Dynamic Circuit Technique for Low-Power Microprocessors.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
24	Woong Choi, Jongsun Park 0001	A Charge-Recycling Assist Technique for Reliable and Low Power SRAM Design.	IEEE Trans. Circuits Syst. I Regul. Pap.	2016	DBLP DOI BibTeX RDF
24	Pablo Castro-Lisboa, Pablo Perez-Nicoli, Francisco Veirano, Fernando Silveira	General Top/Bottom-Plate Charge Recycling Technique for Integrated Switched Capacitor DC-DC Converters.	IEEE Trans. Circuits Syst. I Regul. Pap.	2016	DBLP DOI BibTeX RDF
24	John M. Wilson 0002, Matthew R. Fojtik, John W. Poulton, Xi Chen 0033, Stephen G. Tell, Thomas H. Greer, C. Thomas Gray, William J. Dally	8.6 A 6.5-to-23.3fJ/b/mm balanced charge-recycling bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with clock forwarding and low-crosstalk contraflow wiring.	ISSCC	2016	DBLP DOI BibTeX RDF
24	Tutu Wan, Emre Salman, Milutin Stanacevic	A new circuit design framework for IoT devices: Charge-recycling with wireless power harvesting.	ISCAS	2016	DBLP DOI BibTeX RDF
24	Lei Sun, Bing Li, Alex K. Y. Wong, Wai Tung Ng, Kong-Pang Pun	A Charge Recycling SAR ADC With a LSB-Down Switching Scheme.	IEEE Trans. Circuits Syst. I Regul. Pap.	2015	DBLP DOI BibTeX RDF
24	Seokhyeon Jeong, Wanyeong Jung, Dongsuk Jeon, Omer Berenfeld, Hakan Oral, Grant H. Kruger, David T. Blaauw, Dennis Sylvester	A 120nW 8b sub-ranging SAR ADC with signal-dependent charge recycling for biomedical applications.	VLSIC	2015	DBLP DOI BibTeX RDF
24	Kai-Hsiang Chiang, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin	A 10b 100kS/s SAR ADC with charge recycling switching method.	A-SSCC	2014	DBLP DOI BibTeX RDF
24	Kazuhiro Ueda, Fukashi Morishita, Shunsuke Okura, Leona Okamura, Tsutomu Yoshihara, Kazutami Arimoto	Low-Power On-Chip Charge-Recycling DC-DC Conversion Circuit and System.	IEEE J. Solid State Circuits	2013	DBLP DOI BibTeX RDF
24	Safeen Huda, Jason Helge Anderson, Hirotaka Tamura	Charge recycling for power reduction in FPGA interconnect.	FPL	2013	DBLP DOI BibTeX RDF
24	Tao Tong, Xuan Zhang 0001, Wonyoung Kim, David M. Brooks, Gu-Yeon Wei	A fully integrated battery-connected switched-capacitor 4: 1 voltage regulator with 70% peak efficiency using bottom-plate charge recycling.	CICC	2013	DBLP DOI BibTeX RDF
24	Yong Liu 0023, Ping-Hsuan Hsieh, Seongwon Kim, Jae-sun Seo, Robert K. Montoye, Leland Chang, José A. Tierno, Daniel J. Friedman	A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI.	ISSCC	2013	DBLP DOI BibTeX RDF
24	Kiichi Niitsu, Shusuke Kawai, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda	A 65fJ/b Inter-Chip Inductive-Coupling Data Transceivers Using Charge-Recycling Technique for Low-Power Inter-Chip Communication in 3-D System Integration.	IEEE Trans. Very Large Scale Integr. Syst.	2012	DBLP DOI BibTeX RDF
24	Guanzhong Huang, Pingfen Lin	A 15fJ/conversion-step 8-bit 50 MS/s asynchronous SAR ADC with efficient charge recycling technique.	Microelectron. J.	2012	DBLP DOI BibTeX RDF
24	Shunji Nakata, Ryota Honda, Hiroshi Makino, Shin'ichiro Mutoh, Masayuki Miyama, Yoshio Matsuda	General Stability of Stepwise Waveform of an Adiabatic Charge Recycling Circuit With Any Circuit Topology.	IEEE Trans. Circuits Syst. I Regul. Pap.	2012	DBLP DOI BibTeX RDF
24	Byung-Do Yang	A High-Efficiency On-Chip DC-DC Down-Conversion Using Selectable Supply-Voltage Charge-Recycling.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2011	DBLP DOI BibTeX RDF
24	Xu Wang, Jianfei Jiang 0001, Zhi-Gang Mao, Bingjing Ge, Xinglong Zhao	A novel low power 64-kb SRAM using bit-lines charge-recycling and non-uniform cell scheme.	ICECS	2011	DBLP DOI BibTeX RDF
24	Byung-Do Yang	A Low-Power SRAM Using Bit-Line Charge-Recycling for Read and Write Operations.	IEEE J. Solid State Circuits	2010	DBLP DOI BibTeX RDF
24	Katsumi Dosaka, Daisuke Ogawa, Takahito Kusumoto, Masayuki Miyama, Yoshio Matsuda	A Complete Charge Recycling TCAM with Checkerboard Array Arrangement for Low Power Applications.	IEICE Trans. Electron.	2010	DBLP DOI BibTeX RDF
24	Thomas Schweizer, Julio A. de Oliveira Filho, Tommy Kuhn, Wolfgang Rosenstiel	Charge Recycling in Voltage-Dithered Circuits.	J. Low Power Electron.	2010	DBLP DOI BibTeX RDF
24	Chun-Yu Hsieh, Ke-Horng Chen	Boost DC-DC Converter With Fast Reference Tracking (FRT) and Charge-Recycling (CR) Techniques for High-Efficiency and Low-Cost LED Driver.	IEEE J. Solid State Circuits	2009	DBLP DOI BibTeX RDF
24	Jose Carlos Garcia-Montesdeoca, Juan A. Montiel-Nelson, Saeid Nooshabadi	High Performance CMOS 2-input NAND Based on Low-race Split-level Charge-recycling Pass-transistor Logic.	DSD	2009	DBLP DOI BibTeX RDF
24	Jianwei Zhang 0006, Yizheng Ye, Bin-Da Liu, Feng Guan	Self-timed Charge Recycling Search-line Drivers in Content-addressable Memories.	ISCAS	2009	DBLP DOI BibTeX RDF
24	Keejong Kim, Hamid Mahmoodi, Kaushik Roy 0001	A Low-Power SRAM Using Bit-Line Charge-Recycling.	IEEE J. Solid State Circuits	2008	DBLP DOI BibTeX RDF
24	Ehsan Pakbaznia, Farzan Fallah, Massoud Pedram	Charge Recycling in Power-Gated CMOS Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
24	Yan Zhu 0001, U. Fat Chio, He Gong Wei, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins	A power-efficient capacitor structure for high-speed charge recycling SAR ADCs.	ICECS	2008	DBLP DOI BibTeX RDF
24	Chun-Yu Hsieh, Ke-Horng Chen	Boost DC-DC converter with charge-recycling (CR) and fast reference tracking (FRT) techniques for high-efficiency and low-cost LED driver.	ESSCIRC	2008	DBLP DOI BibTeX RDF
24	Kim Hardee, Michael Parris, O. Fred Jones, Doug Butler, Mike Mound, G. W. Jones, Tim Egging, Tomofumi Arakawa, Katsuhiko Sasahara, Kazuo Taniguchi, Masayuki Miyabayashi	A 170GB/s 16Mb Embedded DRAM with Data-Bus Charge-Recycling.	ISSCC	2008	DBLP DOI BibTeX RDF
24	Akira Tada, Hiromi Notani, Genichi Tanaka, Takashi Ipposhi, Masaaki Iijima, Masahiro Numa	Charge recycling in MTCMOS circuits with block dividing.	IEICE Electron. Express	2007	DBLP DOI BibTeX RDF
24	Rafal Karakiewicz, Roman Genov, Gert Cauwenberghs	1.1 TMACS/mW Load-Balanced Resonant Charge-Recycling Array Processor.	CICC	2007	DBLP DOI BibTeX RDF
24	Mehdi Alimadadi, Samad Sheikhaei, Guy Lemieux, Shahriar Mirabbasi, Patrick R. Palmer	A 3GHz Switching DC-DC Converter Using Clock-Tree Charge-Recycling in 90nm CMOS with Integrated Output Filter.	ISSCC	2007	DBLP DOI BibTeX RDF
24	Saravanan Rajapandian, Kenneth L. Shepard, Peter Hazucha, Tanay Karnik	High-voltage power delivery through charge recycling.	IEEE J. Solid State Circuits	2006	DBLP DOI BibTeX RDF
24	Akira Tada, Hiromi Notani, Masahiro Numa	A novel power gating scheme with charge recycling.	IEICE Electron. Express	2006	DBLP DOI BibTeX RDF
24	Saravanan Rajapandian, Zheng Xu 0003, Kenneth L. Shepard	Implicit DC-DC downconversion through charge-recycling.	IEEE J. Solid State Circuits	2005	DBLP DOI BibTeX RDF
24	Byung-Do Yang, Lee-Sup Kim	A low-power CAM using pulsed NAND-NOR match-line and charge-recycling search-line driver.	IEEE J. Solid State Circuits	2005	DBLP DOI BibTeX RDF
24	Brian P. Ginsburg, Anantha P. Chandrakasan	An energy-efficient charge recycling approach for a SAR converter with capacitive DAC.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
24	Kris Tiri, Ingrid Verbauwhede	Charge Recycling Sense Amplifier Based Logic: Securing Low Power Security IC's against Differential Power Analysis.	IACR Cryptol. ePrint Arch.	2004	DBLP BibTeX RDF
24	Kris Tiri, Ingrid Verbauwhede	Charge recycling sense amplifier based logic: securing low power security ICs against DPA [differential power analysis].	ESSCIRC	2004	DBLP DOI BibTeX RDF
24	Ali Abbasian, Ali Afzali-Kusha	Pipeline Event-driven No-race Charge recycling Logic (PENCL) for low power application.	ICECS	2003	DBLP DOI BibTeX RDF
24	Yiorgos Tsiatouhas, Konstantinos Limniotis, Angela Arapoyanni, Themistoklis Haniotakis	A low power NORA circuit design technique based on charge recycling.	ICECS	2003	DBLP DOI BibTeX RDF
24	Saravanan Rajapandian, Zheng Xu 0003, Kenneth L. Shepard	Charge-Recycling Voltage Domains for Energy-Efficient Low-Voltage Operation of Digital CMOS Circuits.	ICCD	2003	DBLP DOI BibTeX RDF
24	Jungho Lee, Joonbae Park, Byungjoon Song, Wonchan Kim	Split-level precharge differential logic: a new type of high-speed charge-recycling differential logic.	IEEE J. Solid State Circuits	2001	DBLP DOI BibTeX RDF
24	Paul-Peter Sotiriadis, Theodoros Konstantakopoulos, Anantha P. Chandrakasan	Analysis and implementation of charge recycling for deep sub-micron buses.	ISLPED	2001	DBLP DOI BibTeX RDF
24	Jong-Seok Kim, Deog-Kyoon Jeong, Gyudong Kim	A multi-level multi-phase charge-recycling method for low-power AMLCD column drivers.	IEEE J. Solid State Circuits	2000	DBLP DOI BibTeX RDF
24	Ilias Bouras, Yiannis Liaperdos, Angela Arapoyanni	A high speed low power CMOS clock driver using charge recycling technique.	ISCAS	2000	DBLP DOI BibTeX RDF
24	Nobutaro Shibata, Hiroki Morimura, Mayumi Watanabe	A 1-V, 10-MHz, 3.5-mW, 1-Mb MTCMOS SRAM: with charge-recycling input/output buffers.	IEEE J. Solid State Circuits	1999	DBLP DOI BibTeX RDF
24	Spiridon Nikolaidis 0001, Efstathios D. Kyriakis-Bitzaros	A Charge Recycling Technique for the Design of Low Power CMOS Clock Drivers.	J. Circuits Syst. Comput.	1999	DBLP DOI BibTeX RDF
24	Bai-Sun Kong, Joo-Sun Choi, Seog-Jun Lee, Kwyro Lee	Charge recycling differential logic (CRDL) for low power application.	IEEE J. Solid State Circuits	1996	DBLP DOI BibTeX RDF
24	Hiroyuki Yamauchi, Hironori Akamatsu, Tsutomu Fujita	An asymptotically zero power charge-recycling bus architecture for battery-operated ultrahigh data rate ULSI's.	IEEE J. Solid State Circuits	1995	DBLP DOI BibTeX RDF
19	Peter Celinski, Derek Abbott, Sorin Cotofana	Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic.	PATMOS	2004	DBLP DOI BibTeX RDF
19	Peter Celinski, Said F. Al-Sarawi, Derek Abbott, Sorin Cotofana, Stamatis Vassiliadis	Logical Effort Based Design Exploration of 64-bit Adders Using a Mixed Dynamic-CMOS/Threshold-Logic Approach.	ISVLSI	2004	DBLP DOI BibTeX RDF
19	Hongchin Lin, Yi-Fan Chen, Hsien-Chih She	A low-power 3-phase half rail pass-gate differential logic.	ISCAS (4)	2001	DBLP DOI BibTeX RDF