Search results for "chip-multiprocessing"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
69	Per Stenström	Chip-multiprocessing and beyond.	HPCA	2006	DBLP DOI BibTeX RDF
69	Luiz André Barroso, Kourosh Gharachorloo, Robert McNamara, Andreas Nowatzyk, Shaz Qadeer, Barton Sano, Scott Smith, Robert Stets, Ben Verghese	Piranha: a scalable architecture based on single-chip multiprocessing.	ISCA	2000	DBLP DOI BibTeX RDF
64	Michael Gschwind	Chip multiprocessing and the cell broadband engine.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	compute-transfer parallelism (CTP), cell broadband engine, memory-level parallelism (MLP), chip multiprocessing, heterogeneous chip multiprocessor
47	Ismail Kadayif, Mahmut T. Kandemir, Ibrahim Kolcu	Exploiting Processor Workload Heterogeneity for Reducing Energy Consumption in Chip Multiprocessors.	DATE	2004	DBLP DOI BibTeX RDF
45	Rakesh Kumar 0002, Norman P. Jouppi, Dean M. Tullsen	Conjoined-Core Chip Multiprocessing.	MICRO	2004	DBLP DOI BibTeX RDF
42	Gianfranco Bilardi, Andrea Pietracaprina, Geppino Pucci, Sebastiano Fabio Schifano, Raffaele Tripiccione	The Potential of On-Chip Multiprocessing for QCD Machines.	HiPC	2005	DBLP DOI BibTeX RDF
42	James Laudon, Lawrence Spracklen	The Coming Wave of Multithreaded Chip Multiprocessors.	Int. J. Parallel Program.	2007	DBLP DOI BibTeX RDF	performance, parallel programming, multithreading, Chip multiprocessing
42	J. Gregory Steffan, Christopher B. Colohan, Antonia Zhai, Todd C. Mowry	The STAMPede approach to thread-level speculation.	ACM Trans. Comput. Syst.	2005	DBLP DOI BibTeX RDF	cache coherence, automatic parallelization, Thread-level speculation, chip-multiprocessing
41	Qingying Deng, Minxuan Zhang, Jiang Jiang	A Parallel Infrastructure on Dynamic EPIC SMT.	ICA3PP	2007	DBLP DOI BibTeX RDF
38	Annie P. Foong, Gary L. McAlpine, Dave B. Minturn, Greg J. Regnier, Vikram A. Saletore	An Architecture for Software-Based iSCSI: Experiences and Analyses.	NETWORKING	2005	DBLP DOI BibTeX RDF	Asymmetric Multiprocessing, TCP optimization, iSCSI
32	Yuxing Tang, Kun Deng, Xingming Zhou	The Design Space of CMP vs. SMT for High Performance Embedded Processor.	ICESS	2005	DBLP DOI BibTeX RDF
29	Tomasz Madajczak, Henryk Krawczyk	Integrating SHECS-Based Critical Sections with Hardware SMP Scheduler in TLP-CMPs.	PARELEC	2006	DBLP DOI BibTeX RDF
26	David K. Tam, Reza Azimi, Michael Stumm	Thread clustering: sharing-aware scheduling on SMP-CMP-SMT multiprocessors.	EuroSys	2007	DBLP DOI BibTeX RDF	cache behavior, detecting sharing, performance monitoring unit, single-chip multiprocessors, thread placement, resource allocation, CMP, multithreading, sharing, SMP, simultaneous multithreading, SMT, shared caches, cache locality, thread scheduling, thread migration, hardware performance monitors, hardware performance counters, affinity scheduling
26	Xiaofeng Guo, Jinquan Dai, Long Li, Zhiyuan Lv, Prashant R. Chandra	Latency Hiding in Multi-Threading and Multi-Processing of Network Applications.	PACT	2007	DBLP DOI BibTeX RDF
25	Eberle A. Rambo, Olav P. Henschel, Luiz C. V. dos Santos	On ESL verification of memory consistency for system-on-chip multiprocessing.	DATE	2012	DBLP DOI BibTeX RDF
25	Simone Campanoni, Timothy M. Jones 0001, Glenn H. Holloway, Vijay Janapa Reddi, Gu-Yeon Wei, David M. Brooks	HELIX: automatic parallelization of irregular programs for chip multiprocessing.	CGO	2012	DBLP DOI BibTeX RDF
25	Wolfgang Puffitsch, Martin Schoeberl	On the scalability of time-predictable chip-multiprocessing.	JTRES	2012	DBLP DOI BibTeX RDF
25	Eberle A. Rambo, Olav P. Henschel, Luiz C. V. dos Santos	Automatic generation of memory consistency tests for chip multiprocessing.	ICECS	2011	DBLP DOI BibTeX RDF
25	Nikita Nikitin, Satrajit Chatterjee, Jordi Cortadella, Michael Kishinevsky, Ümit Y. Ogras	Physical-Aware Link Allocation and Route Assignment for Chip Multiprocessing.	NOCS	2010	DBLP DOI BibTeX RDF
25	Martin Schoeberl, Peter P. Puschner	Is Chip-Multiprocessing the End of Real-Time Scheduling?.	WCET	2009	DBLP BibTeX RDF
25	Kazutoshi Kobayashi, Masao Aramoto, Hidetoshi Onodera	A Resource-Shared VLIW Processor for Low-Power On-Chip Multiprocessing in the Nanometer Era.	IEICE Trans. Electron.	2005	DBLP DOI BibTeX RDF
25	Kazutoshi Kobayashi, Masao Aramoto, Yoichi Yuyama, Akihiko Higuchi, Hidetoshi Onodera	A resource-shared VLIW processor architecture for area-efficient on-chip multiprocessing.	ASP-DAC	2005	DBLP DOI BibTeX RDF
25	Per Stenström	The Chip-Multiprocessing Paradigm Shift: Opportunities and Challenges.	HiPEAC	2005	DBLP DOI BibTeX RDF
25	Bernard Goossens, Duc Thang Vu	On-Chip Multiprocessing.	Euro-Par, Vol. II	1996	DBLP DOI BibTeX RDF
23	Feihui Li, Chrysostomos Nicopoulos, Thomas D. Richardson, Yuan Xie 0001, Narayanan Vijaykrishnan, Mahmut T. Kandemir	Design and Management of 3D Chip Multiprocessors Using Network-in-Memory.	ISCA	2006	DBLP DOI BibTeX RDF
22	Guochun Shi, Volodymyr V. Kindratenko, Frederico Pratas, Pedro Trancoso, Michael Gschwind	Application Acceleration with the Cell Broadband Engine.	Comput. Sci. Eng.	2010	DBLP DOI BibTeX RDF	PowerXCell 8i processor, chip architecture, data-intensive application architectures, compute-intensive processing, Cell Broadband Engine, chip multiprocessing
22	Christopher B. Colohan, Anastassia Ailamaki, J. Gregory Steffan, Todd C. Mowry	Incrementally parallelizing database transactions with thread-level speculation.	ACM Trans. Comput. Syst.	2008	DBLP DOI BibTeX RDF	incremental parallelization, Thread-level speculation, chip-multiprocessing, optimistic concurrency
22	Antonia Zhai, J. Gregory Steffan, Christopher B. Colohan, Todd C. Mowry	Compiler and hardware support for reducing the synchronization of speculative threads.	ACM Trans. Archit. Code Optim.	2008	DBLP DOI BibTeX RDF	automatic parallelization, instruction scheduling, Thread-level speculation, chip-multiprocessing
22	Guangyu Chen, Feihui Li, Seung Woo Son 0001, Mahmut T. Kandemir	Application mapping for chip multiprocessors.	DAC	2008	DBLP DOI BibTeX RDF	NoC (Network on Chip), compilers, power optimization, chip multiprocessing, application mapping
22	Ozcan Ozturk 0001, Guilin Chen, Mahmut T. Kandemir	Optimizing code parallelization through a constraint network based approach.	DAC	2006	DBLP DOI BibTeX RDF	compiler, constraint network, chip multiprocessing
22	Jason Cong, Ashok Jagannathan, Glenn Reinman, Yuval Tamir	Understanding the energy efficiency of SMT and CMP with multiclustering.	ISLPED	2005	DBLP DOI BibTeX RDF	energy efficiency, simultaneous multithreading, chip multiprocessing
20	Christof Pitter, Martin Schoeberl	Performance evaluation of a java chip-multiprocessor.	SIES	2008	DBLP DOI BibTeX RDF
20	Lawrence Spracklen, Santosh G. Abraham	Chip Multithreading: Opportunities and Challenges.	HPCA	2005	DBLP DOI BibTeX RDF
20	Björn Jäger, Jörg-Christian Niemann, Ulrich Rückert 0001	Analytical approach to massively parallel architectures for nanotechnologies.	ASAP	2005	DBLP DOI BibTeX RDF
20	Mahmut T. Kandemir, Wei Zhang 0002, Mustafa Karaköy	Runtime Code Parallelization for On-Chip Multiprocessors.	DATE	2003	DBLP DOI BibTeX RDF
18	Christof Pitter, Martin Schoeberl	Towards a Java multiprocessor.	JTRES	2007	DBLP DOI BibTeX RDF	Java, multiprocessor, shared memory
18	Xiaofang Wang, Sotirios G. Ziavras	Performance-Energy Tradeoffs for Matrix Multiplication on FPGA-Based Mixed-Mode Chip Multiprocessors.	ISQED	2007	DBLP DOI BibTeX RDF
18	Björn Jäger, Mario Porrmann, Ulrich Rückert 0001	Bio-inspired massively parallel architectures for nanotechnologies.	ISCAS	2006	DBLP DOI BibTeX RDF
18	Yingmin Li, David M. Brooks, Zhigang Hu, Kevin Skadron	Performance, Energy, and Thermal Considerations for SMT and CMP Architectures.	HPCA	2005	DBLP DOI BibTeX RDF
18	Alexandra Fedorova, Christopher Small 0001, Daniel Nussbaum, Margo I. Seltzer	Chip multithreading systems need a new operating system scheduler.	ACM SIGOPS European Workshop	2004	DBLP DOI BibTeX RDF
18	Stefanos Kaxiras, Girija J. Narlikar, Alan D. Berenbaum, Zhigang Hu	Comparing power consumption of an SMT and a CMP DSP for mobile phone workloads.	CASES	2001	DBLP DOI BibTeX RDF
15	Chen-Yong Cher, Michael Gschwind	Cell GC: using the cell synergistic processor as a garbage collection coprocessor.	VEE	2008	DBLP DOI BibTeX RDF	BDW, SPU, explicitly managed memory hierarchies, local store, garbage collection, accelerator, SPE, coprocessor, cell, mark-sweep
15	Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero	MLP-Aware Dynamic Cache Partitioning.	PACT	2007	DBLP DOI BibTeX RDF
15	Christof Pitter, Martin Schoeberl	Time Predictable CPU and DMA Shared Memory Access.	FPL	2007	DBLP DOI BibTeX RDF
15	Dimitrios S. Nikolopoulos	Facing the challenges of multicore processor technologies using autonomic system software.	IPDPS	2006	DBLP DOI BibTeX RDF
15	Luiz André Barroso	The price of performance.	ACM Queue	2005	DBLP DOI BibTeX RDF
15	Jiwei Lu, Abhinav Das, Wei-Chung Hsu, Khoa Nguyen, Santosh G. Abraham	Dynamic Helper Threaded Prefetching on the Sun UltraSPARC CMP Processor.	MICRO	2005	DBLP DOI BibTeX RDF
15	Scott Schneider 0001, Christos D. Antonopoulos, Dimitrios S. Nikolopoulos	Factory: An Object-Oriented Parallel Programming Substrate for Deep Multiprocessors.	HPCC	2005	DBLP DOI BibTeX RDF	Multithreading substrate, Object-oriented parallel programming, Deep parallel architectures, Multiparadigm parallelism, Portability, Programmability
15	Annie P. Foong, Gary L. McAlpine, Dave B. Minturn, Greg J. Regnier, Vikram A. Saletore	An Architecture for Software-Based iSCSI on Multiprocessor Servers.	IPDPS	2005	DBLP DOI BibTeX RDF
15	Ruchira Sasanka, Sarita V. Adve, Yen-Kuang Chen, Eric Debes	The energy efficiency of CMP vs. SMT for multimedia workloads.	ICS	2004	DBLP DOI BibTeX RDF	multimedia, energy efficiency, CMP, SMT