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article(4927) book(19) data(2) incollection(73) inproceedings(16315) phdthesis(271) proceedings(54)
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ICCD(1830) ASAP(1422) IPDPS(503) IEEE Trans. Parallel Distribut...(441) IEEE Trans. Computers(358) CoRR(291) DATE(284) DAC(256) Euro-Par(244) ISCA(240) SC(225) MICRO(214) IEEE Trans. Very Large Scale I...(174) ICS(172) HPCA(161) ICPP(156) More (+10 of total 2222)
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Found 21661 publication records. Showing 21661 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
49Randolph D. Nelson, Donald F. Towsley, Asser N. Tantawi Performance Analysis of Parallel Processing Systems. Search on Bibsonomy SIGMETRICS The full citation details ... 1987 DBLP  DOI  BibTeX  RDF
46Edward H. Bensley, Thomas J. Brando, J. C. Fohlin, Myra Jean Prelle, Ann Wollrath MITRE's future generation computer architectures program. Search on Bibsonomy OOPSLA/ECOOP Workshop on Object-based Concurrent Programming The full citation details ... 1988 DBLP  DOI  BibTeX  RDF
46Michael B. Taylor, Walter Lee, Jason E. Miller, David Wentzlaff, Ian Bratt, Ben Greenwald, Henry Hoffmann, Paul R. Johnson, Jason Sungtae Kim, James Psota, Arvind Saraf, Nathan Shnidman, Volker Strumpen, Matthew I. Frank, Saman P. Amarasinghe, Anant Agarwal Tiled Multicore Processors. Search on Bibsonomy Multicore Processors and Systems The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
46James Laudon, Robert T. Golla, Greg Grohoski Throughput-Oriented Multicore Processors. Search on Bibsonomy Multicore Processors and Systems The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
46Mattan Erez, William J. Dally Stream Processors. Search on Bibsonomy Multicore Processors and Systems The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
46H. Peter Hofstee Heterogeneous Multi-core Processors: The Cell Broadband Engine. Search on Bibsonomy Multicore Processors and Systems The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
46Chuck Moore, Pat Conway General-Purpose Multi-core Processors. Search on Bibsonomy Multicore Processors and Systems The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
46Guido Araujo, Srinivas Devadas, Kurt Keutzer, Stan Y. Liao, Sharad Malik, Ashok Sudarsanam, Steven W. K. Tjiang, Albert R. Wang Challenges in code generation for embedded processors. Search on Bibsonomy Code Generation for Embedded Processors The full citation details ... 1994 DBLP  BibTeX  RDF
46Peter Marwedel Code generation for embedded processors: an introduction. Search on Bibsonomy Code Generation for Embedded Processors The full citation details ... 1994 DBLP  BibTeX  RDF
46Dirk Lanneer, Johan Van Praet, Augusli Kifli, Koen Schoofs, Werner Geurts, Filip Thoen, Gert Goossens Chess: retargetable code generation for embedded DSP processors. Search on Bibsonomy Code Generation for Embedded Processors The full citation details ... 1994 DBLP  BibTeX  RDF
43Pawel Gepner, David L. Fraser, Michal Filip Kowalik Performance Evolution and Power Benefits of Cluster System Utilizing Quad-Core and Dual-Core Intel Xeon Processors. Search on Bibsonomy PPAM The full citation details ... 2007 DBLP  DOI  BibTeX  RDF dual-core processors, quad-core processors, parallel processing, benchmarks, HPC, multi-core processors
43Ruby B. Lee Subword Permutation Instructions for Two-Dimensional Multimedia Processing in MicroSIMD Architectures. Search on Bibsonomy ASAP The full citation details ... 2000 DBLP  DOI  BibTeX  RDF microSIMD, multimedia, microprocessors, computer arithmetic, permutations, processors, digital signal processors, Instruction Set Architecture, fine-grain parallelism, subword parallelism, media processors
43Michael Yang, Ahmed N. Tantawy A design methodology for protocol processors. Search on Bibsonomy FTDCS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF protocol processors, FCS, Fibre Channel Standard, homogeneous multi-processors, single VLSI chip, VHDL macro libraries, VLSI protocol processors, CVDS, Communication VLSI Design System, protocols, asynchronous transfer mode, ATM, multiprocessing systems, communication protocols
42David Sheldon, Rakesh Kumar 0002, Frank Vahid, Dean M. Tullsen, Roman L. Lysecky Conjoining soft-core FPGA processors. Search on Bibsonomy ICCAD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF conjoined processors, parameterized platforms, soft-core processors, FPGAs, customization, tuning
40Seong-Uk Choi, Sung-Soon Park, Myong-Soon Park Scheduling of conditional branches using SSA form for superscalar/VLIW processors. Search on Bibsonomy ICPADS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF conditional branches scheduling, very long instruction word processors, compensation code, optimization, computational complexity, complexity, parallel architectures, processor scheduling, superscalar processors, instruction sets, instruction set, VLIW processors, code motion, global scheduling, conditional branches, SSA
39Anurag Gupta, Ian F. Akyildiz, Richard Fujimoto Performance Analysis of Time Warp With Multiple Homogeneous Processors. Search on Bibsonomy IEEE Trans. Software Eng. The full citation details ... 1991 DBLP  DOI  BibTeX  RDF interacting processors, Time Warp protocol, discrete-state, continuous-time Markov chain model, exponential task times, timestamp increments, event message, negligible rollback, unbounded message buffers, homogeneous processors, processed events, rollback probability, uncommitted processed events, Time Warp testbed, performance evaluation, protocols, discrete event simulation, Markov processes, performance measures, multiprocessing systems, shared-memory multiprocessor, parallel simulation, speedup, communication delay, virtual time, state saving, probability mass function, probability distribution function
39Eric Y. Chou, Bing J. Sheu, Tony H. Wu, Robert C. Chang VLSI design of densely-connected array processors. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF densely-connected array processors, paralleled array processors, real-time signal processing, problem mapping, high potential computational bandwidth, local interconnection, synaptic operators, CNN processing engine, hardware design problems, CNN accelerator design, digital-programmable synapses, flexible digital interface, current-mode CMOS circuits, 2.0 /spl mu/m CMOS technology, edge detection operation, image processing, image processing, parallel processing, VLSI, edge detection, signal processing, VLSI design, heterogeneous computing, CMOS integrated circuits, cellular neural networks, cellular neural nets
38Ali-Reza Adl-Tabatabai, Christos Kozyrakis, Bratin Saha Optimizing Memory Transactions for Multicore Systems. Search on Bibsonomy Multicore Processors and Systems The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
38Li-Shiuan Peh, Stephen W. Keckler, Sriram R. Vangal On-Chip Networks for Multicore Systems. Search on Bibsonomy Multicore Processors and Systems The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
38Doug Burger, Stephen W. Keckler, Simha Sethumadhavan Composable Multicore Chips. Search on Bibsonomy Multicore Processors and Systems The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
38Gurindar S. Sohi, T. N. Vijaykumar Speculatively Multithreaded Architectures. Search on Bibsonomy Multicore Processors and Systems The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
38Peter Marwedel, Gert Goossens (eds.) Code Generation for Embedded Processors [Dagstuhl Workshop, Dagstuhl, Germany, August 31 - September 2, 1994] Search on Bibsonomy Code Generation for Embedded Processors The full citation details ... 1995 DBLP  BibTeX  RDF
38Henk Corporaal, Jan Hoogerbrugge Code generation for transport triggered architectures. Search on Bibsonomy Code Generation for Embedded Processors The full citation details ... 1994 DBLP  BibTeX  RDF
38Ulrich Bieker Retargetable compilation of self-test programs using constraint logic programming. Search on Bibsonomy Code Generation for Embedded Processors The full citation details ... 1994 DBLP  BibTeX  RDF
38Michel Langevin, Eduard Cerny, Jörg Wilberg, Heinrich Theodor Vierhaus Local microcode generation in system design. Search on Bibsonomy Code Generation for Embedded Processors The full citation details ... 1994 DBLP  BibTeX  RDF
38Steven Novack, Alexandru Nicolau, Nikil D. Dutt A Unified code generation approach using mutation scheduling. Search on Bibsonomy Code Generation for Embedded Processors The full citation details ... 1994 DBLP  BibTeX  RDF
38Wolfgang Schenk Retargetable code generation for parallel, pipelined processor structures. Search on Bibsonomy Code Generation for Embedded Processors The full citation details ... 1994 DBLP  BibTeX  RDF
38Farhad Mavaddat On transforming code generation to a parsing problem. Search on Bibsonomy Code Generation for Embedded Processors The full citation details ... 1994 DBLP  BibTeX  RDF
38Marco Cornero, Filip Thoen, Gert Goossens, Francesco Curatelli Software Synthesis for real-time information processing systems. Search on Bibsonomy Code Generation for Embedded Processors The full citation details ... 1994 DBLP  BibTeX  RDF
38Paul Vanoostende, Etienne Vanzieleghem, Emmanuel Rousseau, Christian Massy, François Gérard Retargetable code generation: key issues for successful introduction. Search on Bibsonomy Code Generation for Embedded Processors The full citation details ... 1994 DBLP  BibTeX  RDF
38Pierre G. Paulin, Clifford Liem, Trevor C. May, Shailesh Sutarwala Flexware: A flexible firmware development environment for embedded systems. Search on Bibsonomy Code Generation for Embedded Processors The full citation details ... 1994 DBLP  BibTeX  RDF
38Andreas Fauth Beyond tool-specific machine descriptions. Search on Bibsonomy Code Generation for Embedded Processors The full citation details ... 1994 DBLP  BibTeX  RDF
38Bernhard Wess Code generation based on trellis diagrams. Search on Bibsonomy Code Generation for Embedded Processors The full citation details ... 1994 DBLP  BibTeX  RDF
38Thomas Charles Wilson, Gary William Grewal, Shawn Henshall, Dilip K. Banerji An ILP-based approach to code generation. Search on Bibsonomy Code Generation for Embedded Processors The full citation details ... 1994 DBLP  BibTeX  RDF
37Pedro Marcuello, Antonio González 0001 Clustered speculative multithreaded processors. Search on Bibsonomy International Conference on Supercomputing The full citation details ... 1999 DBLP  DOI  BibTeX  RDF control-flow speculation, data value speculation, simultaneous multithreaded processors, dynamically scheduled processors, data dependance speculation, clustered processors
37Bernard Goossens, Duc Thang Vu Multithreading to Improve Cycle Width and CPI in Superpipelined Superscalar Processors. Search on Bibsonomy ISPAN The full citation details ... 1996 DBLP  DOI  BibTeX  RDF Superpipelined Processors, Architecture, Instruction Level Parallelism, Superscalar Processors, Multithreaded Processors
37Wade Walker, Harvey G. Cragon Interrupt Processing in Concurrent Processors. Search on Bibsonomy Computer The full citation details ... 1995 DBLP  DOI  BibTeX  RDF Interrupt processing, imprecise interrupts, concurrent processors, checkpointing, taxonomy, superscalar processors, pipelined processors, out- of-order execution, out-of-order issue, precise interrupts
36Nuno Roma, Leonel Sousa In the Development and Evaluation of Specialized Processors for Computing High-Order 2-D Image Moments in Real-Time. Search on Bibsonomy CAMP The full citation details ... 2000 DBLP  DOI  BibTeX  RDF specialized processors, high-order 2-D image moments, computational intensive task, systolic processing, programmable digital processors, configurable hardware logic, real-time system, image analysis, object modelling, floating-point arithmetic, digital signal processing chips, object matching
36Stefan M. Petters Bounding the execution time of real-time tasks on modern processors. Search on Bibsonomy RTCSA The full citation details ... 2000 DBLP  DOI  BibTeX  RDF task execution time, modern processors, embedded hard real time systems, up-to-date processors, fast core frequency, systematic information, real-time systems, computer architecture, complex systems, control flow graph, main memory, flow graphs, optimising compilers, real time tasks, acceleration techniques
36Ishfaq Ahmad, Yu-Kwong Kwok, Min-You Wu Analysis, evaluation, and comparison of algorithms for scheduling task graphs on parallel processors. Search on Bibsonomy ISPAN The full citation details ... 1996 DBLP  DOI  BibTeX  RDF edge-weighted directed acyclic graph, bounded number of processors scheduling, arbitrary processor network, scheduling, scheduling, parallel programming, processor scheduling, data flow graphs, task graphs, parallel processors, dataflow graph
35Rainer Leupers, Steven Bashford Graph-based code selection techniques for embedded processors. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF code selection, irregular data paths, embedded processors, data-flow graphs, SIMD instructions
35Grzegorz Malewicz, Alexander Russell, Alexander A. Shvartsman Distributed cooperation in the absence of communication (brief announcement). Search on Bibsonomy PODC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
33Stephen W. Melvin, Yale N. Patt Handling of packet dependencies: a critical issue for highly parallel network processors. Search on Bibsonomy CASES The full citation details ... 2002 DBLP  DOI  BibTeX  RDF memory synchronization, packet dependencies, parallel processing, network processors, processor architecture, thread level speculation, multithreaded processors, packet processing
33Fuji Ren Dialogue Machine Translation System Using Multiple Translation Processors. Search on Bibsonomy DEXA Workshops The full citation details ... 2000 DBLP  DOI  BibTeX  RDF dialogue machine translation system, multiple translation processors, natural dialogues, irregular expressions, natural conversation, ill-formed sentences, dialogue machine translation, MTP, translation processors, original language analysis, target language generation processing, Robust Parser based Translation Processor, Example Based Translation Processor, Family Modal based Translation Processor, Super Function based Translation Processor, information analysis model, syntactic constraint analysis model, semantic constraint analysis model, robust dialogue translation, language translation
33Eric Rotenberg, Quinn Jacobson, Yiannakis Sazeides, James E. Smith 0001 Trace Processors. Search on Bibsonomy MICRO The full citation details ... 1997 DBLP  DOI  BibTeX  RDF trace processors, multiscalar processors, next trace prediction, selective reissuing, context-based value prediction, trace cache
32Amirali Baniasadi Balancing clustering-induced stalls to improve performance in clustered processors. Search on Bibsonomy Conf. Computing Frontiers The full citation details ... 2005 DBLP  DOI  BibTeX  RDF clustering stalls, clustered processors
32Tzi-cker Chiueh, Prashant Pradhan Cache Memory Design for Network Processors. Search on Bibsonomy HPCA The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Routing Table Lookup, Caching, Network Processors
32John-David Wellman, Edward S. Davidson The resource conflict methodology for early-stage design space exploration of superscalar RISC processors. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF resource conflict methodology, early-stage design space exploration, superscalar RISC processors, execution trace driven simulation, hardware element model, analysis program, performance evaluation, virtual machines, computer architecture, reduced instruction set computing, design cycle
32Santanu Dutta, Wayne H. Wolf, Andrew Wolfe VLSI issues in memory-system design for video signal processors. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF VLSI issues, video signal processors, memory-system architectures, circuit-level issues, register-cache based hierarchy, general-purpose programmable microprocessors, VLSI, system architecture, utilization, memory architecture, memory architecture, video signal processing, area, cycle time, memory-system design
31Zhiyi Yu, Michael J. Meeuwsen, Ryan W. Apperson, Omar Sattari, Michael A. Lai, Jeremy W. Webb, Eric W. Work, Tinoosh Mohsenin, Bevan M. Baas Architecture and Evaluation of an Asynchronous Array of Simple Processors. Search on Bibsonomy J. Signal Process. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF programmable DSP, digital signal processing, DSP, multi-core, array processor, GALS, many-core, chip multi-processor, globally asynchronous locally synchronous
31Keith A. Bowman, Alaa R. Alameldeen, Srikanth T. Srinivasan, Chris Wilkerson Impact of die-to-die and within-die parameter variations on the throughput distribution of multi-core processors. Search on Bibsonomy ISLPED The full citation details ... 2007 DBLP  DOI  BibTeX  RDF FMAX distribution, parameter fluctuations, throughput distribution, multi-core, parameter variations
31Dariusz R. Kowalski, Alexander A. Shvartsman Writing-all deterministically and optimally using a non-trivial number of asynchronous processors. Search on Bibsonomy SPAA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF write-all, distributed algorithms, shared memory, asynchrony, work
31Theo Ungerer, Borut Robic, Jurij Silc A survey of processors with explicit multithreading. Search on Bibsonomy ACM Comput. Surv. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF interleaved multithreading, simultaneous multithreading, Blocked multithreading
31Byeong Kil Lee, Lizy Kurian John NpBench: A Benchmark Suite for Control plane and Data plane Applications for Network Processors. Search on Bibsonomy ICCD The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
31Peter R. Cappello Multicore processors as Array Processors: Research Opportunities. Search on Bibsonomy ASAP The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
30Pawel Gepner, David L. Fraser, Michal Filip Kowalik Second Generation Quad-Core Intel Xeon Processors Bring 45 nm Technology and a New Level of Performance to HPC Applications. Search on Bibsonomy ICCS (1) The full citation details ... 2008 DBLP  DOI  BibTeX  RDF quad-core processors, parallel processing, benchmarks, HPC, multi-core processors
30Adrián Cristal, Oliverio J. Santana, Francisco J. Cazorla, Marco Galluzzi, Tanausú Ramírez, Miquel Pericàs, Mateo Valero Kilo-Instruction Processors: Overcoming the Memory Wall. Search on Bibsonomy IEEE Micro The full citation details ... 2005 DBLP  DOI  BibTeX  RDF in-flight instructions, ROB, superscalar processors, memory wall, issue queue, Kilo-instruction processors
30M. Watheq El-Kharashi, Fayez El Guibaly, Kin F. Li Adapting Tomasulo's algorithm for bytecode folding based Java processors. Search on Bibsonomy SIGARCH Comput. Archit. News The full citation details ... 2001 DBLP  DOI  BibTeX  RDF instruction shelving, java bytecode folding, java stack folding, reservation stations, stack processors, tomasulo's algorithm, java, Java, java virtual machine, dynamic scheduling, java processors, register renaming
30A. K. Riemens, Kees A. Vissers, R. J. Schutten, Gerben J. Hekstra, G. D. La Hei, Frans Sijstermans TriMedia CPU64 Application Domain and Benchmark Suite. Search on Bibsonomy ICCD The full citation details ... 1999 DBLP  DOI  BibTeX  RDF TriMedia, multi-media benchmark, design space exploration, embedded processors, VLIW processors, media processing
30Thomas M. Conte, Kishore N. Menezes, Sumedh W. Sathaye A technique to determine power-efficient, high-performance superscalar processors. Search on Bibsonomy HICSS (1) The full citation details ... 1995 DBLP  DOI  BibTeX  RDF high-performance superscalar processors, processor performance advances, thermal power dissipation, architectural power estimates, systematic techniques, user benchmarks, architectural component, real estate usage, superscalar execution units, architectural power measurement, near-optimal search, power-efficient superscalar processors, performance evaluation, parallel architectures, simulated annealing, simulated annealing, parallel machines, power consumption, trace-driven simulation
30Isaac Gelado, John H. Kelm, Shane Ryoo, Steven S. Lumetta, Nacho Navarro, Wen-mei W. Hwu CUBA: an architecture for efficient CPU/co-processor data communication. Search on Bibsonomy ICS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF co-processors
30Surendra Byna, Yong Chen 0001, Xian-He Sun Taxonomy of Data Prefetching for Multicore Processors. Search on Bibsonomy J. Comput. Sci. Technol. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF taxonomy of prefetching strategies, memory hierarchy, multicore processors, data prefetching
30Jayanth Gummaraju, Joel Coburn, Yoshio Turner, Mendel Rosenblum Streamware: programming general-purpose multicore processors using streams. Search on Bibsonomy ASPLOS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF general-purpose multicore processors, programming, streams, runtime system
30Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Compilers for low energy, loop buffers, VLIW processors
30Xiaotong Zhuang, Santosh Pande Effective thread management on network processors with compiler analysis. Search on Bibsonomy LCTES The full citation details ... 2006 DBLP  DOI  BibTeX  RDF real-time scheduling, compiler optimizations, network processors, CPU scheduling
30Naga K. Govindaraju, Nikunj Raghuvanshi, Dinesh Manocha Fast and Approximate Stream Mining of Quantiles and Frequencies Using Graphics Processors. Search on Bibsonomy SIGMOD Conference The full citation details ... 2005 DBLP  DOI  BibTeX  RDF data streams, sorting, sliding windows, memory bandwidth, graphics processors, frequencies, quantiles
30Soraya Ghiasi, Tom W. Keller, Freeman L. Rawson III Scheduling for heterogeneous processors in server systems. Search on Bibsonomy Conf. Computing Frontiers The full citation details ... 2005 DBLP  DOI  BibTeX  RDF scheduling, performance, power, heterogeneous processors
30Oleg Bessonov, Dominique Fougère, Bernard Roux Analysis of Architecture and Design of Linear Algebra Kernels for Superscalar Processors. Search on Bibsonomy PaCT The full citation details ... 2003 DBLP  DOI  BibTeX  RDF linear algebra kernels, LINPACK benchmark, performance measurements, instruction level parallelism, cache memories, microarchitecture, out-of-order processors
30Madhavi Gopal Valluri, R. Govindarajan Evaluating Register Allocation and Instruction Scheduling Techniques in Out-Of-Order Issue Processors. Search on Bibsonomy IEEE PACT The full citation details ... 1999 DBLP  DOI  BibTeX  RDF Out-of-order Issue Processors, Instruction-Level Parallelism, Register Allocation, Instruction Scheduling, Integrated Methods
29Chin-Long Wey, Haiyan Wang, Cheng-Ping Wang A self-timed redundant-binary number to binary number converter for digital arithmetic processors. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF convertors, self-timed redundant-binary number to binary number converter, digital arithmetic processors, self-timed converter circuit, variable conversion time, statistical upper bound, delays, digital arithmetic, propagation delay, redundant number systems
29Bhaskar Saha, J. Sukarno Mertoguno, Nikolaos G. Bourbakis The VLSI design and implementation of the array processors of a multilayer vision system architecture. Search on Bibsonomy ASAP The full citation details ... 1995 DBLP  DOI  BibTeX  RDF multilayer vision system architecture, KYDON vision system, multilayered image understanding system, computer vision, parallel processing, VLSI, digital simulation, VLSI design, array processors, timing simulation
29Kunal Agrawal, Charles E. Leiserson, Yuxiong He, Wen-Jing Hsu Adaptive work-stealing with parallelism feedback. Search on Bibsonomy ACM Trans. Comput. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF instantaneous parallelism, parallelism feedback, trim analysis, parallel computation, randomized algorithm, job scheduling, multiprogramming, processor allocation, multiprocessing, work-stealing, Adaptive scheduling, work, thread scheduling, adversary, span, space sharing, two-level scheduling
29Bharadwaj Veeravalli, Wong Han Min Scheduling Divisible Loads on Heterogeneous Linear Daisy Chain Networks with Arbitrary Processor Release Times. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF finish times, communication delays, divisible loads, processing times, release times, Linear networks
29Grzegorz Malewicz, Alexander Russell, Alexander A. Shvartsman Distributed Cooperation During the Absence of Communication. Search on Bibsonomy DISC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
29Ronny Krashinsky, Christopher Batten, Krste Asanovic Implementing the scale vector-thread processor. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF hybrid C++/Verilog simulation, iterative VLSI design flow, procedural datapath pre-placement, vector-thread processors, multithreaded processors, Vector processors
29Mayan Moudgill, Stamatis Vassiliadis Precise Interrupts. Search on Bibsonomy IEEE Micro The full citation details ... 1996 DBLP  DOI  BibTeX  RDF interrupt handlers, out-of-order issue processors, instruction level parallel processors, pipelining, exceptions, superscalar processors, traps, precise interrupts
29Tsutomu Hoshino, Toshio Kawai, Tomonori Shirakawa, Jun'ichi Higashino, Akira Yamaoka, Hachidai Ito, Takashi Sato, Kazuo Sawada PACS: A Parallel Microprocessor Array for Scientific Calculations Search on Bibsonomy ACM Trans. Comput. Syst. The full citation details ... 1983 DBLP  DOI  BibTeX  RDF highly parallel processors, multimicroprocessors, nearest neighbor communication, scientific calculation, distributed systems, parallel algorithms, synchronization, multiprocessors, performance measurement, supercomputer, parallel language, processor architecture, MIMD, array processors, multiprocessing, parallel processors
29Kenneth E. Batcher Bit-Serial Parallel Processing Systems. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1982 DBLP  DOI  BibTeX  RDF radar processing, Airborne processors, bit-serial processors, custom VLSI chips, multidimensional access, image processing, parallel processors
29Deepa Kannan, Aseem Gupta, Aviral Shrivastava, Nikil D. Dutt, Fadi J. Kurdahi PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors. Search on Bibsonomy VLSI Design The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
29Bogdan S. Chlebus, Dariusz R. Kowalski Randomization Helps to Perform Tasks on Processors Prone to Failures. Search on Bibsonomy DISC The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
29Jack L. Rosenfeld A case study in programming for parallel-processors. Search on Bibsonomy Commun. ACM The full citation details ... 1969 DBLP  DOI  BibTeX  RDF Gauss-Seidel, Jacobi, storage interference, simulation, parallel programming, parallelism, multiprocessor, convergence, tasking, multiprogramming, relaxation, parallel-processor, electrical network
28Adrián Cristal, José F. Martínez, Josep Llosa, Mateo Valero A case for resource-conscious out-of-order processors: towards kilo-instruction in-flight processors. Search on Bibsonomy SIGARCH Comput. Archit. News The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
28Byeong Kil Lee, Lizy Kurian John Implications of Programmable General Purpose Processors for Compression/Encryption Applications. Search on Bibsonomy ASAP The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
28Farinaz Koushanfar, Miodrag Potkonjak, Vandana Prabhu, Jan M. Rabaey Processors for Mobile Applications. Search on Bibsonomy ICCD The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
28Lin Chen 0001 Optimal overlap representations. Search on Bibsonomy ISPAN The full citation details ... 1996 DBLP  DOI  BibTeX  RDF optimal overlap representations, minimal interval, circular arc overlap representations, minimal interval overlap representation, EREW PRAM processors, common CRCW PRAM, BSR processors, parallel algorithms, computational complexity, computational geometry, optimal algorithms
28David Goodwin, Darin Petkov Automatic generation of application specific processors. Search on Bibsonomy CASES The full citation details ... 2003 DBLP  DOI  BibTeX  RDF automatic instruction-set generation, ASIPs, configurable processors, extensible processors
28Jorge E. Carrillo, Paul Chow The effect of reconfigurable units in superscalar processors. Search on Bibsonomy FPGA The full citation details ... 2001 DBLP  DOI  BibTeX  RDF OneChip, superscalar processors, reconfigurable processors
28Sang Jeong Lee, Yuan Wang, Pen-Chung Yew Decoupled Value Prediction on Trace Processors. Search on Bibsonomy HPCA The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Wide-issue superscalar processors, Trace processors, Speculative execution, Value prediction
28Joseph A. Fisher Customized Instruction-Sets for Embedded Processors. Search on Bibsonomy DAC The full citation details ... 1999 DBLP  DOI  BibTeX  RDF custom processors, mass customization of toolchains, instruction-level parallelism, VLIW, embedded processors
28Pedro Marcuello, Antonio González 0001, Jordi Tubella Speculative Multithreaded Processors. Search on Bibsonomy International Conference on Supercomputing The full citation details ... 1998 DBLP  DOI  BibTeX  RDF multithreaded processors, data speculation, dynamically scheduled processors, data dependence speculation, control speculation
28Sandeep N. Bhatt, Geppino Pucci, Abhiram G. Ranade, Arnold L. Rosenberg Scattering and Gathering Messages in Networks of Processors. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1993 DBLP  DOI  BibTeX  RDF message scattering, messages gathering, networks of processors, trees of processors, noncolliding paths, queueing mechanisms, scheduling, distributed processing, multiprocessor interconnection networks, spanning trees, buffering
28Ashok K. Agrawala, Edward G. Coffman Jr., M. R. Garey, Satish K. Tripathi A Stochastic Optimization Algorithm Minimizing Expected Flow Times on Uniform Processors. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1984 DBLP  DOI  BibTeX  RDF uniform processor systems, Consider a set of processors P1, ..., Pm differing only in speed and a set of jobs with exponentially distributed execution times, The rate parameter for the ith processor is given by ?i, 1 =i = m, where we assume the processors are ordered so that ?1 = ?2 = ... = ?m. The problem is to sequence the jobs nonpreemptively so as to minimize expected total flow time (sum of finishing times). We defin, Mean flow time minimization, stochastic optimization, stochastic scheduling, routing problems
28Chris R. Jesshope Some Results Concerning Data Routing in Array Processors. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1980 DBLP  DOI  BibTeX  RDF data rotation, ICL distributed array processor (DAP), k-dimensional cyclic networks, Array processors, parallel processors, data routing
27Marco Galluzzi, Valentin Puente, Adrián Cristal, Ramón Beivide, José-Ángel Gregorio, Mateo Valero A first glance at Kilo-instruction based multiprocessors. Search on Bibsonomy Conf. Computing Frontiers The full citation details ... 2004 DBLP  DOI  BibTeX  RDF ROB, in-flight instructions, shared-memory multiprocessors, CC-NUMA, memory wall, instruction window, Kilo-instruction processors
27Emile Haddad Optimal load distribution for asynchronously scheduled homogeneous multiprocessor and distributed systems. Search on Bibsonomy HICSS (2) The full citation details ... 1995 DBLP  DOI  BibTeX  RDF optimal load distribution, asynchronously scheduled homogeneous multiprocessor systems, interacting tasks, identical processors, job completion time minimization, execution initiation times, earliest availability, load parameters, optimal load allocation, uneven module distribution, distributed systems, resource allocation, distributed processing, multiprocessing systems, processor scheduling, minimisation, system parameters, processor assignment
27Ning Weng, Tilman Wolf Analytic modeling of network processors for parallel workload mapping. Search on Bibsonomy ACM Trans. Embed. Comput. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF embedded systems, network processors, multiprocessor scheduling, Application profiling
27Vinay Hanumaiah, Ravishankar Rao, Sarma B. K. Vrudhula, Karam S. Chatha Throughput optimal task allocation under thermal constraints for multi-core processors. Search on Bibsonomy DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF optimal throughput, task allocation, thermal management, multi-core processors, thread migration
27Garo Bournoutian, Alex Orailoglu Miss reduction in embedded processors through dynamic, power-friendly cache design. Search on Bibsonomy DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF dynamic associativity, multi-core, embedded processors, data cache
27Ya-Shuai Lü, Li Shen 0007, Libo Huang, Zhiying Wang 0003, Nong Xiao Customizing computation accelerators for extensible multi-issue processors with effective optimization techniques. Search on Bibsonomy DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF subgraph covering, VLIW, ASIPs, extensible processors
27Lixia Liu, Xiao-Feng Li, Michael K. Chen, Roy Dz-Ching Ju A Throughput-Driven Task Creation and Mapping for Network Processors. Search on Bibsonomy HiPEAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Intel IXP, Task Creation and Mapping, Throughput, Network Processors, Dataflow Programming
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