Search results for "control-dominated"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
50	Wayne H. Wolf	The FSM Network Model for Behavioral Synthesis of Control-Dominated Machines.	DAC	1990	DBLP DOI BibTeX RDF
49	Gabriele Saucier, Jacques Trilhe (eds.)	Synthesis for Control Dominated Circuits, Selected papers from the IFIP WG10.2/WG10.5 Workshops, Grenoble, France, April and September, 1992	Synthesis for Control Dominated Circuits	1993	DBLP BibTeX RDF
49	Eric Gautrin, Laurent Perraudeau	MADMACS: an environment for the layout of regular arrays.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
49	H. Zhang, Kunihiro Asada	A general and efficient mask pattern generator for non-series-parallel CMOS transistor network.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
49	E. T. Kapuya, M. D. Edwards	Microarchitecture/Microcode Synthesis from VHDL.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
49	C. Safina, Régis Leveugle	Clocking scheme selection for circuits made up of a controller and a datapath.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
49	Jochen Beister, Ralf Wollowski	Controller Implementation by Communicating Asynchronous Sequential Circuits Generated from a Petri Net Specification of Required Behavior.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
49	Evagelos Katsadas, Zohair Sahraoui, Maryse Wouters, Veerle Derudder, Ivo Bolsens, Paul Six, Hugo De Man	Regular Module Generation or Standard Cells: Two Alternative Implementations of a Library of Functional Building Blocks.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
49	Daniel Gajski, Nikil D. Dutt	Benchmarking and the Art of Syntesis Tool Comparison.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
49	A. J. W. M. ten Berg	Floorplan Optimized Topological Partitioning of Programmed Logic Arrays.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
49	Jörg Biesenack, Norbert Wehn, A. Stoll, Michael Payer	Data Part Optimizations in the CALLAS Synthesis Environment.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
49	J. F. M. Theeuwen, H. M. A. M. Arts, Jos T. J. van Eijndhoven, H. J. H. Sleuters, J. H. P. Wijdeven	Module Generation in an Architectural Synthesis Environment.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
49	Vasily G. Moshnyaga, Keikichi Tamaru, Hiroto Yasuura	Design of data-path module generators from algorithmic representations.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
49	James Pardey	The Synthesis of a Parallel Controller from a Petri Net Model.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
49	Antonio Martinez	Timing Model Accuracy Issues and Automated Library Characterization.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
49	Steve C.-Y. Huang, Wayne H. Wolf	Timing-Driven State Assignment for Controller-Datapath Systems.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
49	Régis Leveugle, C. Safina	Generation of optimized datapaths: bit-slice versus standard cells.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
49	Inhag Park, Kevin O'Brien, Ahmed Amine Jerraya	AMICAL: Architectural Synthesis based on VHDL.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
49	Andreas Münzner	BADGE - A synthesis tool for customized arithmetic building blocks.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
49	H. Belhadj, Laurent Gerbaux, Marie-Claude Bertrand, Gabriele Saucier	Specification and Synthesis of Communicating Finite State Machines.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
49	ChiLai Huang, Joseph Lis, Michael Quayle, Saurin Shroff	RTL Controller Synthesis.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
49	Yang Wu, Ian Dorrington	RTL OptimizA: From Control Data Flow Graph to Logic Circuit.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
49	Lotfi Ben Ammar, Alain Greiner	FITPATH: A Process-Independent Datapath Compiler Providing High Density Layout.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
49	Laurent Gerbaux, Régis Leveugle, Gabriele Saucier	Synthesis of large controllers using ROM or PLA generators.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
49	Peter Marwedel	Implementations of IF-statements in the TODOS microarchitecture synthesis system.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
49	A. G. Jost, L. F. Wang, S. Periyalwar, William Robertson 0001	Automatic Layout Synthesis of Pipelined Multipliers for Systolic Arrays.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
49	Alan J. Coppola, Marek A. Perkowski, Robert Anderson, Jeffrey S. Freedman, Edmund Pierzchala	Tokenized State Machine Model for Synthesis of Sequential Circuits into EPLDs and FPGAs.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
49	Francesco Curatelli, Daniele D. Caviglia, Marco Chirico, Giacomo M. Bisio	Optimization strategies in symbolic compaction.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
49	Amnon Baron Cohen, Michael Shechory	Pathway: A datapath layout assembler.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
49	Anne Mignotte, Marie-Claude Bertrand, Michel Crastes de Paulet, Jérôme Rampon, Gabriele Saucier	ASYL: A Control Driven RTL Synthesis System using Library Blocks.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
49	Pierre Abouzeid, Régis Leveugle, Gabriele Saucier	Logic Synthesis for Automatic Layout.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
49	Farhad Mavaddat	Data-Path Synthesis as Grammar Inference.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
49	B. Conq, R. Etienne, T. Perez-Segovia	Design Library Portability: A Case Study.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
49	Augusli Kifli, R. De Wulf, J. Zegers, Gert Goossens, Paul Six, Hugo De Man	Flag/Condition Handling and Branch Assignment for Large Microcoded Controllers.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
48	Íñigo Ugarte, Pablo Sanchez	Assertion checking of control dominated systems with nonlinear solvers.	MEMOCODE	2006	DBLP DOI BibTeX RDF
34	Alessandro Balboni, William Fornaciari, Massimo Vincenzi, Donatella Sciuto	The Use of a Virtual Instruction Set for the Software Synthesis of HW/SW Embedded Systems.	ISSS	1996	DBLP DOI BibTeX RDF	virtual instruction set, control-dominated hardware-software system, retargetable code synthesis, real-time systems, embedded systems, software development, performance estimation, embedded computing, software synthesis, real-time constraints, system synthesis, static scheduling
33	Pai H. Chou, Gaetano Borriello	Software Architecture Synthesis for Retargetable Real-time Embedded Systems.	CODES	1997	DBLP DOI BibTeX RDF	control-dominated, software architecture synthesis, embedded systems, reactive systems, Run-time systems, real-time constraints
33	Partha S. Roop, Zoran A. Salcic, Morteza Biglari-Abhari, Abbas Bigdeli	A New Reactive Processor with Architectural Support for Control Dominated Embedded Systems.	VLSI Design	2003	DBLP DOI BibTeX RDF
31	Chih-Tung Chen, Kayhan Küçükçakar	High-level scheduling model and control synthesis for a broad range of design applications.	ICCAD	1997	DBLP DOI BibTeX RDF	multi-phase clocking, relative scheduling, architectural power optimization, high-level synthesis, pipelining, multi-threading, behavioral synthesis, control synthesis, architectural synthesis, scheduling model
30	Ivan Radojevic, Zoran A. Salcic, Partha S. Roop	Design of Heterogeneous Embedded Systems Using DFCharts Model of Computation.	VLSI Design	2006	DBLP DOI BibTeX RDF
28	Karim Ben Chehida, Michel Auguin	A SW/Configware Codesign Methodology for Control Dominated Applications.	ASAP	2005	DBLP DOI BibTeX RDF
25	Tsung-Yi Wu, Youn-Long Lin	Register Minimization beyond Sharing among Variables.	DAC	1995	DBLP DOI BibTeX RDF	control-dominated circuit, storage synthesis, high-level synthesis
24	Ludovic L'Hours	Generating Efficient Custom FPGA Soft-Cores for Control-Dominated Applications.	ASAP	2005	DBLP DOI BibTeX RDF
24	Charles André, Marie-Agnès Peraldi-Frati, Jean-Paul Rigault	Integrating the Synchronous Paradigm into UML: Application to Control-Dominated Systems.	UML	2002	DBLP DOI BibTeX RDF
24	Franco Fummi, U. Rovati, Donatella Sciuto	Functional design for testability of control-dominated architectures.	ACM Trans. Design Autom. Electr. Syst.	1997	DBLP DOI BibTeX RDF	interacting FSMs, functional testing
19	Ti-Yen Yen, Wayne H. Wolf	An efficient graph algorithm for FSM scheduling.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
18	Tilman Kolks, Steven Vercauteren, Bill Lin 0001	Control resynthesis for control-dominated asynchronous designs.	ASYNC	1996	DBLP DOI BibTeX RDF
18	Shih-Hsu Huang, Yu-Chin Hsu, Yen-Jen Oyang	A new scheduling algorithm for synthesizing the control blocks of control-dominated circuits.	Microprocess. Microprogramming	1995	DBLP DOI BibTeX RDF
17	Peter Petrov, Alex Orailoglu	A reprogrammable customization framework for efficient branch resolution in embedded processors.	ACM Trans. Embed. Comput. Syst.	2005	DBLP DOI BibTeX RDF	Branch resolution, pipeline organization
16	Zoran A. Salcic, Partha S. Roop, Morteza Biglari-Abhari, Abbas Bigdeli	REFLIX: a processor core with native support for control-dominated embedded applications.	Microprocess. Microsystems	2004	DBLP DOI BibTeX RDF
16	Stephen A. Edwards	An Esterel compiler for large control-dominated systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
16	Chunhong Chen, Majid Sarrafzadeh	Power-Manageable Scheduling Technique for Control Dominated High-Level Synthesis.	DATE	2002	DBLP DOI BibTeX RDF
16	Peter Petrov, Alex Orailoglu	Speeding Up Control-Dominated Applications through Microarchitectural Customizations in Embedded Processors.	DAC	2001	DBLP DOI BibTeX RDF
16	Ki-Seok Chung, Taewhan Kim, Chien-Liang Liu	Behavioral-level partitioning for low power design in control-dominated application.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF
16	Alessandro Bogliolo, Luca Benini, Bruno Riccò, Giovanni De Micheli	Efficient switching activity computation during high-level synthesis of control-dominated designs.	ISLPED	1999	DBLP DOI BibTeX RDF
16	Werner Grass, Stefan Lenk 0001, Christine Sontheim	Design of Control Dominated Hardware Based on Formal Methods.	EUROMICRO	1998	DBLP DOI BibTeX RDF
16	Michael Münch, Norbert Wehn, Manfred Glesner	An efficient ILP-based scheduling algorithm for control-dominated VHDL descriptions.	ACM Trans. Design Autom. Electr. Syst.	1997	DBLP DOI BibTeX RDF	scheduling, timing constraints, integer linear programming (ILP)
16	Alessandro Balboni, William Fornaciari, Donatella Sciuto	Co-synthesis and co-simulation of control-dominated embedded systems.	Des. Autom. Embed. Syst.	1996	DBLP DOI BibTeX RDF
16	Michael Münch, Manfred Glesner, Norbert Wehn	An Efficient ILP-Based Scheduling Algorithm for Control-Dominated VHDL Descriptions.	ISSS	1996	DBLP DOI BibTeX RDF	control-flow dominated VHDL, time-constrainted scheduling, scheduling, ILP, code transformation, resource-constrained scheduling
16	Stefano Antoniazzi, Alessandro Balboni, William Fornaciari, Donatella Sciuto	A methodology for control-dominated systems codesign.	CODES	1994	DBLP DOI BibTeX RDF
16	S. H. Huang, Y. L. Jeang, C. T. Hwang, Y. C. Hsu, J. F. Wang	A Tree-Based Scheduling Algorithm for Control-Dominated Circuits.	DAC	1993	DBLP DOI BibTeX RDF	VHDL
15	Lei Yang 0012, Morteza Biglari-Abhari, Zoran A. Salcic	A Power-Efficient Processor Core for Reactive Embedded Applications.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
13	Xin Li 0020, Marian Boldt, Reinhard von Hanxleden	Mapping esterel onto a multi-threaded embedded processor.	ASPLOS	2006	DBLP DOI BibTeX RDF	low-power processing, concurrency, reactive systems, multi-threading, esterel
10	Alessandro Bogliolo, Enrico Macii, Virgil Mihailovici, Massimo Poncino	Power Models for Semi-autonomous RTL Macros.	PATMOS	2000	DBLP DOI BibTeX RDF
10	Sien-An Ong, Kari Tiensyrjä, Lech Józwiak	Interactive codesign for real-time embedded control systems: task graph generation from SA/VHDL models.	EUROMICRO	1997	DBLP DOI BibTeX RDF	interactive codesign, real-time embedded control systems, task graph generation, InCo, textual functional specification method, linear control structures, static behavioral analysis, graphical functional specification method, high level synthesis, finite-state machines, VHDL, modular design, hierarchical decomposition, hardware software partitioning, cost-efficient
9	Ravi Namballa, Nagarajan Ranganathan, Abdel Ejnioui	Control and Data Flow Graph Extraction for High-Level Synthesis.	ISVLSI	2004	DBLP DOI BibTeX RDF
9	Forrest Brewer, Steve Haynal	Symbolic NFA scheduling of a RISC microprocessor.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
9	X. Wendling, H. Chauvet, Lionel Revéret, Raphaël Rochet, Régis Leveugle	Automatic and Optimized Synthesis of Dataparts with Fault Detection or Tolerance Capabilities.	DFT	1997	DBLP DOI BibTeX RDF	RTL synthesis, dependable VLSI circuits, fault tolerance, fault detection, CAD tools
8	John D. Carter, William B. Gardner	Converting scenarios to CSP traces with Mise en Scene for requirements-based programming.	Innov. Syst. Softw. Eng.	2008	DBLP DOI BibTeX RDF
8	Leonardo Mangeruca, Massimo Baleani, Alberto Ferrari, Alberto L. Sangiovanni-Vincentelli	Semantics-Preserving Design of Embedded Control Software from Synchronous Models.	IEEE Trans. Software Eng.	2007	DBLP DOI BibTeX RDF	Software design methodologies, embedded software design, protection mechanisms
8	Marc Segelken	Abstraction and Counterexample-Guided Construction of omega -Automata for Model Checking of Step-Discrete Linear Hybrid Models.	CAV	2007	DBLP DOI BibTeX RDF	automata construction, counterexample guidance, iterative abstraction refinement, step-discrete hybrid systems, model-checking
8	Anupam Chattopadhyay, W. Ahmed, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	Design space exploration of partially re-configurable embedded processors.	DATE	2007	DBLP DOI BibTeX RDF
8	John D. Carter, William B. Gardner	Mise en Scene: Converting Scenarios to CSP Traces in Support of Requirements-Based Programming.	SEW	2007	DBLP DOI BibTeX RDF
8	Deepak Kapur, Rupak Majumdar, Calogero G. Zarba	Interpolation for data structures.	SIGSOFT FSE	2006	DBLP DOI BibTeX RDF	CEGAR, data structure verification, interpolation
8	Gianpiero Cabodi, Alex Kondratyev, Luciano Lavagno, Sergio Nocco, Stefano Quer, Yosinori Watanabe	A BMC-based formulation for the scheduling problem of hardware systems.	Int. J. Softw. Tools Technol. Transf.	2005	DBLP DOI BibTeX RDF	Hardware scheduling, Binary decision diagrams, Bounded model checking, Satisfiability solvers
8	Jürgen Becker 0001, Alexander Thomas	Scalable Processor Instruction Set Extension.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF
8	Massimo Baleani, Alberto Ferrari, Leonardo Mangeruca, Alberto L. Sangiovanni-Vincentelli	Efficient embedded software design with synchronous models.	EMSOFT	2005	DBLP DOI BibTeX RDF	model-based, synchrony
8	Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti	Exploring Design Space of VLIW Architectures.	ASAP	2005	DBLP DOI BibTeX RDF
8	Partha S. Roop, Zoran A. Salcic, M. W. Sajeewa Dayaratne	Towards direct execution of esterel programs on reactive processors.	EMSOFT	2004	DBLP DOI BibTeX RDF	ARE-Bench Auckland reactive benchmark, direct ESTEREL execution, reactive processor architectures
8	Kees A. Vissers	Programming models and architectures for FPGA platforms.	CASES	2004	DBLP DOI BibTeX RDF
8	Enric Pastor, Marco A. Peña	Efficient Hybrid Reachability Analysis for Asynchronous Concurrent Systems.	CHARME	2003	DBLP DOI BibTeX RDF
8	Gérard Berry, Michael Kishinevsky, Satnam Singh	System Level Design and Verification Using a Synchronous Language.	ICCAD	2003	DBLP DOI BibTeX RDF
8	Qin Zhao, Bart Mesman, Twan Basten	Practical Instruction Set Design and Compiler Retargetability Using Static Resource Models.	DATE	2002	DBLP DOI BibTeX RDF
8	Luciano Lavagno, Mihai T. Lazarescu, Stefano Quer, Sergio Nocco, Claudio Passerone, Gianpiero Cabodi	A Symbolic Approach for the Combined Solution of Scheduling and Allocation.	ISSS	2002	DBLP DOI BibTeX RDF	scheduling, high-level synthesis, automata, BDD, allocation
8	Per Bjuréus, Axel Jantsch	Modeling of mixed control and dataflow systems in MASCOT.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
8	Charles André, Marie-Agnès Peraldi, Jean-Paul Rigault	Scenario and Property Checking of Real-Time Systems Using a Synchronous Approach.	ISORC	2001	DBLP DOI BibTeX RDF
8	Marco Di Natale, Alberto L. Sangiovanni-Vincentelli, Felice Balarin	Scheduling Reactive Task Graphs in Embedded Control Systems.	IEEE Real Time Technology and Applications Symposium	2001	DBLP DOI BibTeX RDF
8	Felice Balarin	Automatic Abstraction for Worst-Case Analysis of Discrete Systems.	DATE	2000	DBLP DOI BibTeX RDF
8	Franco Fummi, Donatella Sciuto, Micaela Serra	Synthesis for Testability of Highly Complex Controllers by Functional Redundancy Removal.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	sequential circuits, functional testing, Synthesis for testability, logic minimization, redundant faults, redundancies removal
8	Fulvio Corno, Uwe Gläser, Paolo Prinetto, Matteo Sonza Reorda, Heinrich Theodor Vierhaus, Massimo Violante	SymFony: a hybrid topological-symbolic ATPG exploiting RT-level information.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
8	Kazutoshi Wakabayashi	C-based Synthesis Experiences with a Behavior Synthesizer, "Cyber".	DATE	1999	DBLP DOI BibTeX RDF
8	Claus Schneider	Executable Specification for Multimedia Supporting Refinement and Architecture Exploration.	EUROMICRO	1999	DBLP DOI BibTeX RDF
8	William Fornaciari, Paolo Gubian, Donatella Sciuto, Cristina Silvano	Power estimation of embedded systems: a hardware/software codesign approach.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
8	Johnny Öberg, Anshul Kumar, Ahmed Hemani	Specification of Exception Handling in Grammar-Based Hardware Synthesis.	EUROMICRO	1998	DBLP DOI BibTeX RDF
8	Karsten Lüth	The ICOS Synthesis Environment.	FTRTFT	1998	DBLP DOI BibTeX RDF
8	Franco Fummi, Mariagiovanna Sami, F. Tartarini	Use of Statecharts-Related Description to Achieve Testable Design of Control Subsystems.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF
8	Tsung-Yi Wu, Youn-Long Lin	Register minimization beyond sharing among variables.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
8	Alessandro Balboni, William Fornaciari, Donatella Sciuto	Partitioning and Exploration Strategies in the TOSCA Co-Design Flow.	CODES	1996	DBLP DOI BibTeX RDF
8	Jörg Biesenack, Michael Koster, Anton Langmaier, Stephane Ledeux, Sabine März, Michael Payer, Michael Pilsl, Steffen Rumler, Holger Soukup, Norbert Wehn, Peter Duzy	The Siemens high-level synthesis system CALLAS.	IEEE Trans. Very Large Scale Integr. Syst.	1993	DBLP DOI BibTeX RDF
8	Gérard Berry	Preemption in Concurrent Systems.	FSTTCS	1993	DBLP DOI BibTeX RDF