Search results for "core-cells"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
25	Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine	A statistical simulation method for reliability analysis of SRAM core-cells.	DAC	2010	DBLP DOI BibTeX RDF	SRAM core-cell, Monte-Carlo, reliability analysis
25	Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan	Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
24	Simone Borri, Magali Hage-Hassan, Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel	Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	address decoders, core-cells, memory testing, dynamic faults
21	Rajesh K. Gupta 0001, Yervant Zorian	Introducing Core-Based System Design.	IEEE Des. Test Comput.	1997	DBLP DOI BibTeX RDF
18	Yih-Chih Chou, Youn-Long Lin	Effective enforcement of path-delay constraints inperformance-driven placement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
18	Yih-Chih Chou, Youn-Long Lin	A performance-driven standard-cell placer based on a modified force-directed algorithm.	ISPD	2001	DBLP DOI BibTeX RDF	placement, timing closure, force-directed
15	D. Jothi, R. Sivakumar	Design and Analysis of Power Efficient Binary Content Addressable Memory (PEBCAM) Core Cells.	Circuits Syst. Signal Process.	2018	DBLP DOI BibTeX RDF
15	Elena I. Vatajelu, Alberto Bosio, Luigi Dilillo, Patrick Girard 0001, Aida Todri, Arnaud Virazel, Nabil Badereddine	Analyzing the effect of concurrent variability in the core cells and sense amplifiers on SRAM read access failures.	DTIS	2013	DBLP DOI BibTeX RDF
15	Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine	Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes.	ETS	2010	DBLP DOI BibTeX RDF
15	Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine	Detecting NBTI induced failures in SRAM core-cells.	VTS	2010	DBLP DOI BibTeX RDF
15	Florian Bauer, Georg Georgakos, Doris Schmitt-Landsiedel	A Design Space Comparison of 6T and 8T SRAM Core-Cells.	PATMOS	2008	DBLP DOI BibTeX RDF
15	Stefano Di Carlo, Alessandro Savino, Alberto Scionti, Paolo Prinetto	Influence of Parasitic Capacitance Variations on 65 nm and 32 nm Predictive Technology Model SRAM Core-Cells.	ATS	2008	DBLP DOI BibTeX RDF
15	Lushan Liu, Ramalingam Sridhar, Shambhu J. Upadhyaya	A 3-port Register File Design for Improved Fault Tolerance on Resistive Defects in Core-Cells.	DFT	2006	DBLP DOI BibTeX RDF
15	Albert Jan Huitsing, Theo Smedes, H.-U. Schröder	A simple design methodology for increased ESD robustness of CMOS core cells.	ESSCIRC	2003	DBLP DOI BibTeX RDF
15	Kenneth J. Schultz	Content-addressable memory core cells A survey.	Integr.	1997	DBLP DOI BibTeX RDF
15	Venkata R. Immaneni, Srinivas Raman	Direct access test scheme-design of block and core cells for embedded ASICs.	ITC	1990	DBLP DOI BibTeX RDF
14	Olivier Ginez, Jean Michel Daga, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories.	ETS	2007	DBLP DOI BibTeX RDF
7	Ming-Fang Lai, Hung-Ming Chen	An Implementation of Performance-Driven Block and I/O Placement for Chip-Package Codesign.	ISQED	2008	DBLP DOI BibTeX RDF	Chip-Package Codesign, I/O Placement, Power Integrity
7	Alexandre Ney, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian	Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs.	VTS	2007	DBLP DOI BibTeX RDF
7	Sornavalli Ramanathan, Rituparna Mandal	Low Power Solution for Wireless Applications.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	2.5G, Multi-Vt, CMOS, 3G
7	Sabyasachi Sengupta, Somavalli Ramanathan, Biswadeep Chatterjee, Dibyendu Goswami	Minimizing Area and Maximizing Porosity for Cell Layouts Using Innovative Routing Strategies.	VLSI Design	2001	DBLP DOI BibTeX RDF