Search results for "crypto-processor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
94	Abdulah Abdulah Zadeh	High performance synchronized dual elliptic curve crypto-processor.	CCECE	2009	DBLP DOI BibTeX RDF
58	Bonseok Koo, Dongwook Lee, Gwonho Ryu, Taejoo Chang, Sangjin Lee 0002	High-Speed RSA Crypto-processor with Radix-4 Modular Multiplication and Chinese Remainder Theorem.	ICISC	2006	DBLP DOI BibTeX RDF	Booth’s algorithm, RSA, Chinese Remainder Theorem, Montgomery multiplication, Carry Save Adder
46	Tong Zhou, Mingyan Yu, Yizheng Ye	A Pipelined Switched-Current Chaotic System for the High-Speed Truly Random Number Generation in Crypto Processor.	VLSI Design	2006	DBLP DOI BibTeX RDF
46	W. P. Choi, Lee-Ming Cheng	Modelling the Crypto-Processor from Design to Synthesis.	CHES	1999	DBLP DOI BibTeX RDF
36	Jinkeun Hong, Kihong Kim, Dongcheul Son	The Design of Random Number Generator in an Embedded Crypto Module.	ISPA Workshops	2006	DBLP DOI BibTeX RDF
36	Yongxin Ma, Xiaoyang Zeng, Min Wu, Chengshou Sun	A new low cost and reconfigurable RSA crypto-processor.	ISCAS	2006	DBLP DOI BibTeX RDF
36	Lilian Bossuet, Michael Grand, Lubos Gaspar, Viktor Fischer, Guy Gogniat	Architectures of flexible symmetric key crypto engines - a survey: From hardware coprocessor to multi-crypto-processor system on chip.	ACM Comput. Surv.	2013	DBLP DOI BibTeX RDF
28	Alireza Hodjat, Ingrid Verbauwhede	Area-Throughput Trade-Offs for Fully Pipelined 30 to 70 Gbits/s AES Processors.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	crypto-processor, security, VLSI, cryptography, Advanced Encryption Standard (AES), ASIC, hardware architectures
28	Alireza Hodjat, David Hwang 0001, Bo-Cheng Lai, Kris Tiri, Ingrid Verbauwhede	A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-µm CMOS technology.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	crypto-processor, security, FPGA, VLSI, cryptography, advanced encryption standard (AES), ASIC, hardware architectures
22	Nadine Buard, Florent Miller, Cédric Ruby, Rémi Gaillard	Latchup effect in CMOS IC: a solution for crypto-processors protection against fault injection attacks?	IOLTS	2007	DBLP DOI BibTeX RDF
21	Vu Trung Duong Le, Hoai-Luan Pham, Thi Hong Tran, Yasuhiko Nakashima	Flexible and Energy-Efficient Crypto-Processor for Arbitrary Input Length Processing in Blockchain-Based IoT Applications.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2024	DBLP DOI BibTeX RDF
21	Xiang Li, Jiahao Lu, Dongsheng Liu, Aobo Li, Shuo Yang, Tianze Huang	A High Speed Post-Quantum Crypto-Processor for Crystals-Dilithium.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
21	Yihong Zhu, Wenping Zhu, Yi Ouyang, Junwen Sun, Min Zhu 0001, Qi Zhao, Jinjiang Yang, Chen Chen, Qichao Tao, Guang Yang, Aoyang Zhang, Shaojun Wei, Leibo Liu	16.2 A 28nm 69.4kOPS 4.4μJ/Op Versatile Post-Quantum Crypto-Processor Across Multiple Mathematical Problems.	ISSCC	2024	DBLP DOI BibTeX RDF
21	Yihong Zhu, Wenping Zhu, Chongyang Li, Min Zhu 0001, Chenchen Deng, Chen Chen 0083, Shuying Yin, Shouyi Yin, Shaojun Wei, Leibo Liu	RePQC: A 3.4-uJ/Op 48-kOPS Post-Quantum Crypto-Processor for Multiple-Mathematical Problems.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
21	Murugesan Kalaiarasi, Vepadappu Raman Venkatasubramani, M. S. K. Manikandan, S. Rajaram 0001	High performance HITA based Binary Edward Curve Crypto processor for FPGA platforms.	J. Parallel Distributed Comput.	2023	DBLP DOI BibTeX RDF
21	Jihye Lee, Whijin Kim, Ji-Hoon Kim	A Programmable Crypto-Processor for National Institute of Standards and Technology Post-Quantum Cryptography Standardization Based on the RISC-V Architecture.	Sensors	2023	DBLP DOI BibTeX RDF
21	Aobo Li, Jiahao Lu, Dongsheng Liu, Xiang Li, Shuo Yang, Tianze Huang, Jiaming Zhang, Siqi Xiong, Chenjun Yang	A 40nm $\boldsymbol{2.76}\boldsymbol{\mu}\mathbf{J}/\mathbf{Op}$ Energy-Efficient Secure Post-Quantum Crypto-Processor for Crystals-Kyber on Module-LWE.	A-SSCC	2023	DBLP DOI BibTeX RDF
21	Murugesan Kalaiarasi, Vepadappu Raman Venkatasubramani, V. Vinoth Thyagarajan, S. Rajaram 0001	A parallel elliptic curve crypto-processor architecture with reduced clock cycle for FPGA platforms.	J. Supercomput.	2022	DBLP DOI BibTeX RDF
21	Utsav Banerjee, Anantha P. Chandrakasan	A Low-Power BLS12-381 Pairing Crypto-Processor for Internet-of-Things Security Applications.	CoRR	2022	DBLP BibTeX RDF
21	Yihong Zhu, Wenping Zhu, Min Zhu 0001, Chongyang Li, Chenchen Deng, Chen Chen 0083, Shuying Yin, Shouyi Yin, Shaojun Wei, Leibo Liu	A 28nm 48KOPS 3.4µJ/Op Agile Crypto-Processor for Post-Quantum Cryptography on Multi-Mathematical Problems.	ISSCC	2022	DBLP DOI BibTeX RDF
21	Muhammad Kashif, Ihsan Çiçek	Field-programmable gate array (FPGA) hardware design and implementation of a new area efficient elliptic curve crypto-processor.	Turkish J. Electr. Eng. Comput. Sci.	2021	DBLP DOI BibTeX RDF
21	Raghavan Kumar, Xiaosen Liu, Vikram B. Suresh, Harish K. Krishnamurthy, Sudhir Satpathy, Mark A. Anders 0001, Himanshu Kaul, Krishnan Ravichandran, Vivek De, Sanu K. Mathew	A Time-/Frequency-Domain Side-Channel Attack Resistant AES-128 and RSA-4K Crypto-Processor in 14-nm CMOS.	IEEE J. Solid State Circuits	2021	DBLP DOI BibTeX RDF
21	Yang Su, Bai-Long Yang, Chen Yang, Jing-Yuan He	High-flexible hardware and instruction of composite Galois field multiplication targeted at symmetric crypto processor.	J. Ambient Intell. Humaniz. Comput.	2021	DBLP DOI BibTeX RDF
21	Muhammad Rashid	Corrigendum: Throughput/area optimised pipelined architecture for elliptic curve crypto processor.	IET Comput. Digit. Tech.	2021	DBLP DOI BibTeX RDF
21	Yihong Zhu, Min Zhu 0001, Bohan Yang 0004, Wenping Zhu, Chenchen Deng, Chen Chen 0083, Shaojun Wei, Leibo Liu	LWRpro: An Energy-Efficient Configurable Crypto-Processor for Module-LWR.	IEEE Trans. Circuits Syst. I Regul. Pap.	2021	DBLP DOI BibTeX RDF
21	Utsav Banerjee, Anantha P. Chandrakasan	A Low-Power Elliptic Curve Pairing Crypto-Processor for Secure Embedded Blockchain and Functional Encryption.	CICC	2021	DBLP DOI BibTeX RDF
21	Ryohei Nakayama, Makoto Ikeda	BN-254 Based Multi-Core, Multi-Pairing Crypto-Processor for Functional Encryption.	ISCAS	2021	DBLP DOI BibTeX RDF
21	Aiqing Wu, Mengni Bie, Longmei Nan, Wei Li 0131	Effective Register Allocation for Configurable VLIW Crypto-Processor.	ASICON	2021	DBLP DOI BibTeX RDF
21	Luis Cavo, Sebastien Fuhrmann, Liang Liu 0002	Design of an area efficient crypto processor for 3GPP-LTE NB-IoT devices.	Microprocess. Microsystems	2020	DBLP DOI BibTeX RDF
21	Raghavan Kumar, Sudhir Satpathy, Vikram B. Suresh, Mark A. Anders 0001, Himanshu Kaul, Vivek De, Sanu Mathew	A 435MHz, 2.5Mbps/W Side-Channel-Attack Resistant Crypto-Processor for Secure RSA-4K Public-Key Encryption in 14nm CMOS.	VLSI Circuits	2020	DBLP DOI BibTeX RDF
21	Utsav Banerjee, Siddharth Das, Anantha P. Chandrakasan	Accelerating Post-Quantum Cryptography using an Energy-Efficient TLS Crypto-Processor.	ISCAS	2020	DBLP DOI BibTeX RDF
21	Piljoo Choi, Ji-Hoon Kim, Dong Kyue Kim	Fast and Power-Analysis Resistant Ring Lizard Crypto-Processor Based on the Sparse Ternary Property.	IEEE Access	2019	DBLP DOI BibTeX RDF
21	Hiromitsu Awano, Tadayuki Ichihashi, Makoto Ikeda	An ASIC Crypto Processor for 254-Bit Prime-Field Pairing Featuring Programmable Arithmetic Core Optimized for Quadratic Extension Field.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2019	DBLP DOI BibTeX RDF
21	Malik Imran, Muhammad Rashid, Atif Raza Jafri, Muhammad Kashif	Throughput/area optimised pipelined architecture for elliptic curve crypto processor.	IET Comput. Digit. Tech.	2019	DBLP DOI BibTeX RDF
21	Utsav Banerjee, Tenzin S. Ukyab, Anantha P. Chandrakasan	Sapphire: A Configurable Crypto-Processor for Post-Quantum Lattice-based Protocols.	CoRR	2019	DBLP BibTeX RDF
21	Utsav Banerjee, Tenzin S. Ukyab, Anantha P. Chandrakasan	Sapphire: A Configurable Crypto-Processor for Post-Quantum Lattice-based Protocols.	IACR Trans. Cryptogr. Hardw. Embed. Syst.	2019	DBLP DOI BibTeX RDF
21	Utsav Banerjee, Tenzin S. Ukyab, Anantha P. Chandrakasan	Sapphire: A Configurable Crypto-Processor for Post-Quantum Lattice-based Protocols (Extended Version).	IACR Cryptol. ePrint Arch.	2019	DBLP BibTeX RDF
21	Malik Imran, Muhammad Rashid, Atif Raza Jafri, Muhammad Najam-ul-Islam	ACryp-Proc: Flexible Asymmetric Crypto Processor for Point Multiplication.	IEEE Access	2018	DBLP DOI BibTeX RDF
21	Shotaro Sugiyama, Hiromitsu Awano, Makoto Ikeda	Low Latency 256-bit $mathbb{F}_p$ ECDSA Signature Generation Crypto Processor.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2018	DBLP DOI BibTeX RDF
21	Leibo Liu, Bo Wang 0023, Chenchen Deng, Min Zhu 0001, Shouyi Yin, Shaojun Wei	Anole: A Highly Efficient Dynamically Reconfigurable Crypto-Processor for Symmetric-Key Algorithms.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2018	DBLP DOI BibTeX RDF
21	Hai Huang, Bin Yu, Zhiwei Liu, Rui Weng, Junfeng Gao, Mingyuan Ren	DPA countermeasures for reconfigurable crypto processor using non-deterministic execution.	IEICE Electron. Express	2018	DBLP DOI BibTeX RDF
21	Anastasios N. Bikos, Nicolas Sklavos 0001	Architecture Design of an Area Efficient High Speed Crypto Processor for 4G LTE.	IEEE Trans. Dependable Secur. Comput.	2018	DBLP DOI BibTeX RDF
21	Luis Cavo, Sebastien Fuhrmann, Liang Liu 0002	Implementation of an Area Efficient Crypto Processor for a NB-IoT SoC Platform.	NORCAS	2018	DBLP DOI BibTeX RDF
21	G. Leelavathi, K. Shaila, K. R. Venugopal 0001	Elliptic Curve Crypto Processor on FPGA using Montgomery Multiplication with Vedic and Encoded Multiplier over GF (2m) for Nodes in Wireless Sensor Networks.	ICIIS	2018	DBLP DOI BibTeX RDF
21	G. Leelavathi, K. Shaila, K. R. Venugopal 0001	Implementation of Public Key Crypto Processor with Probabilistic Encryption on FPGA for Nodes in Wireless Sensor Networks.	ICCCNT	2018	DBLP DOI BibTeX RDF
21	Fatma Kahri, Hassen Mestiri, Belgacem Bouallegue, Mohsen Machhout	High Speed FPGA Implementation of Cryptographic KECCAK Hash Function Crypto-Processor.	J. Circuits Syst. Comput.	2016	DBLP DOI BibTeX RDF
21	Peter T. Breuer, Jonathan P. Bowen	A First Practical Fully Homomorphic Crypto-Processor Design: The Secret Computer is Nearly Here.	CoRR	2015	DBLP BibTeX RDF
21	Jun Han 0003, Renfeng Dou, Lingyun Zeng, Shuai Wang, Zhiyi Yu, Xiaoyang Zeng	A Heterogeneous Multicore Crypto-Processor With Flexible Long-Word-Length Computation.	IEEE Trans. Circuits Syst. I Regul. Pap.	2015	DBLP DOI BibTeX RDF
21	Simon Pontie, Paolo Maistri, Régis Leveugle	An Elliptic Curve Crypto-Processor Secured by Randomized Windows.	DSD	2014	DBLP DOI BibTeX RDF
21	Hassan Anwar, Masoud Daneshtalab, Masoumeh Ebrahimi, Juha Plosila, Hannu Tenhunen, Sergei Dytckov, Giovanni Beltrame	Parameterized AES-Based Crypto Processor for FPGAs.	DSD	2014	DBLP DOI BibTeX RDF
21	Christopher Pöpper, Oliver Mischke, Tim Güneysu	MicroACP - A Fast and Secure Reconfigurable Asymmetric Crypto-Processor - -Overhead Evaluation of Side-Channel Countermeasures-.	ARC	2014	DBLP DOI BibTeX RDF
21	Peter T. Breuer, Jonathan P. Bowen	Idea: Towards a Working Fully Homomorphic Crypto-processor - Practice and the Secret Computer.	ESSoS	2014	DBLP DOI BibTeX RDF
21	Kirat Pal Singh, Dilip Kumar 0008	Performance Evaluation of Low Power MIPS Crypto Processor based on Cryptography Algorithms.	CoRR	2013	DBLP BibTeX RDF
21	Qasem Abu Al-Haija, Ahmad Al Badawi	Cost-effective design for binary Edwards elliptic curves crypto-processor over GF (2N) using parallel multipliers and architectures.	Int. J. Inf. Comput. Secur.	2013	DBLP DOI BibTeX RDF
21	Hassan Anwar, Masoud Daneshtalab, Masoumeh Ebrahimi, Juha Plosila, Hannu Tenhunen	FPGA implementation of AES-based crypto processor.	ICECS	2013	DBLP DOI BibTeX RDF
21	Peter T. Breuer, Jonathan P. Bowen	A Fully Homomorphic Crypto-Processor Design.	ESSoS	2013	DBLP DOI BibTeX RDF
21	Jianzhou Li, Hua Li, Wei Dong	Design of an Efficient Hybrid Crypto-Processor.	Int. J. Comput. Their Appl.	2012	DBLP BibTeX RDF
21	Goran Panic, Thomas Basmer, Schomann Henry, Steffen Peter, Frank Vater, Klaus Tittelbach-Helmrich	Design of a sensor node crypto processor for IEEE 802.15.4 applications.	SoCC	2012	DBLP DOI BibTeX RDF
21	Peter T. Breuer, Jonathan P. Bowen	Typed Assembler for a RISC Crypto-Processor.	ESSoS	2012	DBLP DOI BibTeX RDF
21	Michal Varchola, Tim Güneysu, Oliver Mischke	MicroECC: A Lightweight Reconfigurable Elliptic Curve Crypto-processor.	ReConFig	2011	DBLP DOI BibTeX RDF
21	Reza Faghih Mirzaee, Mohammad Eshghi	Design of an ASIP IDEA crypto processor.	NESEA	2011	DBLP DOI BibTeX RDF
21	Michael Grand, Lilian Bossuet, Bertrand Le Gal, Guy Gogniat, Dominique Dallet	Design and Implementation of a Multi-Core Crypto-Processor for Software Defined Radios.	ARC	2011	DBLP DOI BibTeX RDF
21	Hamid Reza Ahmadi, Ali Afzali-Kusha, Massoud Pedram	A power-optimized low-energy elliptic-curve crypto-processor.	IEICE Electron. Express	2010	DBLP DOI BibTeX RDF
21	Lubos Gaspar, Viktor Fischer, Florent Bernard, Lilian Bossuet, Pascal Cotret	HCrypt: A Novel Concept of Crypto-processor with Secured Key Management.	ReConFig	2010	DBLP DOI BibTeX RDF
21	Gaetan Canivet, P. Maistn, Régis Leveugle, Frédéric Valette, Jessy Clédière, Marc Renaudin	Robustness evaluation and improvements under laser-based fault attacks of an AES crypto-processor implemented on a SRAM-based FPGA.	ETS	2010	DBLP DOI BibTeX RDF
21	Hamid Reza Ahmadi, Ali Afzali-Kusha	Very Low-power Flexible GF(p) Elliptic-curve Crypto-processor for Non-time-critical Applications.	ISCAS	2009	DBLP DOI BibTeX RDF
21	Yannick Monnet, Marc Renaudin, Régis Leveugle, Nathalie Feyt, Pascal Moitrel, F. M'Buwa Nzenguet	Practical Evaluation of Fault Countermeasures on an Asynchronous DES Crypto Processor.	IOLTS	2006	DBLP DOI BibTeX RDF
21	G. Fraidy Bouesse, Marc Renaudin, Adrien Witon, Fabien Germain	A clock-less low-voltage AES crypto-processor.	ESSCIRC	2005	DBLP DOI BibTeX RDF
21	Yibo Fan, Xiaoyang Zeng, Zhang Zhang, Jun Chen, Qianling Zhang	VLSI design of a high-speed RAS crypto-processor with reconfigurable architecture.	ISSPA	2005	DBLP DOI BibTeX RDF
21	Ho Won Kim 0001, Sunggu Lee	Design and implementation of a private and public key crypto processor and its application to a security system.	IEEE Trans. Consumer Electron.	2004	DBLP DOI BibTeX RDF
21	Rainer Buchty, Nevin Heintze, Dino Oliva	Cryptonite - A Programmable Crypto Processor Architecture for High-Bandwidth Applications.	ARCS	2004	DBLP DOI BibTeX RDF
21	Rainer Buchty	Modelling Cryptonite - On the Design of a Programmable High-Performance Crypto Processor.	ARCS Workshops	2004	DBLP BibTeX RDF
21	Nicolas Sklavos 0001, Georgios N. Selimis, Odysseas G. Koufopavlou	Bulk encryption crypto-processor for smart cards: design and implementation.	ICECS	2004	DBLP DOI BibTeX RDF
21	Sheikh Muhammad Farhan	High Data Rate 8-Bit Crypto Processor.	ISSA	2004	DBLP BibTeX RDF
21	YunKyung Lee, Sangwoo Lee, Youngsae Kim	AES Crypto-Processor Design Supporting 128/192/256 Bits Input Key Length for Smart Card.	ESA/VLSI	2004	DBLP BibTeX RDF
21	Ming-Cheng Sun, Chih-Pin Su, Chih-Tsun Huang, Cheng-Wen Wu	Design of a scalable RSA and ECC crypto-processor.	ASP-DAC	2003	DBLP DOI BibTeX RDF
21	Adnan Abdul-Aziz Gutub	VLSI core architecture for GF(p) elliptic curve crypto processor.	ICECS	2003	DBLP DOI BibTeX RDF
21	Dino Oliva, Rainer Buchty, Nevin Heintze	AES and the cryptonite crypto processor.	CASES	2003	DBLP DOI BibTeX RDF	round key generation, architecture, cryptography, AES, processor, high-speed, software implementation, high-bandwidth
21	Pak-Keung Leung, Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun	A low power asynchronous GF(2173) ALU for elliptic curve crypto-processor.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
21	Rainer Buchty	Cryptonite: a programmable crypto processor architecture for high bandwidth applications.		2002	RDF
12	Chester Rebeiro, Debdeep Mukhopadhyay	High Speed Compact Elliptic Curve Cryptoprocessor for FPGA Platforms.	INDOCRYPT	2008	DBLP DOI BibTeX RDF
12	Hyun-Sung Kim 0001, Sung-Woon Lee	Semi-systolic Modular Multiplier over GF(2m).	ICCSA (2)	2008	DBLP DOI BibTeX RDF
12	Yannick Monnet, Marc Renaudin, Régis Leveugle	Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	quasi-delay insensitive, hardening techniques, Asynchronous circuits, data encryption standard, fault attacks
12	Hyun-Sung Kim 0001, Sung-Woon Lee	Low Complexity Systolic Architecture for Modular Multiplication over GF(2m).	International Conference on Computational Science (1)	2006	DBLP DOI BibTeX RDF
12	G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin	Path Swapping Method to Improve DPA Resistance of Quasi Delay Insensitive Asynchronous Circuits.	CHES	2006	DBLP DOI BibTeX RDF	QDI Asynchronous circuits, Path Swapping (PS), Power analysis
12	G. Fraidy Bouesse, Marc Renaudin, Gilles Sicard	Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
12	G. Fraidy Bouesse, Marc Renaudin, Sophie Dumont, Fabien Germain	DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement.	DATE	2005	DBLP DOI BibTeX RDF
12	Kris Tiri, Ingrid Verbauwhede	A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation.	DATE	2004	DBLP DOI BibTeX RDF
12	Nam-Yeun Kim, Dae-Ghon Kho, Kee-Young Yoo	Inversion/Division Systolic Architecture for Public-Key Cryptosystems in GF(2m).	ISC	2002	DBLP DOI BibTeX RDF
12	Fabio Ancona, Alessandro De Gloria, Rodolfo Zunino	Parallel VLSI Architectures for Cryptographic Systems.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF