Search results for "decimal"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
177	Mahesh Bhat, John Crawford, Ricardo Morin, Kumar Shiv	Performance Characterization of Decimal Arithmetic in Commercial Java Workloads.	ISPASS	2007	DBLP DOI BibTeX RDF	software decimal implementations, commercial Java workloads, binary floating-point numbers, special decimal representations, optimized hardware support, decimal math, BigDecimal class, scale manipulation, SPECjbb2005, SPECjAppServer2004, mission-critical financial workload, Trade Completion, hashing, performance characterization, decimal arithmetic, format conversion
156	Liang-Kai Wang, Michael J. Schulte	Decimal Floating-Point Adder and Multifunction Unit with Injection-Based Rounding.	IEEE Symposium on Computer Arithmetic	2007	DBLP DOI BibTeX RDF
119	Marius Cornea, John Harrison 0001, Cristina Anderson, Ping Tak Peter Tang, Eric Schneider, Evgeny Gvozdev	A Software Implementation of the IEEE 754R Decimal Floating-Point Arithmetic Using the Binary Encoding Format.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
119	Marius Cornea, Cristina Anderson, John Harrison 0001, Ping Tak Peter Tang, Eric Schneider, Charles Tsen	A Software Implementation of the IEEE 754R Decimal Floating-Point Arithmetic Using the Binary Encoding Format.	IEEE Symposium on Computer Arithmetic	2007	DBLP DOI BibTeX RDF
119	Mark A. Erle, Michael J. Schulte, Brian J. Hickmann	Decimal Floating-Point Multiplication Via Carry-Save Addition.	IEEE Symposium on Computer Arithmetic	2007	DBLP DOI BibTeX RDF
112	Dongdong Chen 0002, Younhee Choi, Li Chen, Daniel Teng, Khan A. Wahid, Seok-Bum Ko	A novel decimal-to-decimal logarithmic converter.	ISCAS	2008	DBLP DOI BibTeX RDF
112	Amir Kaivani, Ali Zakerolhosseini, Saeid Gorgin 0001, Mahmood Fazlali	Reversible Implementation of Densely-Packed-Decimal Converter to and from Binary-Coded-Decimal Format Using in IEEE-754R.	ICIT	2006	DBLP DOI BibTeX RDF
106	Jeff Rebacz, Erdal Oruklu, Jafar Saniie	High performance signed-digit decimal adders.	EIT	2009	DBLP DOI BibTeX RDF
106	Horácio C. Neto, Mário P. Véstias	Decimal multiplier on FPGA using embedded binary multipliers.	FPL	2008	DBLP DOI BibTeX RDF
106	Brian J. Hickmann, Michael J. Schulte, Mark A. Erle	Improved combined binary/decimal fixed-point multipliers.	ICCD	2008	DBLP DOI BibTeX RDF
106	Liang-Kai Wang, Michael J. Schulte	Decimal Floating-Point Square Root Using Newton-Raphson Iteration.	ASAP	2005	DBLP DOI BibTeX RDF
106	Michael F. Cowlishaw	Decimal Floating-Point: Algorism for Computers.	IEEE Symposium on Computer Arithmetic	2003	DBLP DOI BibTeX RDF
106	Mark A. Erle, Michael J. Schulte	Decimal Multiplication Via Carry-Save Addition.	ASAP	2003	DBLP DOI BibTeX RDF
106	Michael F. Cowlishaw, Eric M. Schwarz, Ronald M. Smith, Charles F. Webb	A Decimal Floating-Point Specification.	IEEE Symposium on Computer Arithmetic	2001	DBLP DOI BibTeX RDF
102	Liang-Kai Wang, Michael J. Schulte	A Decimal Floating-Point Divider Using Newton-Raphson Iteration.	J. VLSI Signal Process.	2007	DBLP DOI BibTeX RDF	Newton-Raphson iteration, initial approximation, computer arithmetic, floating-point, division, hardware design, decimal
102	Robert D. Kenney, Michael J. Schulte	High-Speed Multioperand Decimal Adders.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	multioperand adders, Computer arithmetic, hardware designs, decimal arithmetic
94	Brian J. Hickmann, Andrew Krioukov, Michael J. Schulte, Mark A. Erle	A parallel IEEE P754 decimal floating-point multiplier.	ICCD	2007	DBLP DOI BibTeX RDF
89	Luigi Dadda	Multioperand Parallel Decimal Adder: A Mixed Binary and BCD Approach.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	multioperand adders, Computer arithmetic, hardware design, decimal arithmetic
81	Liang-Kai Wang, Michael J. Schulte, John D. Thompson, Nandini Jairam	Hardware Designs for Decimal Floating-Point Addition and Related Operations.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
81	Álvaro Vázquez, Elisardo Antelo, Paolo Montuschi	A New Family of High.Performance Parallel Decimal Multipliers.	IEEE Symposium on Computer Arithmetic	2007	DBLP DOI BibTeX RDF
81	Ivan D. Castellanos, James E. Stine	A 64-bit Decimal Floating-Point Comparator.	ASAP	2006	DBLP DOI BibTeX RDF
81	Robert D. Kenney, Michael J. Schulte, Mark A. Erle	A High-Frequency Decimal Multiplier.	ICCD	2004	DBLP DOI BibTeX RDF
81	Liang-Kai Wang, Michael J. Schulte	Decimal Floating-Point Division Using Newton-Raphson Iteration.	ASAP	2004	DBLP DOI BibTeX RDF
81	Álvaro Vázquez, Elisardo Antelo, Paolo Montuschi	Improved Design of High-Performance Parallel Decimal Multipliers.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	Decimal multiplication, decimal carry-save addition, decimal codings, parallel multiplication
68	Merav Aharoni, Ron Maharik, Abraham Ziv	Solving Constraints on the Intermediate Result of Decimal Floating-Point Operations.	IEEE Symposium on Computer Arithmetic	2007	DBLP DOI BibTeX RDF
68	John Moskal, Erdal Oruklu, Jafar Saniie	Design and Synthesis of a Carry-Free Signed-Digit Decimal Adder.	ISCAS	2007	DBLP DOI BibTeX RDF
68	John D. Thompson, Nandini Karra, Michael J. Schulte	A 64-bit Decimal Floating-Point Adder.	ISVLSI	2004	DBLP DOI BibTeX RDF
64	Ivan D. Castellanos, James E. Stine	Compressor trees for decimal partial product reduction.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	VLSI, decimal arithmetic
63	Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas	Novel, High-Speed 16-Digit BCD Adders Conforming to IEEE 754r Format.	ISVLSI	2007	DBLP DOI BibTeX RDF
60		A Research and Design of Decimal Floating Multiplier Based on FPGA.	WKDD	2010	DBLP DOI BibTeX RDF	Decimal floating multiplier, DPD codec, BCD new codec, Signed-Digit radix-5, Decimal 32:2 CSA
56	José Luis Sánchez, Higinio Mora Mora, Jerónimo Mora Pascual, Antonio Jimeno	Architecture implementation of an improved decimal CORDIC method.	ICCD	2008	DBLP DOI BibTeX RDF
56	Charles Tsen, Sonia González-Navarro, Michael J. Schulte	Hardware design of a Binary Integer Decimal-based floating-point adder.	ICCD	2007	DBLP DOI BibTeX RDF
56	Robert D. Kenney, Michael J. Schulte	Multioperand Decimal Addition.	ISVLSI	2004	DBLP DOI BibTeX RDF
54	Tomás Lang, Alberto Nannarelli	A Radix-10 Digit-Recurrence Division Unit: Algorithm and Architecture.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	decimal division, algorithms and architectures for floating-point arithmetic, Decimal arithmetic, digit-recurrence division
50	Luigi Dadda, Alberto Nannarelli	A variant of a radix-10 combinational multiplier.	ISCAS	2008	DBLP DOI BibTeX RDF
50	Álvaro Vázquez, Elisardo Antelo, Paolo Montuschi	A radix-10 SRT divider based on alternative BCD codings.	ICCD	2007	DBLP DOI BibTeX RDF
50	Clinton R. Foulk	Macintosh assembly language.	ACM Conference on Computer Science	1988	DBLP DOI BibTeX RDF	Macintosh
50	Vincent J. DiGri, Jane E. King	The Share 709 System: Input-Output Translation.	J. ACM	1959	DBLP DOI BibTeX RDF
46	Xiaohu Li, Haifeng Du, Jian Zhuang, Sunan Wang	A PID Parameters Tuning Algorithm Inspired by the Small World Phenomenon.	ICIC (1)	2008	DBLP DOI BibTeX RDF	PID Parameters Tuning, Decimal-Coding, Small World Phenomenon
43	Charles Tsen, Sonia González-Navarro, Michael J. Schulte, Brian J. Hickmann, Katherine Compton	A Combined Decimal and Binary Floating-Point Multiplier.	ASAP	2009	DBLP DOI BibTeX RDF
43	Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura	On Designs of Radix Converters Using Arithmetic Decompositions--Binary to Decimal Converters--.	ISMVL	2007	DBLP DOI BibTeX RDF
43	Josh Dehlinger, Meredith Humphrey, Lada Suvorov, Prasanna Padmanabhan, Robyn R. Lutz	DECIMAL and PLFaultCAT: From Product-Line Requirements to Product-Line Member Software Fault Trees.	ICSE Companion	2007	DBLP DOI BibTeX RDF
43	Hooman Nikmehr, Braden Phillips, Cheng-Chew Lim	Fast Decimal Floating-Point Division.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
43	Mark A. Erle, Eric M. Schwarz, Michael J. Schulte	Decimal Multiplication with Efficient Partial Product Generation.	IEEE Symposium on Computer Arithmetic	2005	DBLP DOI BibTeX RDF
43	Cees-Bart Breunesse, Bart Jacobs 0001, Joachim van den Berg	Specifying and Verifying a Decimal Representation in Java for Smart Cards.	AMAST	2002	DBLP DOI BibTeX RDF
39	Dilip Kumar Gayen, Arunava Bhattacharyya, Chinmoy Taraphdar, Rajat Kumar Pal, Jitendra Nath Roy	All-Optical Binary-Coded Decimal Adder with a Terahertz Optical Asymmetric Demultiplexer.	Comput. Sci. Eng.	2011	DBLP DOI BibTeX RDF	Terahertz optical asymmetric demultiplexer, optical full adder, optical binary-coded decimal adder, optical switch
39	Mário P. Véstias, Horácio C. Neto	Revisiting the Newton-Raphson Iterative Method for Decimal Division.	FPL	2011	DBLP DOI BibTeX RDF	FPGA computing, decimal arithmetic
39	Malte Baesler, Thomas Teufel	FPGA Implementation of a Decimal Floating-Point Accurate Scalar Product Unit with a Parallel Fixed-Point Multiplier.	ReConFig	2009	DBLP DOI BibTeX RDF	decimal multiplier, IEEE 754-2008, accurate scalar product, FPGA, floating point
39	Martín Vázquez 0001, Gustavo Sutter, Gery Bioul, Jean-Pierre Deschamps	Decimal Adders/Subtractors in FPGA: Efficient 6-input LUT Implementations.	ReConFig	2009	DBLP DOI BibTeX RDF	BCD, add/subtract, addtion, FPGA, subtraction, decimal arithmetic
39	C. K. Yuen	A New Representation for Decimal Numbers.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	negative bases, number systems, Decimal arithmetic
38	Florian Loitsch	Printing floating-point numbers quickly and accurately with integers.	PLDI	2010	DBLP DOI BibTeX RDF	dtoa, floating-point printing
38	Tomás Lang, Alberto Nannarelli	Division Unit for Binary Integer Decimals.	ASAP	2009	DBLP DOI BibTeX RDF
38	William D. Clinger	How to read floating point numbers accurately (with retrospective)	Best of PLDI	1990	DBLP DOI BibTeX RDF
38	W. E. Milne, R. R. Reynolds	Stability of a Numerical Solution of Differential Equations.	J. ACM	1959	DBLP DOI BibTeX RDF
36	Saranya Karunamurthi, Vijeyakumar Krishnasamy Natarajan	A Novel n-Decimal Reversible Radix Binary-Coded Decimal Multiplier Using Radix Encoding Scheme.	Circuits Syst. Signal Process.	2021	DBLP DOI BibTeX RDF
36	Mário P. Véstias, Horácio C. Neto	Decimal Multiplication in FPGA with a Novel Decimal Adder/Subtractor.	Algorithms	2021	DBLP DOI BibTeX RDF
36	Shuli Gao, Dhamin Al-Khalili, J. M. Pierre Langlois, Noureddine Chabini	Decimal floating-point multiplier with binary-decimal compression based fixed-point multiplier.	CCECE	2017	DBLP DOI BibTeX RDF
36	Xiao-Ping Cui, Weiqiang Liu 0001, Dong Wenwen, Fabrizio Lombardi	A Parallel Decimal Multiplier Using Hybrid Binary Coded Decimal (BCD) Codes.	ARITH	2016	DBLP DOI BibTeX RDF
36	Ch. Santosh Varma, Syed Ershad Ahmed, M. B. Srinivas	A Decimal/Binary Multi-operand Adder Using a Fast Binary to Decimal Converter.	VLSID	2014	DBLP DOI BibTeX RDF
36	Osama Daifallah Al-Khaleel, Zakaria Al-Qudah, Mohammad Al-Khaleel, Christos A. Papachristou	High performance FPGA-based decimal-to-binary conversion schemes for decimal arithmetic.	Microprocess. Microsystems	2013	DBLP DOI BibTeX RDF
36	Ahmet Akkas, Michael J. Schulte	A decimal floating-point fused multiply-add unit with a novel decimal leading-zero anticipator.	ASAP	2011	DBLP DOI BibTeX RDF
36	Saeid Gorgin 0001, Ghassem Jaberipur	A fully redundant decimal adder and its application in parallel decimal multipliers.	Microelectron. J.	2009	DBLP DOI BibTeX RDF
36	Liang-Kai Wang, Michael J. Schulte	A Decimal Floating-Point Adder with Decoded Operands and a Decimal Leading-Zero Anticipator.	IEEE Symposium on Computer Arithmetic	2009	DBLP DOI BibTeX RDF
36	Michael J. Anderson, Chuck Tsen, Liang-Kai Wang, Katherine Compton, Michael J. Schulte	Performance analysis of decimal floating-point libraries and its impact on decimal hardware and software solutions.	ICCD	2009	DBLP DOI BibTeX RDF
36	Noriaki Muranaka, Shigeru Imanishi, D. Michael Miller	Decimal Addition and Subtraction Units Using the p-Valued Decimal Signed-Digit Number Representation.	ISMVL	1993	DBLP DOI BibTeX RDF
36	Winfried Auzinger, Hans J. Stetter	Accurate arithmetic results for decimal data on non-decimal computers.	Computing	1985	DBLP DOI BibTeX RDF
36	D. Horelick	Comment on "Serial Binary-to-Decimal and Decimal-to-Binary Conversion".	IEEE Trans. Computers	1971	DBLP DOI BibTeX RDF
36	V. Thomas Rhyne	Serial Binary-to-Decimal and Decimal-to-Binary Conversion.	IEEE Trans. Computers	1970	DBLP DOI BibTeX RDF
36	John E. Croy	Rapid Technique of Manual or Machine Binary-to-Decimal Integer Conversion Using Decimal Radix Arithmetic.	IRE Trans. Electron. Comput.	1961	DBLP DOI BibTeX RDF
36	Donald Taranto	Binary Conversion, With Fixed Decimal Precision, Of a Decimal Fraction.	Commun. ACM	1959	DBLP DOI BibTeX RDF
36	John F. Couleur	BIDEC - A Binary-to-Decimal or Decimal-to-Binary Converter.	IRE Trans. Electron. Comput.	1958	DBLP DOI BibTeX RDF
33	Koraljka Golub, Jim Moon, Douglas Tudhope, Catherine Mary Jones, Brian Matthews, Bartlomiej Puzon, Marianne Lykke Nielsen	EnTag: enhancing social tagging for discovery.	JCDL	2009	DBLP DOI BibTeX RDF	ACM computing classification scheme, dewey decimal classification, intute, subject indexing, folksonomies, social tagging, controlled vocabularies, institutional repository, digital collection
33	Charles F. Webb	IBM z10: The Next-Generation Mainframe Microprocessor.	IEEE Micro	2008	DBLP DOI BibTeX RDF	high-frequency design, decimal floating-point, reliability, pipeline, microprocessor, branch prediction, accelerators, symmetric multiprocessor (SMP), mainframe, Hot Chips 19
33	Jun Wang, Meng Chen Lee	Reconstructing ddc for interactive classification.	CIKM	2007	DBLP DOI BibTeX RDF	bibliographic data, dewey decimal classification, interactive classification, taxonomy reconstruction, trimming machine, hierarchical classification
33	Zixing Cai, Zhihong Peng	Cooperative Coevolutionary Adaptive Genetic Algorithm in Path Planning of Cooperative Multi-Mobile Robot Systems.	J. Intell. Robotic Syst.	2002	DBLP DOI BibTeX RDF	multi-mobile robot systems, cooperative coevolutionary adaptive genetic algorithm, fixed-length decimal encoding mechanism, multi-agent systems, path planning
33	Brigitte Verdonk, Annie A. M. Cuyt, Dennis Verschaeren	A precision- and range-independent tool for testing floating-point arithmetic II: conversions.	ACM Trans. Math. Softw.	2001	DBLP DOI BibTeX RDF	IEEE floating-point standard, multiprecision, validation, conversion, floating-point, arithmetic, decimal
33	Tetsuji Imajo, Tatsuki Miyake, Shinobu Sato, Toshiyuki Ito, Daisuke Yokotsuka, Yoshihide Tsujihata, Shunsuke Uemura	COBOL Script: A Business-Oriented Scripting Language.	EDOC	2000	DBLP DOI BibTeX RDF	COBOL Script, business-oriented scripting language, Web-oriented script language, language specifications, COBOL85, decimal arithmetic functions, COBOL processing system, account-related applications, test debugger, large-scale development projects, COBOL, business information systems, Web computing
31		Dewey Decimal Classification.	Encyclopedia of Database Systems	2009	DBLP DOI BibTeX RDF
31	Liang-Kai Wang, Charles Tsen, Michael J. Schulte, Divya Jhalani	Benchmarks and performance analysis of decimal floating-point applications.	ICCD	2007	DBLP DOI BibTeX RDF
31	Ulrike Reiner	Automatic Analysis of Dewey Decimal Classification Notations.	GfKl	2007	DBLP DOI BibTeX RDF
31	Hafiz Md. Hasan Babu, Ahsan Raja Chowdhury	Design of a Reversible Binary Coded Decimal Adder by Using Reversible 4-Bit Parallel Adder.	VLSI Design	2005	DBLP DOI BibTeX RDF
31	Gerald M. Weinberg	Programmed error correction on a decimal computer.	Commun. ACM	1961	DBLP DOI BibTeX RDF
25	Sreehari Veeramachaneni, Kirthi M. Krishna, Prateek G. V., Subroto S., Bharat S., M. B. Srinivas	A Novel Carry-Look Ahead Approach to a Unified BCD and Binary Adder/Subtractor.	VLSI Design	2008	DBLP DOI BibTeX RDF
25	Himanshu Thapliyal, Saurabh Kotiyal, M. B. Srinivas	Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format.	VLSI Design	2006	DBLP DOI BibTeX RDF
25	Prasanna Padmanabhan, Robyn R. Lutz	Tool-Supported Verification of Product Line Requirements.	Autom. Softw. Eng.	2005	DBLP DOI BibTeX RDF	requirements verification, feature-interaction resolution, variability, product line, consistency checking, product family, dependency constraints
25	Lena Pareto	Graphical arithmetic for learners with dyscalculia.	ASSETS	2005	DBLP DOI BibTeX RDF	dyscalculia, math disability, graphical model, arithmetic
25	Fadi Busaba, Timothy J. Slegel, Steven R. Carlough, Christopher A. Krygowski, John G. Rell	The design of the fixed point unit for the z990 microprocessor.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	superscalar FXU, microprocessor
25	Oliver Benedens	Affine Invariant Watermarks for 3D Polygonal and NURBS Based Models.	ISW	2000	DBLP DOI BibTeX RDF
25	Richard P. Brent	Recent Progress and Prospects for Integer Factorisation Algorithms.	COCOON	2000	DBLP DOI BibTeX RDF
25	Richard P. Brent	Some Parallel Algorithms for Integer Factorisation.	Euro-Par	1999	DBLP DOI BibTeX RDF
25	William D. Clinger	How to Read Floating-Point Numbers Accurately.	PLDI	1990	DBLP DOI BibTeX RDF
25	Donald W. Davies	A Message Authenticator Algorithm Suitable for A Mainframe Computer.	CRYPTO	1984	DBLP DOI BibTeX RDF
25	John W. Carr III, James W. Hanson	Two subroutines for symbol manipulation with an algebraic compiler.	Commun. ACM	1961	DBLP DOI BibTeX RDF
25	Ronald E. Prather	Computational Aids for Determining the Minimal Form of a Truth Function.	J. ACM	1960	DBLP DOI BibTeX RDF
21	Nikunja Swain, Mrutyunjaya Swain	Design and development of computer networking modules using virtual instruments and object oriented programming.	SIGITE Conference	2004	DBLP DOI BibTeX RDF	IP classes, dotted decimal notation, java/visual basic, router forwarding, subnet & subnet mask, TCP/IP, virtual instruments, routing table
18	Marcelo Tosini, Martín Vázquez 0001, Lucas Leiva	Analysis and efficient implementation of IEEE-754 decimal floating point adders/subtractors in FPGAs for DPD and BID encoding.	J. Supercomput.	2024	DBLP DOI BibTeX RDF
18	Zahra Yazdanian Amiri, Mojtaba Valinataj	High-speed binary coded decimal digit multipliers with multiple error detection.	Integr.	2023	DBLP DOI BibTeX RDF
18	Muhamed F. Mudawar	Exact Versus Inexact Decimal Floating-Point Numbers and Arithmetic.	IEEE Access	2023	DBLP DOI BibTeX RDF
18	Huy Anh Nguyen, Hayden Stec, Xinying Hou, Sarah Di, Bruce M. McLaren	Evaluating ChatGPT's Decimal Skills and Feedback Generation in a Digital Learning Game.	CoRR	2023	DBLP DOI BibTeX RDF
18	Ilyse Resnick, Nora S. Newcombe, Micah B. Goldwater	Reasoning about fraction and decimal magnitudes, reasoning proportionally, and mathematics achievement in Australia and the United States.	J. Numer. Cogn.	2023	DBLP DOI BibTeX RDF