Search results for "deinterleaver"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
56	László Horváth, Imed Ben Dhaou, Hannu Tenhunen, Jouni Isoaho	A novel, high-speed, reconfigurable demapper-symbol deinterleaver architecture for DVB-T.	ISCAS (4)	1999	DBLP DOI BibTeX RDF
49	Stevan M. Berber, Xinghua Zhan	Reverse CDMA link based on noise-like spreading sequences and fading mitigation.	IWCMC	2009	DBLP DOI BibTeX RDF	noise based CDMA, noise-like sequences, non-binary spreading sequences, probability of error derivation
49	Michael K. Cheng, Bruce E. Moision, Jon Hamkins, Michael A. Nakashima	An interleaver implementation for the serially concatenated pulse-position modulation decoder.	ISCAS	2006	DBLP DOI BibTeX RDF
49	Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto	Reconfigurable adaptive FEC system with interleaving.	ASP-DAC	2005	DBLP DOI BibTeX RDF
36	Amin Ansari, Keyvan Amiri	Flexible FPGA-based parallel architecture for identification of repetitive sequences in interleaved pulse trains.	FPGA	2008	DBLP DOI BibTeX RDF	deinterleaver, pulse train, FPGA, parallel architecture
32	Gwonhan Mun, Hee Wook Kim, Daeho Kim	CNPC deinterleaver implementation to increase hardware logic utilization on FPGA.	ICAIIC	2021	DBLP DOI BibTeX RDF
32	J. Magdalene Mathana, S. Badrinarayanan, Rani Hemamalini	VLSI Architecture for High Performance 3GPP Interleaver/Deinterleaver for Turbo Codes.	Int. J. Comput. Commun. Control	2014	DBLP DOI BibTeX RDF
32	Omar Rafique	Area Versus Speed Trade-off Analysis of a WiMAX Deinterleaver Circuit Design.	CoRR	2014	DBLP BibTeX RDF
32	Omar Rafique, Gangadharaiah S. L	Hardware Efficient WiMAX Deinterleaver Capable of Address Generation for Random Interleaving Depths.	CoRR	2014	DBLP BibTeX RDF
32	Hyeong-Ju Kang, Hee Suk Seo, Jin Kwak	Area-efficient convolutional deinterleaver for mobile TV receiver.	ACM Trans. Embed. Comput. Syst.	2013	DBLP DOI BibTeX RDF
32	Bijoy Kumar Upadhyaya, Salil Kumar Sanyal	Efficient FPGA Implementation of Address Generator for WiMAX Deinterleaver.	IEEE Trans. Circuits Syst. II Express Briefs	2013	DBLP DOI BibTeX RDF
32	Arash Ardakani, Mojtaba Mahdavi, Mahdi Shabany	An efficient VLSI architecture of QPP interleaver/deinterleaver for LTE turbo coding.	ISCAS	2013	DBLP DOI BibTeX RDF
32	Zhen-dong Zhang, Bin Wu 0006, Yumei Zhou, Xin Zhang	Low-Complexity Hardware Interleaver/Deinterleaver for IEEE 802.11a/g/n WLAN.	VLSI Design	2012	DBLP DOI BibTeX RDF
32	Hyeong-Ju Kang, Byung-Do Yang	Low-Power Time Deinterleaver for ISDB-T Receiver.	IEEE Trans. Circuits Syst. II Express Briefs	2012	DBLP DOI BibTeX RDF
32	Hamid Reza Tanhaei, Mojtaba Rezaee	An area-efficient symbol deinterleaver architecture for DVB-T.	SiPS	2011	DBLP DOI BibTeX RDF
32	Yun-Nan Chang	A Multibank Memory-Based VLSI Architecture of DVB Symbol Deinterleaver.	IEEE Trans. Very Large Scale Integr. Syst.	2010	DBLP DOI BibTeX RDF
32	Hector Borrayo-Sandoval, Ramón Parra-Michel, Luis F. Gonzalez-Perez, Fernando Landeros Printzen, Claudia Feregrino Uribe	Design and Implementation of a Configurable Interleaver/Deinterleaver for Turbo Codes in 3GPP Standard.	ReConFig	2009	DBLP DOI BibTeX RDF	configurable, interleaver, Turbo codes
32	Yun-Nan Chang	A low-cost dual-mode deinterleaver design.	IEEE Trans. Consumer Electron.	2008	DBLP DOI BibTeX RDF
32	A. Mark Earnshaw, Steven D. Blostein	A combined soft-decision deinterleaver/decoder for the IS95 reverse link.	IEEE Trans. Veh. Technol.	2000	DBLP DOI BibTeX RDF
25	Tjerk Bijlsma, Marco Bekooij, Pierre G. Jansen, Gerard J. M. Smit	Communication between nested loop programs via circular buffers in an embedded multiprocessor system.	SCOPES	2008	DBLP DOI BibTeX RDF
25	Yu Zhu 0002, Khaled Ben Letaief	Single Carrier Frequency Domain Equalization with Time Domain Noise Prediction for Wideband Wireless Communications.	IEEE Trans. Wirel. Commun.	2006	DBLP DOI BibTeX RDF