Search results for "direct-mapped"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
61	Yau-Tsun Steven Li, Sharad Malik, Andrew Wolfe	Cache modeling for real-time software: beyond direct mapped instruction caches.	RTSS	1996	DBLP DOI BibTeX RDF	direct mapped instruction caches, worst case timing analysis, cache hits, set associative instruction caches, unified caches, cinderella, research, integer-linear-programming, worst case execution time, data caches, cache storage, design tool, memory performance, cache misses, real-time software, tight bound, cache modeling, hardware system
54	Chuanjun Zhang	Balanced Cache: Reducing Conflict Misses of Direct-Mapped Caches.	ISCA	2006	DBLP DOI BibTeX RDF
53	Dimitrios Stiliadis, Anujan Varma	Selective Victim Caching: A Method to Improve the Performance of Direct-Mapped Caches.	IEEE Trans. Computers	1997	DBLP DOI BibTeX RDF	data cache, instruction cache, cache simulation, Victim cache, direct-mapped cache
47	Brad Calder, Dirk Grunwald, Joel S. Emer	Predictive Sequential Associative Cache.	HPCA	1996	DBLP DOI BibTeX RDF	predictive sequential associative cache, miss rate, prediction sources, storage management, memory architecture, content-addressable storage, access time, direct-mapped cache, access latency
46	Chuanjun Zhang	Balanced instruction cache: reducing conflict misses of direct-mapped caches through balanced subarray accesses.	IEEE Comput. Archit. Lett.	2006	DBLP DOI BibTeX RDF
39	Kenichi Yoshida, Fuminori Adachi, Takashi Washio, Hiroshi Motoda, Teruaki Homma, Akihiro Nakashima, Hiromitsu Fujikawa, Katsuyuki Yamazaki	Density-based spam detector.	KDD	2004	DBLP DOI BibTeX RDF	document space density, unsupervised learning, spam, direct-mapped cache
39	Johnson Kin, Munish Gupta, William H. Mangione-Smith	The Filter Cache: An Energy Efficient Memory Structure.	MICRO	1997	DBLP DOI BibTeX RDF	direct mapped 256-byte filter cache, energy efficient memory structure, on-chip caches, static RAM, microprocessors, microprocessor chips, power reduction, embedded applications, L2 cache, filter cache, L1 cache
39	Craig B. Stunkel, W. Kent Fuchs	An Analysis of Cache Performance for a Hypercube Multicomputer.	IEEE Trans. Parallel Distributed Syst.	1992	DBLP DOI BibTeX RDF	Intel iPSC/2, processornodes, direct-mapped cache performance, application-specific datapartitioning, communication distribution, communication frequency, system accesses, user code, time distribution, message-passing code, performance evaluation, parallel programming, hypercube networks, storage management, buffer storage, parallel application, hypercube multicomputer, code analysis, cache simulation, address traces, data access patterns
38	Chuanjun Zhang	An efficient direct mapped instruction cache for application-specific embedded systems.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	efficient cache design, instruction cache, low power cache
38	Brian N. Bershad, Dennis Lee 0001, Theodore H. Romer, J. Bradley Chen	Avoiding Conflict Misses Dynamically in Large Direct-Mapped Caches.	ASPLOS	1994	DBLP DOI BibTeX RDF
38	Jia-Jhe Li, Yuan-Shin Hwang	Indirect-Mapped Caches: Approximating Set-Associativity with Direct-Mapped Caches.	CDES	2009	DBLP BibTeX RDF
32	Pepijn J. de Langen, Ben H. H. Juurlink	Reducing traffic generated by conflict misses in caches.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	caches, embedded processors, power reduction, conflict misses
32	Ben H. H. Juurlink, Pepijn J. de Langen	Dynamic techniques to reduce memory traffic in embedded systems.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	memory traffic, caches, power consumption, embedded processors
32	Brannon Batson, T. N. Vijaykumar	Reactive-Associative Caches.	IEEE PACT	2001	DBLP DOI BibTeX RDF
31	David C. Wong 0002, Edward W. Davis, Jeffrey O. Young	A Software Approach to Avoiding Spatial Cache Collisions in Parallel Processor Systems.	IEEE Trans. Parallel Distributed Syst.	1998	DBLP DOI BibTeX RDF	Cache collision, cache offset, highly parallel systems, sequential DO-loops, direct-mapped cache
31	Mark D. Hill, Alan Jay Smith	Evaluating Associativity in CPU Caches.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	CPU caches, cache miss ratio, forest simulation, all-associativity simulation, stack simulation, associativity, buffer storage, content-addressable storage, direct-mapped, set-associative
31	James E. Smith, James R. Goodman	Instruction Cache Replacement Policies and Organizations.	IEEE Trans. Computers	1985	DBLP DOI BibTeX RDF	fully associative, loop model, Cache memories, replacement algorithms, memory organization, direct-mapped, set-associative
30	Mirza Omer Beg, Peter van Beek	A graph theoretic approach to cache-conscious placement of data for direct mapped caches.	ISMM	2010	DBLP DOI BibTeX RDF	cache consciousness, data placement in cache, offline algorithms, memory management, cache optimization
30	Raimund Kirner, Peter P. Puschner	Time-Predictable Task Preemption for Real-Time Systems with Direct-Mapped Instruction Cache.	ISORC	2007	DBLP DOI BibTeX RDF
30	Paolo D'Alberto, Alexandru Nicolau, Alexander V. Veidenbaum, Rajesh K. Gupta 0001	Line Size Adaptivity Analysis of Parameterized Loop Nests for Direct Mapped Data Cache.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Cache-line size adaptivity, parameterized loop nests, interference, spatial locality
30	Shmuel Gal, Yona Hollander, Alon Itai	Optimal Mapping in Direct Mapped Cache Environments.	ISTCS	1992	DBLP DOI BibTeX RDF
24	Chuanjun Zhang	Reducing cache misses through programmable decoders.	ACM Trans. Archit. Code Optim.	2008	DBLP DOI BibTeX RDF	low power, Cache, dynamic optimization
24	Yoav Etsion, Dror G. Feitelson	L1 Cache Filtering Through Random Selection of Memory References.	PACT	2007	DBLP DOI BibTeX RDF
24	Jung-Hoon Lee, Seh-Woong Jeong, Shin-Dug Kim, Charles C. Weems	An Intelligent Cache System with Hardware Prefetching for High Performance.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	dual data cache, prefetching, Memory hierarchy, temporal locality, spatial locality
24	Paul Racunas, Yale N. Patt	Partitioned first-level cache design for clustered microarchitectures.	ICS	2003	DBLP DOI BibTeX RDF	partitioned cache, clustered microarchitecture
24	Jung-Hoon Lee, Jang-Soo Lee, Shin-Dug Kim	A Selective Temporal and Aggressive Spatial Cache System Based on Time Interval.	ICCD	2000	DBLP DOI BibTeX RDF
24	Thomas J. Murray 0002, A. Wayne Madison, James Westall	Lookahead page placement.	ACM Southeast Regional Conference	1995	DBLP DOI BibTeX RDF
24	Scott McFarling	Program Optimization for Instruction Caches.	ASPLOS	1989	DBLP DOI BibTeX RDF	RISC
22	Hossein Chalangar, Tarek Ould Bachir, Keyhan Sheshyekani, Jean Mahseredjian	A Direct Mapped Method for Accurate Modeling and Real-Time Simulation of High Switching Frequency Resonant Converters.	IEEE Trans. Ind. Electron.	2021	DBLP DOI BibTeX RDF
22	Hossein Chalangar, Tarek Ould Bachir, Keyhan Sheshyekani, Jean Mahseredjian	A direct mapped method for accurate modeling and real-time simulation of high switching frequency resonant converters.	CoRR	2020	DBLP BibTeX RDF
22	Alaa R. Alameldeen, Rajat Agarwal	Opportunistic compression for direct-mapped DRAM caches.	MEMSYS	2018	DBLP DOI BibTeX RDF
22	Dongwoo Lee, Sang-Heon Lee 0006, Soojung Ryu, Kiyoung Choi	Dirty-Block Tracking in a Direct-Mapped DRAM Cache with Self-Balancing Dispatch.	ACM Trans. Archit. Code Optim.	2017	DBLP DOI BibTeX RDF
22	Noboru Murabayashi, Kenichi Yoshida	Similar video detection using multiple direct-mapped cache.	Int. J. Intell. Syst. Technol. Appl.	2013	DBLP DOI BibTeX RDF
22	Sidharta Andalam, Alain Girault, Roopak Sinha, Partha S. Roop, Jan Reineke 0001	Precise timing analysis for direct-mapped caches.	DAC	2013	DBLP DOI BibTeX RDF
22	Noboru Murabayashi, Kenichi Yoshida	Copied video detection with MPEG-7 video signature and multiple direct-mapped cache.	HIS	2011	DBLP DOI BibTeX RDF
22	Wei Zhang 0002, Jun Yan 0008	Accurately Estimating Worst-Case Execution Time for Multi-core Processors with Shared Direct-Mapped Instruction Caches.	RTCSA	2009	DBLP DOI BibTeX RDF
22	Yi-Cheng Lin, Yi-Ying Tsai, Kuen-Jong Lee, Cheng-Wei Yen, Chung-Ho Chen	A Software-Based Test Methodology for Direct-Mapped Data Cache.	ATS	2008	DBLP DOI BibTeX RDF
22	Nagm Eldin Mohamed, Adil Akaaboune, Nazeih Botros	Lethargic Cache: A Low Leakage Direct Mapped Cache.	J. Low Power Electron.	2007	DBLP DOI BibTeX RDF
22	Carsten Scholtes	A method to derive the cache performance of irregular applications on machines with direct mapped caches.	Int. J. Comput. Sci. Eng.	2005	DBLP DOI BibTeX RDF
22	Carsten Scholtes	Abschätzung der Fehlzugriffe bei dünn besetzten Matrixoperationen auf Architekturen mit einem direct mapped Cache		2003	RDF
22	Ramon Doallo, Basilio B. Fraguela, Emilio L. Zapata	Direct mapped cache performance modeling for sparse matrix operations.	PDP	1999	DBLP DOI BibTeX RDF
22	Sultan M. Al-Harbi, Sandeep K. Gupta 0001	A Methodology for Transforming Memory Tests for In-System Testing of Direct Mapped Cache Tags.	VTS	1998	DBLP DOI BibTeX RDF
22	Norman P. Jouppi	Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache Prefetch Buffers.	25 Years ISCA: Retrospectives and Reprints	1998	DBLP DOI BibTeX RDF
22	Norman P. Jouppi	Retrospective: Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers.	25 Years ISCA: Retrospectives and Reprints	1998	DBLP DOI BibTeX RDF
22	Jude A. Rivers, Edward S. Davidson	Reducing Conflicts in Direct-Mapped Caches with a Temporality-Based Design.	ICPP, Vol. 1	1996	DBLP DOI BibTeX RDF
22	Nathalie Drach, André Seznec, Daniel Windheiser	Direct-mapped versus set-associative pipelined caches.	PACT	1995	DBLP BibTeX RDF
22	Shmuel Gal, Yona Hollander, Alon Itai	Optimal mapping in direct mapped cache environments.	Math. Program.	1994	DBLP DOI BibTeX RDF
22	Dimitrios Stiliadis, Anujan Varma	Selective Victim Caching: A Method to Improve the Performance of Direct-Mapped Caches.	HICSS (1)	1994	DBLP BibTeX RDF
22	Anant Agarwal, Steven D. Pudar	Column-Associative Caches: A Technique for Reducing the Miss Rate of Direct-Mapped Caches.	ISCA	1993	DBLP DOI BibTeX RDF
22	Wen-Hann Wang, Jim Quinlan, Konrad Lai	Revisit the case for direct-mapped chaches: a case for two-way set-associative level-two caches.	ISCA	1992	DBLP DOI BibTeX RDF
22	Norman P. Jouppi	Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers.	ISCA	1990	DBLP DOI BibTeX RDF
22	V. S. Madan, C.-J. Peng, Gurindar S. Sohi	On the Adequacy of Direct Mapped Caches for Lisp and Prolog Data Reference Patterns.	NACLP	1989	DBLP BibTeX RDF
22	Mark D. Hill	A Case for Direct-Mapped Caches.	Computer	1988	DBLP DOI BibTeX RDF
19	Ashutosh Kulkarni, Navin Chander, Soumya Pillai, Lizy Kurian John	Modeling and Analysis of The Difference-Bit Cache.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	hit access time, cache mapping strategies*, Cache memory, critical path
16	Chuanjun Zhang, Frank Vahid, Walid A. Najjar	A highly configurable cache for low energy embedded systems.	ACM Trans. Embed. Comput. Syst.	2005	DBLP DOI BibTeX RDF	embedded systems, low power, Cache, microprocessor, configurable, memory hierarchy, low energy, architecture tuning
16	Jung-Wook Park, Cheong-Ghil Kim, Jung-Hoon Lee, Shin-Dug Kim	An energy efficient cache memory architecture for embedded systems.	SAC	2004	DBLP DOI BibTeX RDF	selective way access, skewed associativity, embedded system, memory hierarchy, low power cache
16	Rui Min, Wen-Ben Jone, Yiming Hu	Location cache: a low-power L2 cache system.	ISLPED	2004	DBLP DOI BibTeX RDF	L1/L2 caches, data location, power, TLB, set-associative caches
16	Chuanjun Zhang, Frank Vahid, Walid A. Najjar	A Highly-Configurable Cache Architecture for Embedded Systems.	ISCA	2003	DBLP DOI BibTeX RDF	embedded systems, low power, Cache, microprocessor, configurable, low energy, architecture tuning
16	Rui Min, Yiming Hu	Improving Performance of Large Physically Indexed Caches by Decoupling Memory Addresses from Cache Addresses.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Novel memory architectures, cache, memory systems, TLB, performance enhancement
16	Stephanie Coleman, Kathryn S. McKinley	Tile Size Selection Using Cache Organization and Data Layout.	PLDI	1995	DBLP DOI BibTeX RDF
16	Richard E. Kessler, Richard Jooss, Alvin R. Lebeck, Mark D. Hill	Inexpensive Implementations of Set-Associativity.	ISCA	1989	DBLP DOI BibTeX RDF
11	Jan Staschulat, Rolf Ernst	Worst case timing analysis of input dependent data cache behavior.	ECRTS	2006	DBLP DOI BibTeX RDF
11	Edouard Bugnion, Jennifer-Ann M. Anderson, Todd C. Mowry, Mendel Rosenblum, Monica S. Lam	Compiler-Directed Page Coloring for Multiprocessors.	ASPLOS	1996	DBLP DOI BibTeX RDF
8	Yu Liu 0037, Wei Zhang 0002	Exploiting stack distance to estimate worst-case data cache performance.	SAC	2009	DBLP DOI BibTeX RDF	stack distance, cache, timing analysis, worst-case execution time
8	Andhi Janapsatya, Sri Parameswaran, Aleksandar Ignjatovic	HitME: low power Hit MEmory buffer for embedded systems.	ASP-DAC	2009	DBLP DOI BibTeX RDF
8	Samir Ammenouche, Sid Ahmed Ali Touati, William Jalby	On Instruction-Level Method for Reducing Cache Penalties in Embedded VLIW Processors.	HPCC	2009	DBLP DOI BibTeX RDF
8	Jongmin Lee 0002, Soontae Kim	An energy-delay efficient 2-level data cache architecture for embedded system.	ISLPED	2009	DBLP DOI BibTeX RDF	2-level data cache, early cache hit predictor, one-way write
8	Kevin Camera, Robert W. Brodersen	An integrated debugging environment for FPGA computing platforms.	FPGA	2008	DBLP DOI BibTeX RDF	simulation, FPGA, design, verification
8	Zhenghong Wang, Ruby B. Lee	A novel cache architecture with enhanced performance and security.	MICRO	2008	DBLP DOI BibTeX RDF
8	Chia-Hsiang Yang, Dejan Markovic	A Flexible VLSI Architecture for Extracting Diversity and Spatial Multiplexing Gains in MIMO Channels.	ICC	2008	DBLP DOI BibTeX RDF
8	Kevin Camera, Robert W. Brodersen	An integrated debugging environment for FPGA computing platforms.	FPL	2008	DBLP DOI BibTeX RDF
8	Hyungmin Cho, Bernhard Egger 0002, Jaejin Lee, Heonshik Shin	Dynamic data scratchpad memory management for a memory subsystem with an MMU.	LCTES	2007	DBLP DOI BibTeX RDF	horizontally-partitioned memory, post-pass optimization, compilers, scratchpad memory, demand paging
8	Rajiv A. Ravindran, Michael L. Chu, Scott A. Mahlke	Compiler-managed partitioned data caches for low power.	LCTES	2007	DBLP DOI BibTeX RDF	hardware/software co-managed cache, instruction-driven cache management, partitioned cache, low-power, embedded processor
8	Fadia Nemer, Hugues Cassé, Pascal Sainrat, Ali Awada	Improving the Worst-Case Execution Time Accuracy by Inter-Task Instruction Cache Analysis.	SIES	2007	DBLP DOI BibTeX RDF
8	Ju-Hyun Kim, Gyoung-Hwan Hyun, Hyuk-Jae Lee	Cache Organizations for H.264/AVC Motion Compensation.	RTCSA	2007	DBLP DOI BibTeX RDF
8	Prasanna Palsodkar, Amol Y. Deshmukh, Preeti R. Bajaj, Avinash G. Keskar	An Approach for Four Way Set Associative Multilevel CMOS Cache Memory.	KES (1)	2007	DBLP DOI BibTeX RDF
8	Kimish Patel, Luca Benini, Enrico Macii, Massimo Poncino	Reducing Conflict Misses by Application-Specific Reconfigurable Indexing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
8	Sumesh Udayakumaran, Angel Dominguez, Rajeev Barua	Dynamic allocation for scratch-pad memory using compile-time decisions.	ACM Trans. Embed. Comput. Syst.	2006	DBLP DOI BibTeX RDF	embedded systems, compiler, Memory allocation, software caching, scratch pad, software-managed cache
8	Hoon-Mo Yang, Gi-Ho Park, Shin-Dug Kim	Low-Power Data Cache Architecture by Address Range Reconfiguration for Multimedia Applications.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF	embedded system, low-power, multimedia application, cache architecture
8	Samuel Rodríguez, Bruce L. Jacob	Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm).	ISLPED	2006	DBLP DOI BibTeX RDF	nanometer design, pipelined caches, cache design
8	Allan Hartstein, Viji Srinivasan, Thomas R. Puzak, Philip G. Emma	Cache miss behavior: is it sqrt(2)?	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	performance, memory hierarchy, cache organization
8	Jan Staschulat, Rolf Ernst	Scalable precision cache analysis for preemptive scheduling.	LCTES	2005	DBLP DOI BibTeX RDF	scheduling, embedded systems, cache, worst case execution time analysis
8	Kenichi Yoshida, Fuminori Adachi, Takashi Washio, Hiroshi Motoda, Teruaki Homma, Akihiro Nakashima, Hiromitsu Fujikawa, Katsuyuki Yamazaki	Memory Management of Density-Based Spam Detector.	SAINT	2005	DBLP DOI BibTeX RDF
8	Kaustubh Patil, Kiran Seth, Frank Mueller 0001	Compositional static instruction cache simulation.	LCTES	2004	DBLP DOI BibTeX RDF	scheduling, real-time systems, caches, worst-case execution time
8	Chuanjun Zhang, Frank Vahid	Using a Victim Buffer in an Application-Specific Memory Hierarchy.	DATE	2004	DBLP DOI BibTeX RDF
8	Chi F. Chen, Se-Hyun Yang, Babak Falsafi, Andreas Moshovos	Accurate and Complexity-Effective Spatial Pattern Prediction.	HPCA	2004	DBLP DOI BibTeX RDF
8	Kimish Patel, Enrico Macii, Luca Benini, Massimo Poncino	Reducing cache misses by application-specific re-configurable indexing.	ICCAD	2004	DBLP DOI BibTeX RDF
8	Christophe Guillon, Fabrice Rastello, Thierry Bidault, Florent Bouchez	Procedure placement using temporal-ordering information: dealing with code size expansion.	CASES	2004	DBLP DOI BibTeX RDF	min-matching, profiling, instruction cache, Hamiltonian-path, cache miss, code size, code placement
8	Sriram Nadathur, Akhilesh Tyagi	IPC Driven Dynamic Associative Cache Architecture for Low Energy.	ICCD	2004	DBLP DOI BibTeX RDF
8	Jung-Wook Park, Gi-Ho Park, Sung-Bae Park, Shin-Dug Kim	Power-Aware Deterministic Block Allocation for Low-Power Way-Selective Cache Structure.	ICCD	2004	DBLP DOI BibTeX RDF
8	Cheol Hong Kim, Jong Wook Kwak, Seong Tae Jhang, Chu Shik Jhon	Adaptive Block Management for Victim Cache by Exploiting L1 Cache History Information.	EUC	2004	DBLP DOI BibTeX RDF	Block Management, Low Power, Computer Architecture, Victim Cache
8	John Y. Fong, Randy Acklin, John Roscher, Feng Li, Cindy Laird, Cezary Pietrzyk	Nonvolatile Repair Caches Repair Embedded SRAM and New Nonvolatile Memories.	DFT	2004	DBLP DOI BibTeX RDF
8	Pavel Tvrdík, Ivan Simecek	Performance Optimization and Evaluation for Linear Codes.	NAA	2004	DBLP DOI BibTeX RDF
8	A. P. Shanthi, P. Muruganandam, Ranjani Parthasarathi	Enhancing the Development Based Evolution of Digital Circuits.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
8	Rui Min, Zhiyong Xu, Yiming Hu, Wen-Ben Jone	Partial Tag Comparison: A New Technology for Power-Efficient Set-Associative Cache Designs.	VLSI Design	2004	DBLP DOI BibTeX RDF
8	Kurt Mehlhorn, Peter Sanders 0001	Scanning Multiple Sequences Via Cache Memory.	Algorithmica	2003	DBLP DOI BibTeX RDF
8	Jung-Hoon Lee, Gi-Ho Park, Shin-Dug Kim	An Adaptive Multi-Module Cache with Hardware Prefetching Mechanism for Multimedia Applications.	PDP	2003	DBLP DOI BibTeX RDF
8	Maria Grigoriadou, Maria Toula, Evangelos Kanidis	Design and Evaluation of a Cache Memory Simulation Program.	ICALT	2003	DBLP DOI BibTeX RDF
8	Pavel Tvrdík, Ivan Simecek	Analytical Modeling of Optimized Sparse Linear Code.	PPAM	2003	DBLP DOI BibTeX RDF
8	Jung-Hoon Lee, Shin-Dug Kim, Charles C. Weems	Application-adaptive intelligent cache memory system.	ACM Trans. Embed. Comput. Syst.	2002	DBLP DOI BibTeX RDF	dynamic block fetching and cache memory, general application, media application, Memory hierarchy, temporal locality, spatial locality