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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 9 occurrences of 9 keywords
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Results
Found 16 publication records. Showing 16 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
75 | Swarnalatha Radhakrishnan, Hui Guo 0001, Sri Parameswaran |
Dual-pipeline heterogeneous ASIP design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2004, Stockholm, Sweden, September 8-10, 2004, pp. 12-17, 2004, ACM, 1-58113-937-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
dual-pipeline, instruction set generation, ASIP, superscalar |
22 | Yuu Tanaka, Toshinori Sato, Takenori Koushiro |
The potential in energy efficiency of a speculative chip-multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPAA ![In: SPAA 2004: Proceedings of the Sixteenth Annual ACM Symposium on Parallelism in Algorithms and Architectures, June 27-30, 2004, Barcelona, Spain, pp. 273-274, 2004, ACM, 1-58113-840-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
dual pipeline, energy efficiency, speculative multithreading |
19 | Hua Qin, Weihong Chen, Buwen Cao, Min Zeng, Jessica Li, Yang Peng |
DIPS: Dual-Interface Dual-Pipeline Scheduling for Energy-Efficient Multihop Communications in IoT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Internet Things J. ![In: IEEE Internet Things J. 6(1), pp. 718-733, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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15 | Weirong Jiang, Viktor K. Prasanna |
Large-scale wire-speed packet classification on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 219-228, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
fpga, decision tree, pipeline, sram, packet classification |
14 | Fengwei Gu, Jun Lu, Chengtao Cai, Qidan Zhu, Zhaojie Ju |
Repformer: a robust shared-encoder dual-pipeline transformer for visual tracking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Neural Comput. Appl. ![In: Neural Comput. Appl. 35(28), pp. 20581-20603, October 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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14 | Shiqi Jiang |
Color and Texture Dual Pipeline Lightweight Style Transfer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2310.01321, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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14 | Yu Chen, Shuai Zheng, Menglong Jin, Yan Chang, Nianyi Wang |
DualFluidNet: an Attention-based Dual-pipeline Network for Accurate and Generalizable Fluid-solid Coupled Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2312.16867, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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14 | Shiqi Jiang, Junjie Kang, Yujian Li |
Dual Pipeline Style Transfer with Input Distribution Differentiation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2311.05432, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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14 | Shuaitao Zhao, Kun Liu 0016, Yuhang Huang, Qian Bao, Dan Zeng 0001, Wu Liu |
DPIT: Dual-Pipeline Integrated Transformer for Human Pose Estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2209.02431, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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14 | Shuaitao Zhao, Kun Liu 0016, Yuhang Huang, Qian Bao, Dan Zeng 0001, Wu Liu |
DPIT: Dual-Pipeline Integrated Transformer for Human Pose Estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICAI (2) ![In: Artificial Intelligence - Second CAAI International Conference, CICAI 2022, Beijing, China, August 27-28, 2022, Revised Selected Papers, Part II, pp. 559-576, 2022, Springer, 978-3-031-20499-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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14 | Ying Kang, Cong Liu, Ning Wang, Dianxi Shi, Ning Zhou, Mengmeng Li, Yunlong Wu |
Siamese Visual Tracking with Dual-Pipeline Correlated Fusion Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Inf. Syst. ![In: IEICE Trans. Inf. Syst. 104-D(10), pp. 1702-1711, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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14 | Xiang Li 0064, Jing Li, Yazhou Zhang, Prayag Tiwari |
Emotion Recognition from Multi-channel EEG Data through A Dual-pipeline Graph Attention Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BIBM ![In: IEEE International Conference on Bioinformatics and Biomedicine, BIBM 2021, Houston, TX, USA, December 9-12, 2021, pp. 3642-3647, 2021, IEEE, 978-1-6654-0126-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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14 | Pedro Lara-Benítez, Manuel Carranza-García, Jorge García-Gutiérrez, José C. Riquelme |
Asynchronous dual-pipeline deep learning framework for online data stream classification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. Comput. Aided Eng. ![In: Integr. Comput. Aided Eng. 27(2), pp. 101-119, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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14 | T. Gokulan, Akshay Muraleedharan, Kuruvilla Varghese |
Design of a 32-bit, dual pipeline superscalar RISC-V processor on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 23rd Euromicro Conference on Digital System Design, DSD 2020, Kranj, Slovenia, August 26-28, 2020, pp. 340-343, 2020, IEEE, 978-1-7281-9535-3. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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14 | You Wu 0005, Guo-Ping Liu 0003 |
Dual pipeline pressure synchronous-coordinated control with the assistance of the golden section control method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Syst. Sci. ![In: Int. J. Syst. Sci. 49(11), pp. 2318-2327, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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10 | George Kornaros, Theofanis Orphanoudakis, Nicholaos Zervos |
An Efficient Implementation of Fair Load Balancing over Multi-CPU SOC Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), Architectures, Methods and Tools, 3-5 September 2003, Belek-Antalya, Turkey, pp. 197-205, 2003, IEEE Computer Society, 0-7695-2003-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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