Search results for "fixed-outline"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
98	Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng	A novel fixed-outline floorplanner with zero deadspace for hierarchical design.	ICCAD	2008	DBLP DOI BibTeX RDF	floorplanner, soft modules, zero deadspace, fixed-outline
86	Song Chen 0001, Takeshi Yoshimura	A stable fixed-outline floorplanning method.	ISPD	2007	DBLP DOI BibTeX RDF	floorplanning, sequence pair, fixed-outline
84	Ou He, Sheqin Dong, Jinian Bian, Yuchun Ma, Xianlong Hong	An effective buffer planning algorithm for IP based fixed-outline SOC placement.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	buffer planning, very large scale integration (VLSI), floorplanning, fixed-outline
81	Rong Liu, Sheqin Dong, Xianlong Hong	Fixed-outline floorplanning based on common subsequence.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	common subsequence, floorplanning, fixed-outline
72	Jackey Z. Yan, Chris Chu	DeFer: deferred decision making enabled fixed-outline floorplanner.	DAC	2008	DBLP DOI BibTeX RDF	deferred decision making, floorplanning, fixed outline
53	Song Chen 0001, Takeshi Yoshimura	Fixed-Outline Floorplanning: Block-Position Enumeration and a New Method for Calculating Area Costs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
53	Chaomin Luo, Miguel F. Anjos, Anthony Vannelli	A nonlinear optimization methodology for VLSI fixed-outline floorplanning.	J. Comb. Optim.	2008	DBLP DOI BibTeX RDF	Circuit layout design, VLSI floorplanning, Facility layout, Combinatorial optimization, Global optimization, Convex programming
50	Chang-Tzu Lin, De-Sheng Chen, Yiwen Wang 0003, Hsin-Hsien Ho	Modem floorplanning with abutment and fixed-outline constraints.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
50	Saurabh N. Adya, Igor L. Markov	Fixed-outline floorplanning: enabling hierarchical design.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
43	Rong Liu, Sheqin Dong, Xianlong Hong, Yoji Kajitani	Fixed-outline floorplanning with constraints through instance augmentation.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
41	Chang-Tzu Lin, De-Sheng Chen, Yiwen Wang 0003	Robust fixed-outline floorplanning through evolutionary search.	ASP-DAC	2004	DBLP DOI BibTeX RDF
38	Chaomin Luo, Miguel F. Anjos, Anthony Vannelli	Large-scale fixed-outline floorplanning design using convex optimization techniques.	ASP-DAC	2008	DBLP DOI BibTeX RDF
34	Tung-Chieh Chen, Yao-Wen Chang	Modern Floorplanning Based on B*-Tree and Fast Simulated Annealing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
34	Tung-Chieh Chen, Yao-Wen Chang	Modern floorplanning based on fast simulated annealing.	ISPD	2005	DBLP DOI BibTeX RDF	simulated annealing, floorplanning
31	De-Yu Liu, Wai-Kei Mak, Ting-Chi Wang	Temperature-constrained fixed-outline floorplanning for die-stacking system-in-package design.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	wire bonding, floorplanning, system-in-package
31	Shaojun Wei, Sheqin Dong, Xianlong Hong, Youliang Wu	On handling the fixed-outline constraints of floorplanning using less flexibility first principles.	ISCAS	2006	DBLP DOI BibTeX RDF
23	De-Xuan Zou, Gai-Ge Wang, Arun Kumar Sangaiah, Xiangyong Kong	A memory-based simulated annealing algorithm and a new auxiliary function for the fixed-outline floorplanning with soft blocks.	J. Ambient Intell. Humaniz. Comput.	2024	DBLP DOI BibTeX RDF
23	Jai-Ming Lin, Tsung-Lin Tsai, Tsung-Chun Tsai	Multilevel Fixed-Outline Component Placement and Graph-Based Ball Assignment for System in Package.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
23	Wenbo Guan, Xiaoyan Tang, Hongliang Lu, Yuming Zhang, Yimen Zhang	Thermal-Aware Fixed-Outline 3-D IC Floorplanning: An End-to-End Learning-Based Approach.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
23	Wenbo Guan, Xiaoyan Tang, Hongliang Lu, Yuming Zhang, Yimen Zhang	A Novel Thermal-Aware Floorplanning and TSV Assignment With Game Theory for Fixed-Outline 3-D ICs.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
23	Ximeng Li 0005, Keyu Peng, Fuxing Huang, Wenxing Zhu	PeF: Poisson's Equation-Based Large-Scale Fixed-Outline Floorplanning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
23	Fuxing Huang, Duanxiang Liu, Xingquan Li, Bei Yu 0001, Wenxing Zhu	Handling Orientation and Aspect Ratio of Modules in Electrostatics-Based Large Scale Fixed-Outline Floorplanning.	ICCAD	2023	DBLP DOI BibTeX RDF
23	J. Shanthi, D. Gracia Nirmala Rani, S. Rajaram 0001	An Enhanced Memetic Algorithm using SKB tree representation for fixed-outline and temperature driven non-slicing floorplanning.	Integr.	2022	DBLP DOI BibTeX RDF
23	Shimin Du, Yang Runping, Yuejun Zhang, Yu Shenglu	A stable voltage island-driven floorplanning with fixed-outline constraint for low power SoC.	Microelectron. J.	2022	DBLP DOI BibTeX RDF
23	Ximeng Li 0005, Keyu Peng, Fuxing Huang, Wenxing Zhu	PeF: Poisson's Equation Based Large-Scale Fixed-Outline Floorplanning.	CoRR	2022	DBLP DOI BibTeX RDF
23	Pengli Ji, Kun He 0001, Zhengli Wang, Yan Jin 0005, Jigang Wu	A Quasi-Newton-based Floorplanner for fixed-outline floorplanning.	Comput. Oper. Res.	2021	DBLP DOI BibTeX RDF
23	Jai-Ming Lin, Wei-Yi Chang, Hao-Yuan Hsieh, Ya-Ting Shyu, Yeong-Jar Chang, Juin-Ming Lu	Thermal-Aware Floorplanning and TSV-Planning for Mixed-Type Modules in a Fixed-Outline 3-D IC.	IEEE Trans. Very Large Scale Integr. Syst.	2021	DBLP DOI BibTeX RDF
23	Jai-Ming Lin, Tai-Ting Chen, Hao-Yuan Hsieh, Ya-Ting Shyu, Yeong-Jar Chang, Juin-Ming Lu	Thermal-Aware Fixed-Outline Floorplanning Using Analytical Models With Thermal-Force Modulation.	IEEE Trans. Very Large Scale Integr. Syst.	2021	DBLP DOI BibTeX RDF
23	Suchandra Banerjee, Suchismita Roy	Thermal-Driven Floorplanning for Fixed Outline Layouts.	J. Circuits Syst. Comput.	2021	DBLP DOI BibTeX RDF
23	Zhipeng Huang 0009, Zhifeng Lin, Ziran Zhu, Jianli Chen	An Improved Simulated Annealing Algorithm With Excessive Length Penalty for Fixed-Outline Floorplanning.	IEEE Access	2020	DBLP DOI BibTeX RDF
23	M. Shunmugathammal, C. Christopher Columbus, S. Anand	A Novel B*tree Crossover-Based Simulated Annealing Algorithm for Combinatorial Optimization in VLSI Fixed-Outline Floorplans.	Circuits Syst. Signal Process.	2020	DBLP DOI BibTeX RDF
23	Tianming Ni, Hao Chang, Shidong Zhu, Lin Lu, Xueyun Li, Qi Xu, Huaguo Liang, Zhengfeng Huang	Temperature-Aware Floorplanning for Fixed-Outline 3D ICs.	IEEE Access	2019	DBLP DOI BibTeX RDF
23	Qian Chen, Sheqin Dong	A Novel Mixed-Size Fixed-Outline Floorplacement Algorithm.	ISVLSI	2018	DBLP DOI BibTeX RDF
23	Jai-Ming Lin, Tai-Ting Chen, Yen-Fu Chang, Wei-Yi Chang, Ya-Ting Shyu, Yeong-Jar Chang, Juin-Ming Lu	A fast thermal-aware fixed-outline floorplanning methodology based on analytical models.	ICCAD	2018	DBLP DOI BibTeX RDF
23	Behnam Khodabandeloo, Ahmad Khonsari, Masoomeh Jasemi, Golnaz Taheri	A fast temperature-aware fixed-outline floorplanning framework using convex optimization.	Integr.	2017	DBLP DOI BibTeX RDF
23	Qi Xu, Song Chen 0001	Fast thermal analysis for fixed-outline 3D floorplanning.	Integr.	2017	DBLP DOI BibTeX RDF
23	Pengli Ji, Kun He 0001, Yan Jin 0005, Hongsheng Lan, Chumin Li	An iterative merging algorithm for soft rectangle packing and its extension for application of fixed-outline floorplanning of soft modules.	Comput. Oper. Res.	2017	DBLP DOI BibTeX RDF
23	Jai-Ming Lin, Jung-An Yang	Routability-Driven TSV-Aware Floorplanning Methodology for Fixed-Outline 3-D ICs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2017	DBLP DOI BibTeX RDF
23	De-Xuan Zou, Gaige Wang, Gai Pan, Hongwei Qin	A modified simulated annealing algorithm and an excessive area model for floorplanning using fixed-outline constraints.	Frontiers Inf. Technol. Electron. Eng.	2016	DBLP DOI BibTeX RDF
23	Qi Xu, Song Chen 0001, Bin Li 0025	Combining the ant system algorithm and simulated annealing for 3D/2D fixed-outline floorplanning.	Appl. Soft Comput.	2016	DBLP DOI BibTeX RDF
23	Jai-Ming Lin, Po-Yang Chiu, Yen-Fu Chang	SAINT: handling module folding and alignment in fixed-outline floorplans for 3D ICs.	ICCAD	2016	DBLP DOI BibTeX RDF
23	Jai-Ming Lin, Chih-Yao Hu, Kai-Chung Chan	Routability-driven floorplanning algorithm for mixed-size modules with fixed-outline constraint.	VLSI-DAT	2015	DBLP DOI BibTeX RDF
23	Chyi-Shiang Hoo, Kanesan Jeevan, Harikrishnan Ramiah	Enumeration technique in very large-scale integration fixed-outline floorplanning.	IET Circuits Devices Syst.	2014	DBLP DOI BibTeX RDF
23	Jai-Ming Lin, Ji-Heng Wu	F-FM: Fixed-Outline Floorplanning Methodology for Mixed-Size Modules Considering Voltage-Island Constraint.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2014	DBLP DOI BibTeX RDF
23	Kun He 0001, Pengli Ji, Chumin Li	An iterative merging placement algorithm for the fixed-outline floorplanning.	CoRR	2014	DBLP BibTeX RDF
23	Wenxu Sheng, Sheqin Dong	Multi-bend bus-driven floorplanning considering fixed-outline constraints.	Integr.	2013	DBLP DOI BibTeX RDF
23	Cha-Ru Li, Wai-Kei Mak, Ting-Chi Wang	Fast Fixed-Outline 3-D IC Floorplanning With TSV Co-Placement.	IEEE Trans. Very Large Scale Integr. Syst.	2013	DBLP DOI BibTeX RDF
23	Jackey Z. Yan, Chris Chu	SDS: An Optimal Slack-Driven Block Shaping Algorithm for Fixed-Outline Floorplanning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2013	DBLP DOI BibTeX RDF
23	Kai-Chung Chan, Chao-Jam Hsu, Jia-Ming Lin	A flexible fixed-outline floorplanning methodology for mixed-size modules.	ASP-DAC	2013	DBLP DOI BibTeX RDF
23	Jai-Ming Lin, Zhi-Xiong Hung	SKB-Tree: A Fixed-Outline Driven Representation for Modern Floorplanning Problems.	IEEE Trans. Very Large Scale Integr. Syst.	2012	DBLP DOI BibTeX RDF
23	Mohammad A. Ahmed, Shantesh Pinge, Malgorzata Chrzanowska-Jeske	Fast floorplanning for fixed-outline and nonrectangular regions.	ICECS	2012	DBLP DOI BibTeX RDF
23	Jackey Z. Yan, Chris Chu	Optimal slack-driven block shaping algorithm in fixed-outline floorplanning.	ISPD	2012	DBLP DOI BibTeX RDF
23	Jai-Ming Lin, Zhi-Xiong Hung	UFO: Unified Convex Optimization Algorithms for Fixed-Outline Floorplanning Considering Pre-Placed Modules.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2011	DBLP DOI BibTeX RDF
23	Song Chen 0001, Takeshi Yoshimura	Multi-layer floorplanning for stacked ICs: Configuration number and fixed-outline constraints.	Integr.	2010	DBLP DOI BibTeX RDF
23	Jackey Z. Yan, Chris Chu	DeFer: Deferred Decision Making Enabled Fixed-Outline Floorplanning Algorithm.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2010	DBLP DOI BibTeX RDF
23	Jai-Ming Lin, Hsi Hung	UFO: unified convex optimization algorithms for fixed-outline floorplanning.	ASP-DAC	2010	DBLP DOI BibTeX RDF
23	Linfu Xiao, Subarna Sinha, Jingyu Xu, Evangeline F. Y. Young	Fixed-outline thermal-aware 3D floorplanning.	ASP-DAC	2010	DBLP DOI BibTeX RDF
23	Wenxu Sheng, Sheqin Dong, Yuliang Wu, Satoshi Goto	Fixed outline multi-bend bus driven floorplanning.	ISQED	2010	DBLP DOI BibTeX RDF
23	Baofang Chang, Wu Jigang, Thambipillai Srikanthan, Lian Li	A Novel Approach for Multilevel Fixed Outline Floorplanning.	PAAP	2010	DBLP DOI BibTeX RDF
23	De-Sheng Chen, Chang-Tzu Lin, Yiwen Wang 0003, Ching-Hwa Cheng	Fixed-outline floorplanning using robust evolutionary search.	Eng. Appl. Artif. Intell.	2007	DBLP DOI BibTeX RDF
23	Chang-Tzu Lin, De-Sheng Chen, Yiwen Wang 0003	Modern Floorplanning with Boundary and Fixed-outline Constraints via Genetic Clustering Algorithm.	J. Circuits Syst. Comput.	2006	DBLP DOI BibTeX RDF
23	Rong Liu, Sheqin Dong, Xianlong Hong	An efficient algorithm to fixed-outline floorplanning based on instance augmentation.	CAD/Graphics	2005	DBLP DOI BibTeX RDF
23	Saurabh N. Adya, Igor L. Markov	Fixed-outline Floorplanning through Better Local Search.	ICCD	2001	DBLP DOI BibTeX RDF
15	Song Chen 0001, Zheng Xu, Takeshi Yoshimura	A generalized V-shaped multilevel method for large scale floorplanning.	ISQED	2009	DBLP DOI BibTeX RDF
15	Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin	A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
15	Jarrod A. Roy, Saurabh N. Adya, David A. Papa, Igor L. Markov	Min-cut floorplacement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
15	Saurabh N. Adya, S. Chaturvedi, Jarrod A. Roy, David A. Papa, Igor L. Markov	Unification of partitioning, placement and floorplanning.	ICCAD	2004	DBLP DOI BibTeX RDF
12	Saurabh N. Adya, Igor L. Markov	Combinatorial techniques for mixed-size placement.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	VLSI, placement, floorplanning
12	Saurabh N. Adya, Igor L. Markov	Consistent placement of macro-blocks using floorplanning and standard-cell placement.	ISPD	2002	DBLP DOI BibTeX RDF
10	Jason Cong, Michail Romesis, Joseph R. Shinnerl	Fast floorplanning by look-ahead enabled recursive bipartitioning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
10	Jason Cong, Michail Romesis, Joseph R. Shinnerl	Fast floorplanning by look-ahead enabled recursive bipartitioning.	ASP-DAC	2005	DBLP DOI BibTeX RDF
7	Michael D. Moffitt, Jarrod A. Roy, Igor L. Markov, Martha E. Pollack	Constraint-driven floorplan repair.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	constraints, Floorplanning, legalization
7	Yan Feng, Dinesh P. Mehta	Heterogeneous Floorplanning for FPGAs.	VLSI Design	2006	DBLP DOI BibTeX RDF
7	Emine Inelmen, Erol Inelmen, Ahmad Ibrahim 0003	A New Approach to Teaching Fuzzy Logic System Design.	IFSA	2003	DBLP DOI BibTeX RDF