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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 17 occurrences of 10 keywords
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Results
Found 558 publication records. Showing 558 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
44 | A. E. Hussein, Mohamed I. Elmasry |
Fractional-N frequency synthesizer for wireless communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 513-516, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
44 | Michael H. Perrott |
Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 498-503, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
fractional-N, sigma, PLL, frequency, delta, DLL, synthesizer |
37 | Volodymyr Kratyuk, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram |
A low spur fractional-N frequency synthesizer architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2807-2810, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
37 | Ching-Yuan Yang, Jen-Wen Chen, Meng-Ting Tsai |
A high-frequency phase-compensation fractional-N frequency synthesizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 5091-5094, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
36 | Charlotte Y. Lau, Michael H. Perrott |
Fractional-N frequency synthesizer design at the transfer function level using a direct closed loop realization algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 526-531, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
fractional-N, sigma, design, PLL, frequency, delta, synthesizer |
29 | Ching-Lung Ti, Yao-Hong Liu, Tsung-Hsien Lin |
A 2.4-GHz fractional-N PLL with a PFD/CP linearization and an improved CP circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 1728-1731, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
29 | Himanshu Arora, Nikolaus Klemmer, Patrick D. Wolf |
A 900 MHz ISM band mash-12 fractional-n frequency synthesizer for 5-Mbps data transmission. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 381-386, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
RMS phase error, delta-sigma, fractional-N, gain mismatch, phase frequency detector, spurs, thermal noise, VCO, phase noise, frequency synthesizer, charge pump |
22 | Shuilong Huang, Huainan Ma, Zhihua Wang |
Modeling and simulation to the design of SigmaDelta fractional-N frequency synthesizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 291-296, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Baoyong Chi, Xueyi Yu, Woogeun Rhee, Zhihua Wang 0001 |
A Fractional-N PLL for Digital Clock Generation With an FIR-Embedded Frequency Divider. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3051-3054, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Shuilong Huang, Zhihua Wang, Huainan Ma |
A Fast 1.9 GHz Fractional-N/Integer Frequency Synthesizer with a Self-tuning Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 203-206, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Shuenn-Yuh Lee, Chung-Han Cheng, Ming-Feng Huang, Shyh-Chyang Lee |
A 1-V 2.4-GHz low-power fractional-N frequency synthesizer with sigma-delta modulator controller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2811-2814, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Paul V. Brennan, Dai Jiang, Jianxin Zhang |
Analyses of intermodulation effects in fractional-N frequency synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2243-2246, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Farhad Zarkeshvari, Peter Noel, Tad A. Kwasniewski |
PLL-Based Fractional-N Frequency Synthesizers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 20-24 July 2004, Banff, Alberta, Canada, pp. 85-91, 2005, IEEE Computer Society, 0-7695-2403-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Joohwan Park, Franco Maloberti |
Phase noise improvement in fractional-N synthesizer with 90° phase shift lock. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 733-736, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Ping Wu, Kai He |
A CMOS triple-band fractional-N frequency synthesizer for GSM/GPRS/EDGE applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 706-709, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
22 | Woogeun Rhee, Akbar Ali |
An on-chip phase compensation technique in fractional-N frequency synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 363-366, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
22 | Augusto Manuel Marques, Michiel S. J. Steyaert, Willy M. C. Sansen |
Theory of PLL fractional-N frequency synthesizers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Wirel. Networks ![In: Wirel. Networks 4(1), pp. 79-85, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
15 | Jae Y. Kim, Chih-Wei Yao, Alan N. Willson Jr. |
A programmable 25 MHz to 6 GHz rational-K/L frequency synthesizer with digital Kvco compensation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 2629-2632, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Meng-Ting Tsai, Ching-Yuan Yang |
A frequency synthesizer realized by a transformer-based voltage-controlled oscillator for IEEE 802.11a/b/g channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Taoufik Bourdi, Assaad Borjak, Izzet Kale |
A modeling platform for efficient characterization of phase-locked loop Delta Sigma frequency synthesizers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Young-Mi Lee, Ju-Sang Lee, Sang Jin Lee, Ri-A Ju |
Design of a frequency synthesizer for WCDMA in 0.18µm CMOS process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 757-760, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
15 | Keliu Shu, Edgar Sánchez-Sinencio, José Silva-Martínez |
A 2.1-GHz monolithic frequency synthesizer with robust phase switching prescaler and loop capacitance scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 791-794, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
14 | Himanshu Arora, Nikolaus Klemmer, Thomas Jochum, Patrick D. Wolf |
Phase-Noise Driven System Design of Fractional-N Frequency Synthesizers and Validation With Measured Results. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pp. 133-138, 2007, IEEE Computer Society, 0-7695-2896-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Himanshu Arora, Nikolaus Klemmer, Thomas Jochum, Patrick D. Wolf |
Design Methodology and CAD Tools for Prototyping Delta-Sigma Fractional-N Frequency Synthesizers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 28-30 May 2007, Porto Alegre, RS, Brazil, pp. 150-156, 2007, IEEE Computer Society, 978-0-7695-2834-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Jian-Hong Fang, Norman M. Filiol, Tom A. D. Riley, Miles A. Copeland |
A Second Order Delta-Sigma Frequency Discriminator with Fractional-N Divider and Multi-Bit Quantizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1689-1692, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Shu-Chang Kuo, Tzu-Chien Hung, Wei-Bin Yang |
The new improved pseudo fractional-N clock generator with 50% duty cycle. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
14 | Lei Yang 0019, Cherry Wakayama, C.-J. Richard Shi |
Noise aware behavioral modeling of the E-Delta fractional-N frequency synthesizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 138-142, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
jitter noise, PLL, phase noise, frequency synthesizer |
14 | Rasoul Dehghani |
A 2.5GHz CMOS Fully-Integrated \Delta\Sigma-Controlled Fractional-N Frequency Synthesizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 163-167, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
14 | N. Christoffers, Rainer Kokozinski, Stephan Kolnsberg, Bedrich J. Hosticka |
High loop-filter-order ΣΔ-fractional-n frequency synthesizers for use in frequency-hopping-spread-spectrum communication-systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 216-219, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
14 | Zhenhua Wang |
A virtually jitter-free fractional-N divider for a Bluetooth radio. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 312-315, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
14 | Marco Cassia, Peter Shah, Erik Bruun |
A spur-free fractional-N ΣΔ PLL for GSM applications: linear model and simulations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 1065-1068, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
14 | Michael H. Perrott |
Behavioral Simulation of Fractional-N Frequency Synthesizers and Other PLL Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 19(4), pp. 74-83, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
14 | Lizhong Sun, Thierry Lepley, Franck Nozahic, Amaud Bellissant, Tad A. Kwasniewski, Bany Heim |
Reduced complexity, high performance digital delta-sigma modulator for fractional-N frequency synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 152-155, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
13 | Yuhwan Shin, Junseok Lee, Juyeop Kim, Yongwoo Jo, Jaehyouk Choi |
10.5 A 76 fsrms- Jitter and -65dBc- Fractional-Spur Fractional-N Sampling PLL Using a Nonlinearity-Replication Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2024, San Francisco, CA, USA, February 18-22, 2024, pp. 196-198, 2024, IEEE, 979-8-3503-0620-0. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
13 | Michael Peter Kennedy, Valerio Mazzaro, Stefano Tulisi, Micheál Scully, Niall McDermott, James Breslin |
10.4 A 45.5fs-Integrated-Random-Jitter and -75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional, Horn, and Wandering Spurs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2024, San Francisco, CA, USA, February 18-22, 2024, pp. 194-196, 2024, IEEE, 979-8-3503-0620-0. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
13 | Dingxin Xu, Yuncheng Zhang, Hongye Huang, Zheng Sun, Bangan Liu, Ashbir Aviat Fadila, Junjun Qiu, Zezheng Liu, Wenqian Wang, Yuang Xiong, Waleed Madany, Atsushi Shirane, Kenichi Okada |
A 6.5-to-8GHz Cascaded Dual-Fractional-N Digital PLL Achieving -63.7dBc Fractional Spurs with 50MHz Reference. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: IEEE Custom Integrated Circuits Conference, CICC 2023, San Antonio, TX, USA, April 23-26, 2023, pp. 1-2, 2023, IEEE, 979-8-3503-9948-6. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
13 | Xinlin Geng, Zonglin Ye, Yao Xiao, Oian Xie, Zheng Wang 0050 |
A 26GHz Fractional-N Charge-Pump PLL Based on A Dual-DTC-Assisted Time-Amplifying-Phase-Frequency Detector Achieving 37.1fs and 45.6fs rms Jitter for Integer-N and Fractional-N Channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: IEEE Custom Integrated Circuits Conference, CICC 2023, San Antonio, TX, USA, April 23-26, 2023, pp. 1-2, 2023, IEEE, 979-8-3503-9948-6. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
13 | Qiaochu Zhang, Hsiang-Chun Cheng, Shiyu Su, Mike Shuo-Wei Chen |
A Fractional-N Digital MDLL with Injection-Error Scrambling and Background Third-Order DTC Delay Equalizer Achieving -67dBc Fractional Spur. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid- State Circuits Conference, ISSCC 2023, San Francisco, CA, USA, February 19-23, 2023, pp. 226-227, 2023, IEEE, 978-1-6654-9016-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
13 | Chanwoong Hwang, Hangi Park, Yongsun Lee, Taeho Seong, Jaehyouk Choi |
A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC's Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping ΔΣM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 57(9), pp. 2841-2855, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Zhong Gao, Jingchu He, Martin Fritz, Jiang Gong, Yiyu Shen, Zhirui Zong, Peng Chen 0022, Gerd Spalink, Ben Eitel, Ken Yamamoto, Robert Bogdan Staszewski, Morteza S. Alavi, Masoud Babaie |
A 2.6-to-4.1GHz Fractional-N Digital PLL Based on a Time-Mode Arithmetic Unit Achieving -249.4dB FoM and -59dBc Fractional Spurs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2022, San Francisco, CA, USA, February 20-26, 2022, pp. 380-382, 2022, IEEE, 978-1-6654-2800-2. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Dongyi Liao, Fa Foster Dai |
A Fractional-N Reference Sampling PLL With Linear Sampler and CDAC Based Fractional Spur Cancellation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 56(3), pp. 694-704, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Hangi Park, Chanwoong Hwang, Taeho Seong, Yongsun Lee, Jaehyouk Choi |
A 365fsrms-Jitter and -63dBc-Fractional Spur 5.3GHz-Ring-DCO-Based Fractional-N DPLL Using a DTC Second/Third- Order Nonlinearity Cancelation and a Probability-Density-Shaping Δ ΣM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2021, San Francisco, CA, USA, February 13-22, 2021, pp. 442-444, 2021, IEEE, 978-1-7281-9549-0. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Qiaochu Zhang, Shiyu Su, Cheng-Ru Ho, Mike Shuo-Wei Chen |
29.4 A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving -60dBc Fractional Spur. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2021, San Francisco, CA, USA, February 13-22, 2021, pp. 410-412, 2021, IEEE, 978-1-7281-9549-0. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Juyeop Kim, Yongwoo Jo, Younghyun Lim, Taeho Seong, Hangi Park, Seyeon Yoo, Yongsun Lee, Seojin Choi, Jaehyouk Choi |
32.4 A 104fsrms-Jitter and -61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancelation Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2021, San Francisco, CA, USA, February 13-22, 2021, pp. 448-450, 2021, IEEE, 978-1-7281-9549-0. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Dongyi Liao, Fa Foster Dai |
A 7.7~10.3GHz 5.2mW -247.3dB-FOM Fractional-N Reference Sampling PLL with 2nd Order CDAC Based Fractional Spur Cancellation In 45nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: 2020 IEEE Custom Integrated Circuits Conference, CICC 2020, Boston, MA, USA, March 22-25, 2020, pp. 1-4, 2020, IEEE, 978-1-7281-6031-3. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Hossein Rahmanian Kooshkaki, Patrick P. Mercier |
A 0.55mW Fractional-N PLL with a DC-DC Powered Class-D VCO Achieving Better than -66dBc Fractional and Reference Spurs for NB-IoT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: 2020 IEEE Custom Integrated Circuits Conference, CICC 2020, Boston, MA, USA, March 22-25, 2020, pp. 1-4, 2020, IEEE, 978-1-7281-6031-3. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Taeho Seong, Yongsun Lee, Chanwoong Hwang, Jeonghyun Lee, Hangi Park, Kyuho Jason Lee, Jaehyouk Choi |
17.3 A -58dBc-Worst-Fractional-Spur and -234dB-FoMjitter, 5.5GHz Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator, Generating a Nonlinearity-Robust DTC-Control Word. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2020 IEEE International Solid- State Circuits Conference, ISSCC 2020, San Francisco, CA, USA, February 16-20, 2020, pp. 270-272, 2020, IEEE, 978-1-7281-3205-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Masaru Osada, Zule Xu, Tetsuya Iizuka |
A 3.2-to-3.8GHz Calibration-Free Harmonic-Mixer-Based Dual-Feedback Fractional-N PLL Achieving -66dBc Worst-Case In-Band Fractional Spur. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Circuits ![In: IEEE Symposium on VLSI Circuits, VLSI Circuits 2020, Honolulu, HI, USA, June 16-19, 2020, pp. 1-2, 2020, IEEE, 978-1-7281-9942-9. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Michael Peter Kennedy, Yann Donnelly, James Breslin, Stefano Tulisi, Sanganagouda Patil, Ciaran Curtin, Stephen Brookes, Brian Shelly, Patrick Griffin, Michael Keaveney |
4.48GHz 0.18μm SiGe BiCMOS Exact-Frequency Fractional-N Frequency Synthesizer with Spurious-Tone Suppression Yielding a -80dBc In-Band Fractional Spur. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid- State Circuits Conference, ISSCC 2019, San Francisco, CA, USA, February 17-21, 2019, pp. 272-274, 2019, IEEE, 978-1-5386-8531-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Cheng-Ru Ho, Mike Shuo-Wei Chen |
A fractional-N digital PLL with background-dither-noise-cancellation loop achieving <-62.5dBc worst-case near-carrier fractional spurs in 65nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018, pp. 394-396, 2018, IEEE, 978-1-5090-4940-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Young-Ho Choi, Byungsub Kim, Jae-Yoon Sim, Hong-June Park |
A Phase-Interpolator-Based Fractional Counter for All-Digital Fractional-N Phase-Locked Loop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 64-II(3), pp. 249-253, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
13 | Chih-Wei Yao, Wing Fai Loke, Ronghua Ni, Yongping Han, Haoyang Li, Kunal Godbole, Yongrong Zuo, Sangsoo Ko, Nam-Seog Kim, Sangwook Han, Ikkyun Jo, Joonhee Lee, Juyoung Han, Daehyeon Kwon, Chulho Kim, Shinwoong Kim, Sang Won Son, Thomas Byunghak Cho |
24.8 A 14nm fractional-N digital PLL with 0.14psrms jitter and -78dBc fractional spur for cellular RFICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017, San Francisco, CA, USA, February 5-9, 2017, pp. 422-423, 2017, IEEE, 978-1-5090-3758-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
13 | Chun-Yu Lin 0002, Tsung-Hsien Lin |
A 4-GHz ΔΣ fractional-N frequency synthesizer with 2-dimensional quantization noise pushing and fractional spur elimination techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
A-SSCC ![In: IEEE Asian Solid-State Circuits Conference, A-SSCC 2016, Toyama, Japan, November 7-9, 2016, pp. 93-96, 2016, IEEE, 978-1-5090-3699-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
13 | Najmeh Sadatnejad, Hossein Miar Naimi |
A new fractional spur modeling in fractional-N frequency synthesizers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: IEEE 28th Canadian Conference on Electrical and Computer Engineering, CCECE 2015, Halifax, NS, Canada, May 3-6, 2015, pp. 536-540, 2015, IEEE, 978-1-4799-5827-6. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
13 | Jenlung Liu, Tae-Kwang Jang, Yonghee Lee, Jungeun Shin, Seunghoon Lee, Taeik Kim, Jaejin Park, Hojin Park |
15.2 A 0.012mm2 3.1mW bang-bang digital fractional-N PLL with a power-supply-noise cancellation technique and a walking-one-phase-selection fractional frequency divider. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2014 IEEE International Conference on Solid-State Circuits Conference, ISSCC 2014, Digest of Technical Papers, San Francisco, CA, USA, February 9-13, 2014, pp. 268-269, 2014, IEEE, 978-1-4799-0918-6. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
13 | Tsung-Kai Kao, Che-Fu Liang, Hsien-Hsiang Chiu, Michael Ashburn |
A wideband fractional-N ring PLL with fractional-spur suppression using spectrally shaped segmentation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2013 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2013, San Francisco, CA, USA, February 17-21, 2013, pp. 416-417, 2013, IEEE, 978-1-4673-4515-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
13 | Chun-Pang Wu, Hen-Wai Tsao, Jingshown Wu |
A novel sigma-delta fractional-N synthesizer architecture with fractional spur and quantization noise cancellation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France, pp. 1117-1120, 2010, IEEE, 978-1-4244-5308-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
13 | Chen-Wei Huang, Ping Gui, Liming Xiu |
A Wide-tuning-range and Reduced-fractional-spurs Synthesizer Combining Sigma-Delta Fractional-N and Integer Flying-Adder Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2009), 24-17 May 2009, Taipei, Taiwan, pp. 1377-1380, 2009, IEEE, 978-1-4244-3827-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
13 | Xiaopin Zhang |
A Fractional- N Frequency Synthesizer With No Fractional Spurs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 53-II(9), pp. 986-990, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
8 | Markus Pichler, Andreas Stelzer, Claus Seisenberger |
Modeling and simulation of PLL-based frequency-synthesizers for FMCW radar. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 1540-1543, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
8 | Josef Zipper, Gernot Hueber, Andreas Holm |
A single-chip UMTS receiver with integrated digital frontend in 0.13 µm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 972-975, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
8 | Ping-Ying Wang, Hsiu-Ming Chang 0001 |
A charge pump-based direct frequency modulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 1962-1965, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
8 | Ashok Swaminathan, Andrea Panigada, Elias Masry, Ian Galton |
A Digital Requantizer With Shaped Requantization Noise That Remains Well Behaved After Nonlinear Distortion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Signal Process. ![In: IEEE Trans. Signal Process. 55(11), pp. 5382-5394, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
8 | Sangho Shin, Kwyro Lee, Sung-Mo Kang |
2.4GHz ZigBee radio architecture with fast frequency offset cancellation loop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
8 | Igor Miletic, Ralph Mason |
Quantization noise reduction using multiphase PLLs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
8 | Igor Miletic, Ralph Mason |
Bandwidth Expansion in Sigma-Delta PLLs Using Multiphase VCOs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the Canadian Conference on Electrical and Computer Engineering, CCECE 2006, May 7-10, 2006, Ottawa Congress Centre, Ottawa, Canada, pp. 971-974, 2006, IEEE, 1-4244-0038-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
8 | Yao-Huang Kao, Yi-Bin Hsieh |
A Wide Input-Range Sigma Delta Modulator for Applications to Spread-Spectrum Clock Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 530-533, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
8 | Eva Tatschl-Unterberger, Sasan Cyrusian, Michael Ruegg |
A 2.5GHz phase-switching PLL using a supply controlled 2-delay-stage 10GHz ring oscillator for improved jitter/mismatch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 5453-5456, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
8 | Wei-Ta Chen, Jen-Chien Hsu, Hong-Wen Lune, Chauchin Su |
A spread spectrum clock generator for SATA-II. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2643-2646, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
8 | Jianxin Zhang, Paul V. Brennan, Dai Jiang, E. Vinogradova, P. D. Smith |
Stability analysis of a sigma delta modulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 961-964, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
8 | Amr M. Fahim, Mohamed I. Elmasry |
A low-power CMOS frequency synthesizer design methodology for wireless applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 115-119, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
6 | Qiaochu Zhang, Hsiang-Chun Cheng, Shiyu Su, Mike Shuo-Wei Chen |
Fractional-N Digital MDLL With Injection-Error Scrambling and Calibration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 59(1), pp. 40-51, January 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
6 | Zonglin Ye, Xinlin Geng, Yao Xiao, Qian Xie, Zheng Wang 0050 |
A Sub-50-fsrms Jitter Fractional-N CPPLL Based on a Dual-DTC-Assisted Time-Amplifying Phase-Frequency Detector With Cascadable DTC Nonlinearity Compensation Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 59(3), pp. 677-689, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
6 | Juyeop Kim, Yongwoo Jo, Hangi Park, Taeho Seong, Younghyun Lim, Jaehyouk Choi |
A 12.8-15.0-GHz Low-Jitter Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 59(2), pp. 424-434, February 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
6 | Liqun Feng, Woogeun Rhee, Zhihua Wang 0001 |
A DTC-Free Fractional-N BBPLL With FIR-Embedded Injection-Locked-Oscillator-Based Phase-Domain Lowpass Filter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 59(3), pp. 728-739, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
6 | Seheon Jang, Munjae Chae, Hangi Park, Chanwoong Hwang, Jaehyouk Choi |
10.2 A 5.5μs-Calibration-Time, Low-Jitter, and Compact-Area Fractional-N Digital PLL Using the Recursive-Least-Squares (RLS) Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2024, San Francisco, CA, USA, February 18-22, 2024, pp. 190-192, 2024, IEEE, 979-8-3503-0620-0. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
6 | Michele Rossoni, Simone Mattia Dartizio, Francesco Tesolin, Giacomo Castoro, Riccardo Dell'Orto, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino |
10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and -252.4dB FoM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2024, San Francisco, CA, USA, February 18-22, 2024, pp. 188-190, 2024, IEEE, 979-8-3503-0620-0. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
6 | Liqun Feng, Xuansheng Ji, Longhao Kuang, Qianxian Liao, Su Han, Jiahao Zhao, Woogeun Rhee, Zhihua Wang 0001 |
14.7 A 0.45V 0.72mW 2.4GHz Bias-Current-Free Fractional-N Hybrid PLL Using a Voltage-Mode Phase Interpolator in 28nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2024, San Francisco, CA, USA, February 18-22, 2024, pp. 266-268, 2024, IEEE, 979-8-3503-0620-0. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
6 | David Murphy, Dihang Yang, Hooman Darabi, Arya Behzad |
A Calibration-Free Fractional-N Analog PLL With Negligible DSM Quantization Noise. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 58(9), pp. 2513-2525, September 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
6 | Simone Mattia Dartizio, Francesco Tesolin, Giacomo Castoro, Francesco Buccoleri, Michele Rossoni, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino |
A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 58(12), pp. 3320-3337, December 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
6 | Zhong Gao, Jingchu He, Martin Fritz, Jiang Gong, Yiyu Shen, Zhirui Zong, Peng Chen 0022, Gerd Spalink, Ben Eitel, Morteza S. Alavi, Robert Bogdan Staszewski, Masoud Babaie |
A Low-Spur Fractional-N PLL Based on a Time-Mode Arithmetic Unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 58(6), pp. 1552-1571, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
6 | Francesco Buccoleri, Simone Mattia Dartizio, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino |
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 58(3), pp. 634-646, March 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
6 | Yu Zhao, Onur Memioglu, Long Kong, Behzad Razavi |
A 56-GHz Fractional-N PLL With 110-fs Jitter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 58(1), pp. 57-67, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
6 | Dawei Mai, Michael Peter Kennedy |
Optimized MASH-SR Divider Controller for Fractional-N Frequency Synthesizers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 70(3), pp. 1057-1070, March 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
6 | Junlin Zhong, Xiaofeng Yang 0004, Rui Paulo Martins, Yan Zhu 0001, Chi-Hang Chan |
A 0.016mm2 Active Area 4GHz Fully Ring-Oscillator-Based Cascaded Fractional-N PLL With Burst-Mode Sampling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 70(10), pp. 3792-3796, October 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
6 | Kyungmin Lee, Jaehong Jung, Seungjin Kim, Seunghyun Oh, Jongwoo Lee, Sung Min Park 0001 |
A 208-MHz, 0.75-mW Self-Calibrated Reference Frequency Quadrupler for a 2-GHz Fractional-N Ring-PLL in 4-nm FinFET CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 70(8), pp. 2719-2723, August 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
6 | Abdul Muqueem, Shanky Saxena, Govind Singh Patel |
An Ultra-Low-Power C-Band FMCW Transmitter Using a Fast Settling Fractional-N DPLL and Ring-Based Pulse Injection Locking Oscillator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 32(3), pp. 2350045:1-2350045:24, February 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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6 | Zirui Jin, Xiaoyu Shan, Ang Hu, Dongsheng Liu, Xuan Cheng, Jinsong Cui, Chengcheng Zhang, Jianming Lei |
A DTC-based Fractional-N DPLL using probability-density-shaping spur immunity and Q-noise reduction techniques for IoT applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 135, pp. 105753, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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6 | Hui Li, Changchun Zhang, Yi Zhang, Jing Wang |
A fractional-N frequency synthesizer with phase synchronization and programmable phase control capability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 142, pp. 105996, December 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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6 | Zirui Jin, Ang Hu, Xiaoyu Shan, Chengcheng Zhang, Jinsong Cui, Jianming Lei, Dongsheng Liu |
A Fractional-N CP-PLL with fast two-point modulation calibration using duty-cycle and polarity tracking technique in 110-nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 132, pp. 105676, February 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
6 | Yantian Xu, Zhiyu Wang, Jiarui Liu 0001, Hua Chen, Faxin Yu |
Multi-chip phase synchronization circuit of fractional-N PLL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 20(9), pp. 20230035, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
6 | Xu Wang, Michael Peter Kennedy |
Performance Limits of Fractional-N Digital PLLs with Mid-Rise TDCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRIME ![In: 18th Conference on Ph.D Research in Microelectronics and Electronics, PRIME 2023, Valencia, Spain, June 18-21, 2023, pp. 317-320, 2023, IEEE, 979-8-3503-0320-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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6 | Wenqiang Huang, Yanshu Guo, Yaoyu Li, Zhihua Wang 0001, Yuanjin Zheng, Tiefu Li, Hanjun Jiang, Wen Jia |
A 1-1.7 GHz Cryogenic Fractional-N CP-PLL for Quantum Computing Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: 66th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2023, Tempe, AZ, USA, August 6-9, 2023, pp. 172-176, 2023, IEEE, 979-8-3503-0210-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
6 | Junjie Li, Youming Zhang, Yunqi Cao, Xusheng Tang, Fengyi Huang |
A Unity Feedback Length-Extend Delta-Sigma Modulator for Fractional-N Frequency Synthesizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 31st IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023, pp. 1-4, 2023, IEEE, 979-8-3503-2599-7. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
6 | Xu Wang, Michael Peter Kennedy |
Comparison of DTC-Related Spurs in Fractional-N Digital PLLs with MASH-and-ENOP-based Divider Controllers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 30th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2023, Istanbul, Turkey, December 4-7, 2023, pp. 1-5, 2023, IEEE, 979-8-3503-2649-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
6 | Xu Lu, Michael Peter Kennedy |
Further Insights into Spur Immunity in MASH-Based Fractional-N CP-PLLs with Polynomial Nonlinearities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 30th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2023, Istanbul, Turkey, December 4-7, 2023, pp. 1-5, 2023, IEEE, 979-8-3503-2649-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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6 | Xinyu Shen, Zhao Zhang 0004, Guike Li, Yong Chen, Nan Qi, Jian Liu 0021, Nanjian Wu, Liyuan Liu |
A 4-12.1-GHz Fractional-N Ring Sampling PLL Based on Adaptively-Biased PD-Merged DTC Achieving -37.6± 0.9-dBc Integrated Phase Noise, 261.9-fs RMS Jitter, and -240.6-dB FoM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: 49th IEEE European Solid State Circuits Conference, ESSCIRC 2023, Lisbon, Portugal, September 11-14, 2023, pp. 257-260, 2023, IEEE, 979-8-3503-0420-6. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
6 | Xu Wang, Michael Peter Kennedy |
Linearized Analysis of Mid-Rise TDCs for Integer-N and Fractional-N Digital PLLs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NEWCAS ![In: 21st IEEE Interregional NEWCAS Conference, NEWCAS 2023, Edinburgh, United Kingdom, June 26-28, 2023, pp. 1-5, 2023, IEEE, 979-8-3503-0024-6. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
6 | Liqun Feng, Woogeun Rhee, Zhihua Wang 0001 |
A 2.6GHz ΔΣ Fractional-N Bang-Bang PLL with FIR-Embedded Injection-Locking Phase-Domain Low-Pass Filter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: IEEE Custom Integrated Circuits Conference, CICC 2023, San Antonio, TX, USA, April 23-26, 2023, pp. 1-2, 2023, IEEE, 979-8-3503-9948-6. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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6 | Wen Chen, Yiyang Shu, Xun Luo |
A 21.8-41.6GHz Fractional-N Sub-Sampling PLL with Dividerless Unequal-REF-Delay Frequency-Locked Loop Achieving -246.9dB FoMj and -270.3dB FoMj,N. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: IEEE Custom Integrated Circuits Conference, CICC 2023, San Antonio, TX, USA, April 23-26, 2023, pp. 1-2, 2023, IEEE, 979-8-3503-9948-6. The full citation details ...](Pics/full.jpeg) |
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