Search results for "fractional-N"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
44	A. E. Hussein, Mohamed I. Elmasry	Fractional-N frequency synthesizer for wireless communications.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
44	Michael H. Perrott	Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits.	DAC	2002	DBLP DOI BibTeX RDF	fractional-N, sigma, PLL, frequency, delta, DLL, synthesizer
37	Volodymyr Kratyuk, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram	A low spur fractional-N frequency synthesizer architecture.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
37	Ching-Yuan Yang, Jen-Wen Chen, Meng-Ting Tsai	A high-frequency phase-compensation fractional-N frequency synthesizer.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
36	Charlotte Y. Lau, Michael H. Perrott	Fractional-N frequency synthesizer design at the transfer function level using a direct closed loop realization algorithm.	DAC	2003	DBLP DOI BibTeX RDF	fractional-N, sigma, design, PLL, frequency, delta, synthesizer
29	Ching-Lung Ti, Yao-Hong Liu, Tsung-Hsien Lin	A 2.4-GHz fractional-N PLL with a PFD/CP linearization and an improved CP circuit.	ISCAS	2008	DBLP DOI BibTeX RDF
29	Himanshu Arora, Nikolaus Klemmer, Patrick D. Wolf	A 900 MHz ISM band mash-12 fractional-n frequency synthesizer for 5-Mbps data transmission.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	RMS phase error, delta-sigma, fractional-N, gain mismatch, phase frequency detector, spurs, thermal noise, VCO, phase noise, frequency synthesizer, charge pump
22	Shuilong Huang, Huainan Ma, Zhihua Wang	Modeling and simulation to the design of SigmaDelta fractional-N frequency synthesizer.	DATE	2007	DBLP DOI BibTeX RDF
22	Baoyong Chi, Xueyi Yu, Woogeun Rhee, Zhihua Wang 0001	A Fractional-N PLL for Digital Clock Generation With an FIR-Embedded Frequency Divider.	ISCAS	2007	DBLP DOI BibTeX RDF
22	Shuilong Huang, Zhihua Wang, Huainan Ma	A Fast 1.9 GHz Fractional-N/Integer Frequency Synthesizer with a Self-tuning Algorithm.	APCCAS	2006	DBLP DOI BibTeX RDF
22	Shuenn-Yuh Lee, Chung-Han Cheng, Ming-Feng Huang, Shyh-Chyang Lee	A 1-V 2.4-GHz low-power fractional-N frequency synthesizer with sigma-delta modulator controller.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
22	Paul V. Brennan, Dai Jiang, Jianxin Zhang	Analyses of intermodulation effects in fractional-N frequency synthesis.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
22	Farhad Zarkeshvari, Peter Noel, Tad A. Kwasniewski	PLL-Based Fractional-N Frequency Synthesizers.	IWSOC	2005	DBLP DOI BibTeX RDF
22	Joohwan Park, Franco Maloberti	Phase noise improvement in fractional-N synthesizer with 90° phase shift lock.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
22	Ping Wu, Kai He	A CMOS triple-band fractional-N frequency synthesizer for GSM/GPRS/EDGE applications.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
22	Woogeun Rhee, Akbar Ali	An on-chip phase compensation technique in fractional-N frequency synthesis.	ISCAS (3)	1999	DBLP DOI BibTeX RDF
22	Augusto Manuel Marques, Michiel S. J. Steyaert, Willy M. C. Sansen	Theory of PLL fractional-N frequency synthesizers.	Wirel. Networks	1998	DBLP DOI BibTeX RDF
15	Jae Y. Kim, Chih-Wei Yao, Alan N. Willson Jr.	A programmable 25 MHz to 6 GHz rational-K/L frequency synthesizer with digital Kvco compensation.	ISCAS	2008	DBLP DOI BibTeX RDF
15	Meng-Ting Tsai, Ching-Yuan Yang	A frequency synthesizer realized by a transformer-based voltage-controlled oscillator for IEEE 802.11a/b/g channels.	ISCAS	2006	DBLP DOI BibTeX RDF
15	Taoufik Bourdi, Assaad Borjak, Izzet Kale	A modeling platform for efficient characterization of phase-locked loop Delta Sigma frequency synthesizers.	ISCAS	2006	DBLP DOI BibTeX RDF
15	Young-Mi Lee, Ju-Sang Lee, Sang Jin Lee, Ri-A Ju	Design of a frequency synthesizer for WCDMA in 0.18µm CMOS process.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
15	Keliu Shu, Edgar Sánchez-Sinencio, José Silva-Martínez	A 2.1-GHz monolithic frequency synthesizer with robust phase switching prescaler and loop capacitance scaling.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
14	Himanshu Arora, Nikolaus Klemmer, Thomas Jochum, Patrick D. Wolf	Phase-Noise Driven System Design of Fractional-N Frequency Synthesizers and Validation With Measured Results.	ISVLSI	2007	DBLP DOI BibTeX RDF
14	Himanshu Arora, Nikolaus Klemmer, Thomas Jochum, Patrick D. Wolf	Design Methodology and CAD Tools for Prototyping Delta-Sigma Fractional-N Frequency Synthesizers.	IEEE International Workshop on Rapid System Prototyping	2007	DBLP DOI BibTeX RDF
14	Jian-Hong Fang, Norman M. Filiol, Tom A. D. Riley, Miles A. Copeland	A Second Order Delta-Sigma Frequency Discriminator with Fractional-N Divider and Multi-Bit Quantizer.	ISCAS	2007	DBLP DOI BibTeX RDF
14	Shu-Chang Kuo, Tzu-Chien Hung, Wei-Bin Yang	The new improved pseudo fractional-N clock generator with 50% duty cycle.	ISCAS	2006	DBLP DOI BibTeX RDF
14	Lei Yang 0019, Cherry Wakayama, C.-J. Richard Shi	Noise aware behavioral modeling of the E-Delta fractional-N frequency synthesizer.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	jitter noise, PLL, phase noise, frequency synthesizer
14	Rasoul Dehghani	A 2.5GHz CMOS Fully-Integrated \Delta\Sigma-Controlled Fractional-N Frequency Synthesizer.	VLSI Design	2004	DBLP DOI BibTeX RDF
14	N. Christoffers, Rainer Kokozinski, Stephan Kolnsberg, Bedrich J. Hosticka	High loop-filter-order ΣΔ-fractional-n frequency synthesizers for use in frequency-hopping-spread-spectrum communication-systems.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
14	Zhenhua Wang	A virtually jitter-free fractional-N divider for a Bluetooth radio.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
14	Marco Cassia, Peter Shah, Erik Bruun	A spur-free fractional-N ΣΔ PLL for GSM applications: linear model and simulations.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
14	Michael H. Perrott	Behavioral Simulation of Fractional-N Frequency Synthesizers and Other PLL Circuits.	IEEE Des. Test Comput.	2002	DBLP DOI BibTeX RDF
14	Lizhong Sun, Thierry Lepley, Franck Nozahic, Amaud Bellissant, Tad A. Kwasniewski, Bany Heim	Reduced complexity, high performance digital delta-sigma modulator for fractional-N frequency synthesis.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
13	Yuhwan Shin, Junseok Lee, Juyeop Kim, Yongwoo Jo, Jaehyouk Choi	10.5 A 76 fsrms- Jitter and -65dBc- Fractional-Spur Fractional-N Sampling PLL Using a Nonlinearity-Replication Technique.	ISSCC	2024	DBLP DOI BibTeX RDF
13	Michael Peter Kennedy, Valerio Mazzaro, Stefano Tulisi, Micheál Scully, Niall McDermott, James Breslin	10.4 A 45.5fs-Integrated-Random-Jitter and -75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional, Horn, and Wandering Spurs.	ISSCC	2024	DBLP DOI BibTeX RDF
13	Dingxin Xu, Yuncheng Zhang, Hongye Huang, Zheng Sun, Bangan Liu, Ashbir Aviat Fadila, Junjun Qiu, Zezheng Liu, Wenqian Wang, Yuang Xiong, Waleed Madany, Atsushi Shirane, Kenichi Okada	A 6.5-to-8GHz Cascaded Dual-Fractional-N Digital PLL Achieving -63.7dBc Fractional Spurs with 50MHz Reference.	CICC	2023	DBLP DOI BibTeX RDF
13	Xinlin Geng, Zonglin Ye, Yao Xiao, Oian Xie, Zheng Wang 0050	A 26GHz Fractional-N Charge-Pump PLL Based on A Dual-DTC-Assisted Time-Amplifying-Phase-Frequency Detector Achieving 37.1fs and 45.6fs rms Jitter for Integer-N and Fractional-N Channels.	CICC	2023	DBLP DOI BibTeX RDF
13	Qiaochu Zhang, Hsiang-Chun Cheng, Shiyu Su, Mike Shuo-Wei Chen	A Fractional-N Digital MDLL with Injection-Error Scrambling and Background Third-Order DTC Delay Equalizer Achieving -67dBc Fractional Spur.	ISSCC	2023	DBLP DOI BibTeX RDF
13	Chanwoong Hwang, Hangi Park, Yongsun Lee, Taeho Seong, Jaehyouk Choi	A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC's Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping ΔΣM.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
13	Zhong Gao, Jingchu He, Martin Fritz, Jiang Gong, Yiyu Shen, Zhirui Zong, Peng Chen 0022, Gerd Spalink, Ben Eitel, Ken Yamamoto, Robert Bogdan Staszewski, Morteza S. Alavi, Masoud Babaie	A 2.6-to-4.1GHz Fractional-N Digital PLL Based on a Time-Mode Arithmetic Unit Achieving -249.4dB FoM and -59dBc Fractional Spurs.	ISSCC	2022	DBLP DOI BibTeX RDF
13	Dongyi Liao, Fa Foster Dai	A Fractional-N Reference Sampling PLL With Linear Sampler and CDAC Based Fractional Spur Cancellation.	IEEE J. Solid State Circuits	2021	DBLP DOI BibTeX RDF
13	Hangi Park, Chanwoong Hwang, Taeho Seong, Yongsun Lee, Jaehyouk Choi	A 365fsrms-Jitter and -63dBc-Fractional Spur 5.3GHz-Ring-DCO-Based Fractional-N DPLL Using a DTC Second/Third- Order Nonlinearity Cancelation and a Probability-Density-Shaping Δ ΣM.	ISSCC	2021	DBLP DOI BibTeX RDF
13	Qiaochu Zhang, Shiyu Su, Cheng-Ru Ho, Mike Shuo-Wei Chen	29.4 A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving -60dBc Fractional Spur.	ISSCC	2021	DBLP DOI BibTeX RDF
13	Juyeop Kim, Yongwoo Jo, Younghyun Lim, Taeho Seong, Hangi Park, Seyeon Yoo, Yongsun Lee, Seojin Choi, Jaehyouk Choi	32.4 A 104fsrms-Jitter and -61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancelation Technique.	ISSCC	2021	DBLP DOI BibTeX RDF
13	Dongyi Liao, Fa Foster Dai	A 7.7~10.3GHz 5.2mW -247.3dB-FOM Fractional-N Reference Sampling PLL with 2nd Order CDAC Based Fractional Spur Cancellation In 45nm CMOS.	CICC	2020	DBLP DOI BibTeX RDF
13	Hossein Rahmanian Kooshkaki, Patrick P. Mercier	A 0.55mW Fractional-N PLL with a DC-DC Powered Class-D VCO Achieving Better than -66dBc Fractional and Reference Spurs for NB-IoT.	CICC	2020	DBLP DOI BibTeX RDF
13	Taeho Seong, Yongsun Lee, Chanwoong Hwang, Jeonghyun Lee, Hangi Park, Kyuho Jason Lee, Jaehyouk Choi	17.3 A -58dBc-Worst-Fractional-Spur and -234dB-FoMjitter, 5.5GHz Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator, Generating a Nonlinearity-Robust DTC-Control Word.	ISSCC	2020	DBLP DOI BibTeX RDF
13	Masaru Osada, Zule Xu, Tetsuya Iizuka	A 3.2-to-3.8GHz Calibration-Free Harmonic-Mixer-Based Dual-Feedback Fractional-N PLL Achieving -66dBc Worst-Case In-Band Fractional Spur.	VLSI Circuits	2020	DBLP DOI BibTeX RDF
13	Michael Peter Kennedy, Yann Donnelly, James Breslin, Stefano Tulisi, Sanganagouda Patil, Ciaran Curtin, Stephen Brookes, Brian Shelly, Patrick Griffin, Michael Keaveney	4.48GHz 0.18μm SiGe BiCMOS Exact-Frequency Fractional-N Frequency Synthesizer with Spurious-Tone Suppression Yielding a -80dBc In-Band Fractional Spur.	ISSCC	2019	DBLP DOI BibTeX RDF
13	Cheng-Ru Ho, Mike Shuo-Wei Chen	A fractional-N digital PLL with background-dither-noise-cancellation loop achieving <-62.5dBc worst-case near-carrier fractional spurs in 65nm CMOS.	ISSCC	2018	DBLP DOI BibTeX RDF
13	Young-Ho Choi, Byungsub Kim, Jae-Yoon Sim, Hong-June Park	A Phase-Interpolator-Based Fractional Counter for All-Digital Fractional-N Phase-Locked Loop.	IEEE Trans. Circuits Syst. II Express Briefs	2017	DBLP DOI BibTeX RDF
13	Chih-Wei Yao, Wing Fai Loke, Ronghua Ni, Yongping Han, Haoyang Li, Kunal Godbole, Yongrong Zuo, Sangsoo Ko, Nam-Seog Kim, Sangwook Han, Ikkyun Jo, Joonhee Lee, Juyoung Han, Daehyeon Kwon, Chulho Kim, Shinwoong Kim, Sang Won Son, Thomas Byunghak Cho	24.8 A 14nm fractional-N digital PLL with 0.14psrms jitter and -78dBc fractional spur for cellular RFICs.	ISSCC	2017	DBLP DOI BibTeX RDF
13	Chun-Yu Lin 0002, Tsung-Hsien Lin	A 4-GHz ΔΣ fractional-N frequency synthesizer with 2-dimensional quantization noise pushing and fractional spur elimination techniques.	A-SSCC	2016	DBLP DOI BibTeX RDF
13	Najmeh Sadatnejad, Hossein Miar Naimi	A new fractional spur modeling in fractional-N frequency synthesizers.	CCECE	2015	DBLP DOI BibTeX RDF
13	Jenlung Liu, Tae-Kwang Jang, Yonghee Lee, Jungeun Shin, Seunghoon Lee, Taeik Kim, Jaejin Park, Hojin Park	15.2 A 0.012mm2 3.1mW bang-bang digital fractional-N PLL with a power-supply-noise cancellation technique and a walking-one-phase-selection fractional frequency divider.	ISSCC	2014	DBLP DOI BibTeX RDF
13	Tsung-Kai Kao, Che-Fu Liang, Hsien-Hsiang Chiu, Michael Ashburn	A wideband fractional-N ring PLL with fractional-spur suppression using spectrally shaped segmentation.	ISSCC	2013	DBLP DOI BibTeX RDF
13	Chun-Pang Wu, Hen-Wai Tsao, Jingshown Wu	A novel sigma-delta fractional-N synthesizer architecture with fractional spur and quantization noise cancellation.	ISCAS	2010	DBLP DOI BibTeX RDF
13	Chen-Wei Huang, Ping Gui, Liming Xiu	A Wide-tuning-range and Reduced-fractional-spurs Synthesizer Combining Sigma-Delta Fractional-N and Integer Flying-Adder Techniques.	ISCAS	2009	DBLP DOI BibTeX RDF
13	Xiaopin Zhang	A Fractional- N Frequency Synthesizer With No Fractional Spurs.	IEEE Trans. Circuits Syst. II Express Briefs	2006	DBLP DOI BibTeX RDF
8	Markus Pichler, Andreas Stelzer, Claus Seisenberger	Modeling and simulation of PLL-based frequency-synthesizers for FMCW radar.	ISCAS	2008	DBLP DOI BibTeX RDF
8	Josef Zipper, Gernot Hueber, Andreas Holm	A single-chip UMTS receiver with integrated digital frontend in 0.13 µm CMOS.	ISCAS	2008	DBLP DOI BibTeX RDF
8	Ping-Ying Wang, Hsiu-Ming Chang 0001	A charge pump-based direct frequency modulator.	ISCAS	2008	DBLP DOI BibTeX RDF
8	Ashok Swaminathan, Andrea Panigada, Elias Masry, Ian Galton	A Digital Requantizer With Shaped Requantization Noise That Remains Well Behaved After Nonlinear Distortion.	IEEE Trans. Signal Process.	2007	DBLP DOI BibTeX RDF
8	Sangho Shin, Kwyro Lee, Sung-Mo Kang	2.4GHz ZigBee radio architecture with fast frequency offset cancellation loop.	ISCAS	2006	DBLP DOI BibTeX RDF
8	Igor Miletic, Ralph Mason	Quantization noise reduction using multiphase PLLs.	ISCAS	2006	DBLP DOI BibTeX RDF
8	Igor Miletic, Ralph Mason	Bandwidth Expansion in Sigma-Delta PLLs Using Multiphase VCOs.	CCECE	2006	DBLP DOI BibTeX RDF
8	Yao-Huang Kao, Yi-Bin Hsieh	A Wide Input-Range Sigma Delta Modulator for Applications to Spread-Spectrum Clock Generator.	APCCAS	2006	DBLP DOI BibTeX RDF
8	Eva Tatschl-Unterberger, Sasan Cyrusian, Michael Ruegg	A 2.5GHz phase-switching PLL using a supply controlled 2-delay-stage 10GHz ring oscillator for improved jitter/mismatch.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
8	Wei-Ta Chen, Jen-Chien Hsu, Hong-Wen Lune, Chauchin Su	A spread spectrum clock generator for SATA-II.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
8	Jianxin Zhang, Paul V. Brennan, Dai Jiang, E. Vinogradova, P. D. Smith	Stability analysis of a sigma delta modulator.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
8	Amr M. Fahim, Mohamed I. Elmasry	A low-power CMOS frequency synthesizer design methodology for wireless applications.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
6	Qiaochu Zhang, Hsiang-Chun Cheng, Shiyu Su, Mike Shuo-Wei Chen	Fractional-N Digital MDLL With Injection-Error Scrambling and Calibration.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
6	Zonglin Ye, Xinlin Geng, Yao Xiao, Qian Xie, Zheng Wang 0050	A Sub-50-fsrms Jitter Fractional-N CPPLL Based on a Dual-DTC-Assisted Time-Amplifying Phase-Frequency Detector With Cascadable DTC Nonlinearity Compensation Algorithm.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
6	Juyeop Kim, Yongwoo Jo, Hangi Park, Taeho Seong, Younghyun Lim, Jaehyouk Choi	A 12.8-15.0-GHz Low-Jitter Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
6	Liqun Feng, Woogeun Rhee, Zhihua Wang 0001	A DTC-Free Fractional-N BBPLL With FIR-Embedded Injection-Locked-Oscillator-Based Phase-Domain Lowpass Filter.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
6	Seheon Jang, Munjae Chae, Hangi Park, Chanwoong Hwang, Jaehyouk Choi	10.2 A 5.5μs-Calibration-Time, Low-Jitter, and Compact-Area Fractional-N Digital PLL Using the Recursive-Least-Squares (RLS) Algorithm.	ISSCC	2024	DBLP DOI BibTeX RDF
6	Michele Rossoni, Simone Mattia Dartizio, Francesco Tesolin, Giacomo Castoro, Riccardo Dell'Orto, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino	10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and -252.4dB FoM.	ISSCC	2024	DBLP DOI BibTeX RDF
6	Liqun Feng, Xuansheng Ji, Longhao Kuang, Qianxian Liao, Su Han, Jiahao Zhao, Woogeun Rhee, Zhihua Wang 0001	14.7 A 0.45V 0.72mW 2.4GHz Bias-Current-Free Fractional-N Hybrid PLL Using a Voltage-Mode Phase Interpolator in 28nm CMOS.	ISSCC	2024	DBLP DOI BibTeX RDF
6	David Murphy, Dihang Yang, Hooman Darabi, Arya Behzad	A Calibration-Free Fractional-N Analog PLL With Negligible DSM Quantization Noise.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
6	Simone Mattia Dartizio, Francesco Tesolin, Giacomo Castoro, Francesco Buccoleri, Michele Rossoni, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino	A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
6	Zhong Gao, Jingchu He, Martin Fritz, Jiang Gong, Yiyu Shen, Zhirui Zong, Peng Chen 0022, Gerd Spalink, Ben Eitel, Morteza S. Alavi, Robert Bogdan Staszewski, Masoud Babaie	A Low-Spur Fractional-N PLL Based on a Time-Mode Arithmetic Unit.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
6	Francesco Buccoleri, Simone Mattia Dartizio, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino	A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
6	Yu Zhao, Onur Memioglu, Long Kong, Behzad Razavi	A 56-GHz Fractional-N PLL With 110-fs Jitter.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
6	Dawei Mai, Michael Peter Kennedy	Optimized MASH-SR Divider Controller for Fractional-N Frequency Synthesizers.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
6	Junlin Zhong, Xiaofeng Yang 0004, Rui Paulo Martins, Yan Zhu 0001, Chi-Hang Chan	A 0.016mm2 Active Area 4GHz Fully Ring-Oscillator-Based Cascaded Fractional-N PLL With Burst-Mode Sampling.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
6	Kyungmin Lee, Jaehong Jung, Seungjin Kim, Seunghyun Oh, Jongwoo Lee, Sung Min Park 0001	A 208-MHz, 0.75-mW Self-Calibrated Reference Frequency Quadrupler for a 2-GHz Fractional-N Ring-PLL in 4-nm FinFET CMOS.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
6	Abdul Muqueem, Shanky Saxena, Govind Singh Patel	An Ultra-Low-Power C-Band FMCW Transmitter Using a Fast Settling Fractional-N DPLL and Ring-Based Pulse Injection Locking Oscillator.	J. Circuits Syst. Comput.	2023	DBLP DOI BibTeX RDF
6	Zirui Jin, Xiaoyu Shan, Ang Hu, Dongsheng Liu, Xuan Cheng, Jinsong Cui, Chengcheng Zhang, Jianming Lei	A DTC-based Fractional-N DPLL using probability-density-shaping spur immunity and Q-noise reduction techniques for IoT applications.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
6	Hui Li, Changchun Zhang, Yi Zhang, Jing Wang	A fractional-N frequency synthesizer with phase synchronization and programmable phase control capability.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
6	Zirui Jin, Ang Hu, Xiaoyu Shan, Chengcheng Zhang, Jinsong Cui, Jianming Lei, Dongsheng Liu	A Fractional-N CP-PLL with fast two-point modulation calibration using duty-cycle and polarity tracking technique in 110-nm CMOS.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
6	Yantian Xu, Zhiyu Wang, Jiarui Liu 0001, Hua Chen, Faxin Yu	Multi-chip phase synchronization circuit of fractional-N PLL.	IEICE Electron. Express	2023	DBLP DOI BibTeX RDF
6	Xu Wang, Michael Peter Kennedy	Performance Limits of Fractional-N Digital PLLs with Mid-Rise TDCs.	PRIME	2023	DBLP DOI BibTeX RDF
6	Wenqiang Huang, Yanshu Guo, Yaoyu Li, Zhihua Wang 0001, Yuanjin Zheng, Tiefu Li, Hanjun Jiang, Wen Jia	A 1-1.7 GHz Cryogenic Fractional-N CP-PLL for Quantum Computing Applications.	MWSCAS	2023	DBLP DOI BibTeX RDF
6	Junjie Li, Youming Zhang, Yunqi Cao, Xusheng Tang, Fengyi Huang	A Unity Feedback Length-Extend Delta-Sigma Modulator for Fractional-N Frequency Synthesizer.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
6	Xu Wang, Michael Peter Kennedy	Comparison of DTC-Related Spurs in Fractional-N Digital PLLs with MASH-and-ENOP-based Divider Controllers.	ICECS	2023	DBLP DOI BibTeX RDF
6	Xu Lu, Michael Peter Kennedy	Further Insights into Spur Immunity in MASH-Based Fractional-N CP-PLLs with Polynomial Nonlinearities.	ICECS	2023	DBLP DOI BibTeX RDF
6	Xinyu Shen, Zhao Zhang 0004, Guike Li, Yong Chen, Nan Qi, Jian Liu 0021, Nanjian Wu, Liyuan Liu	A 4-12.1-GHz Fractional-N Ring Sampling PLL Based on Adaptively-Biased PD-Merged DTC Achieving -37.6± 0.9-dBc Integrated Phase Noise, 261.9-fs RMS Jitter, and -240.6-dB FoM.	ESSCIRC	2023	DBLP DOI BibTeX RDF
6	Xu Wang, Michael Peter Kennedy	Linearized Analysis of Mid-Rise TDCs for Integer-N and Fractional-N Digital PLLs.	NEWCAS	2023	DBLP DOI BibTeX RDF
6	Liqun Feng, Woogeun Rhee, Zhihua Wang 0001	A 2.6GHz ΔΣ Fractional-N Bang-Bang PLL with FIR-Embedded Injection-Locking Phase-Domain Low-Pass Filter.	CICC	2023	DBLP DOI BibTeX RDF
6	Wen Chen, Yiyang Shu, Xun Luo	A 21.8-41.6GHz Fractional-N Sub-Sampling PLL with Dividerless Unequal-REF-Delay Frequency-Locked Loop Achieving -246.9dB FoMj and -270.3dB FoMj,N.	CICC	2023	DBLP DOI BibTeX RDF