Search results for "inverter"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
103	Hiroki Morizumi, Jun Tarui	Linear-Size Log-Depth Negation-Limited Inverter for k -Tonic Binary Sequences.	TAMC	2007	DBLP DOI BibTeX RDF	negation-limited circuit, k-tonic, circuit complexity, inverter
72	Suwon Lee, Sung-Hun Lim	Operational Characteristics of Intelligent Dual-Reactor with Current Controlled Inverter.	KES (1)	2005	DBLP DOI BibTeX RDF	dual-reactor, current controlled inverter, fault current, reactive power
62	Sardis Azongha, Hui Li	Modeling and simulation of the dynamic control of a cascaded multilevel inverter using single DC source for induction motor drive application.	SCSC	2007	DBLP BibTeX RDF	dynamic modulation control, multilevel inverter, induction motor
62	Huibo Lou, Chengxiong Mao, Jiming Lu, Dan Wang 0008, Luonan Chen	Double Three-Level Inverter Based Variable Frequency Drive with Minimal Total Harmonic Distortion Using Particle Swarm Optimization.	ICIC (1)	2007	DBLP DOI BibTeX RDF	three-level inverter, total harmonic distortion, particle swarm optimization, pulse width modulation
61	Luigi Egiziano, Nicola Femia, D. Granozio, Giovanni Petrone, Giovanni Spagnuolo, Massimo Vitelli	Photovoltaic inverters with Perturb&Observe MPPT technique and one-cycle control.	ISCAS	2006	DBLP DOI BibTeX RDF
61	Surya Shankar Dan, Santanu Mahapatra	Analysis of the Energy Quantization Effects on Single Electron Inverter Performance through Noise Margin Modeling.	VLSI Design	2009	DBLP DOI BibTeX RDF
61	Toshiro Akino, Kei Matsuura, Akiyoshi Yasunaga	A high-speed domino CMOS full adder driven by a new unified-BiCMOS inverter.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
61	Mohamed Hafed, Mourad Oulmane, Nicholas C. Rumin	Delay and current estimation in a CMOS inverter with an RC load.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
61	Itsda Boonyaroonate, Shinsaku Mori	Compact DC/AC inverter for large electroluminescent lamp.	ISCAS (3)	2001	DBLP DOI BibTeX RDF
61	C. M. Wu, Wing Hong Lau, Henry Shu-Hung Chung	A five-level neutral-point-clamped H-bridge PWM inverter with superior harmonics suppression: a theoretical analysis.	ISCAS (5)	1999	DBLP DOI BibTeX RDF
61	Labros Bisdounis, Odysseas G. Koufopavlou, Constantinos E. Goutis, Spiridon Nikolaidis 0001	Switching Response Modeling of the CMOS Inverter for Sub-micron Devices.	DATE	1998	DBLP DOI BibTeX RDF	CMOS circuits timing analysis, Propagation delay modeling, Sub-micron devices
52	Kazuo Iwama, Hiroki Morizumi, Jun Tarui	Negation-Limited Complexity of Parity and Inverters.	Algorithmica	2009	DBLP DOI BibTeX RDF	Negation-limited circuit, Parity function, Inversion complexity, Gate elimination, Circuit complexity, Inverter
52	Runqing Zhu, Lixin Lu, Limin Li, Huan You	The Application of Inverter-Driven Technology on the Crimping Machine.	PROLAMAT	2006	DBLP DOI BibTeX RDF	Inverter-driven, Adjustable-speed Motor, Crimping Machine, Controller
51	Tadashi Suetsugu, Marian K. Kazimierczuk	Integration of class DE inverter for on-chip DC-DC power supplies.	ISCAS	2006	DBLP DOI BibTeX RDF
51	Itsda Boonyaroonate, Shinsaku Mori	A compact DC/AC inverter for automotive application.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
41	Karel Jezernik	Hybrid Approach in Power Electronics and Motion Control.	Towards Intelligent Engineering and Information Technology	2009	DBLP DOI BibTeX RDF
41	Hiroki Morizumi, Genki Suzuki	Negation-Limited Inverters of Linear Size.	ISAAC	2008	DBLP DOI BibTeX RDF
41	Thomas Dowrick, Steve Hall, Liam McDaid, Octavian Buiu, Peter M. Kelly	A Biologically Plausible Neuron Circuit.	IJCNN	2007	DBLP DOI BibTeX RDF
41	Jagdish G. Chaudhari, Sandeep K. Mude, Prakash G. Gabhane	High Performance Direct Torque Control of Induction Motor using Space Vector Modulation.	CCECE	2006	DBLP DOI BibTeX RDF
41	Tony Pialis, Khoman Phang	Analysis of timing jitter in ring oscillators due to power supply noise.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
41	Antonio Zenteno, Víctor H. Champac	Resistive Opens in a Class of CMOS Latches: Analysis and DFT.	VTS	2001	DBLP DOI BibTeX RDF
40	Mahmoud Shaker, Imadeddin Abdalla Abdalla	Integration-duty cycle conversion as novel digital algorithm for PWM inverter.	EIT	2008	DBLP DOI BibTeX RDF
40	Shao-Lin Li, Ping Yang	Research on a SPWM Inverter Power Supply System Based on DSP.	CSSE (4)	2008	DBLP DOI BibTeX RDF
40	Junfeng Fan, Ingrid Verbauwhede	Unified Digit-Serial Multiplier and Inverter in Finite Field GF(2m).	HOST	2008	DBLP DOI BibTeX RDF
40	Hirotaka Koizumi, Kosuke Kurokawa	Class DE Inverter with Asymmetric Shunt Capacitors.	ISCAS	2007	DBLP DOI BibTeX RDF
40	Emine Dogru Bolat	DSP Based Implementation of Current Mode Fuzzy Gain Scheduling of PI Controller for Single Phase UPS Inverter.	KES (1)	2006	DBLP DOI BibTeX RDF
40	Hirotaka Koizumi, Kosuke Kurokawa, Shinsaku Mori	Thinned-out controlled class D inverter with delta-sigma modulated 1-bit driving pulses.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
40	Hirak Patangia, Tandi Wijaya, Dennis Gregory	A multi-level inverter for driving a high voltage display.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
40	Hiroo Sekiya, Hirotaka Koizumi, Shinsaku Mori, Iwao Sasase	FM/PWM control scheme on class DE inverter for keeping high power conversion efficiency.	ISCAS (3)	2001	DBLP DOI BibTeX RDF
40	Chung-Yu Wu, Ming-Chuen Shiau	Efficient physical timing models for CMOS AND-OR-inverter and OR-AND-inverter gates and their applications.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
32	Fengwen Cao, Yiwang Wang	Design of a Single-Phase Grid-Connected Photovoltaic Systems Based on Fuzzy-PID Controller.	ICIC (2)	2009	DBLP DOI BibTeX RDF	photovoltaic system, DC/AC inverter, grid-connected, Fuzzy-PID control
32	Taufik, Makbul Anwari	Modeling and Simulation of Current Ripple in DC Link Connecting Two PWM Inverters Using Matlab/Simulink.	Asia International Conference on Modelling and Simulation	2008	DBLP DOI BibTeX RDF	DC bus Current Ripple, PWM Inverter
32	Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton	DAG-aware AIG rewriting a fresh look at combinational logic synthesis.	DAC	2006	DBLP DOI BibTeX RDF	NPN equivalence, and-inverter graphs, technology-independent logic synthesis, technology mapping
32	Qi Zhu 0002, Nathan Kitchen, Andreas Kuehlmann, Alberto L. Sangiovanni-Vincentelli	SAT sweeping with local observability don't-cares.	DAC	2006	DBLP DOI BibTeX RDF	SAT sweeping, and/inverter graphs, observability
32	Stephen K. Sunter	A low cost 100 MHz analog test bus.	VTS	1995	DBLP DOI BibTeX RDF	analog test bus, on-chip analog bus, digital three-state inverter, low-input capacitance, signal bandwidth, bus input, design for testability, DFT, integrated circuit design, mixed-signal circuits, capacitance, mixed analogue-digital integrated circuits, IC design, 100 MHz
32	Shih-Chang Hsia, Wen-Ching Lee	A Very Low-Power Flash A/D Converter Based on Cmos Inverter Circuit.	IWSOC	2005	DBLP DOI BibTeX RDF	CMOS inverter, flash, A/D converter
30	Behnam Amelifard, Farzan Fallah, Massoud Pedram	Low-Power Fanout Optimization Using Multi Threshold Voltages and Multi Channel Lengths.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
30	Li Ke 0002, Reuben Wilcock, Peter R. Wilson	Improved 6.7GHz CMOS VCO delay cell with up to seven octave tuning range.	ISCAS	2008	DBLP DOI BibTeX RDF
30	Kazuo Iwama, Hiroki Morizumi, Jun Tarui	Negation-Limited Complexity of Parity and Inverters.	ISAAC	2006	DBLP DOI BibTeX RDF
30	Pinar Korkmaz, Bilge Saglam Akgul, Krishna V. Palem	Ultra-Low Energy Computing with Noise: Energy-Performance-Probability Trade-offs.	ISVLSI	2006	DBLP DOI BibTeX RDF
30	Tzyy-Kuen Tien, Jing-Jou Tang, Kuan-Jou Chen	A new high speed dynamic PLA.	ISCAS	2006	DBLP DOI BibTeX RDF
30	Bor-Ren Lin, Chun-Hao Huang, Zheng-Zhang Yang	Three-phase active power filter under unbalanced condition.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
30	Domingo Biel, Rafael Ramos, Francesc Guinjoan, Juan J. Negroni, Carlos Meza	Sliding-mode control design of parallel-connected switching converters for modular transformerless DC-AC step-up conversion.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
30	Ali Bastani, Charles A. Zukowski	Design of superbuffers in sub-100nm CMOS technologies with significant gate leakage.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	gate leakage reduction, superbuffers, low power design
30	Yngvar Berg, Snorre Aunet, Øivind Næss, Johannes Goplen Lomsdalen, Mats Høvin	Exploiting hyperbolic functions to increase linearity in low-voltage floating-gate transconductance amplifiers.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
30	Ki-Wook Kim, Taewhan Kim, C. L. Liu 0001, Sung-Mo Kang	Domino logic synthesis based on implication graph.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
30	Yngvar Berg, Snorre Aunet, Øivind Næss, Henning Gundersen, Mats Høvin	Extreme low-voltage floating-gate CMOS transconductance amplifier.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
30	Ki-Wook Kim, C. L. Liu 0001, Sung-Mo Kang	Implication graph based domino logic synthesis.	ICCAD	1999	DBLP DOI BibTeX RDF
30	Yang Hu, Liuchen Chang, Bo Cao	Novel predictive voltage controlled UPS inverter for an improved stand-alone wind turbine system.	CCECE	2009	DBLP DOI BibTeX RDF
30	Hirotaka Koizumi	Delta-sigma modulated class D ZCS series resonant inverter with an inductive load.	ISCAS	2008	DBLP DOI BibTeX RDF
30	Ming Li, Dong Dai, Xikui Ma, Herbert H. C. Iu	Fast-scale period-doubling bifurcation in voltage-mode controlled full-bridge inverter.	ISCAS	2008	DBLP DOI BibTeX RDF
30	Louis R. Nerone	Analytical solutions of the Class D inverter.	ISCAS	2008	DBLP DOI BibTeX RDF
30	Guilian Guo, Wenxia You	Quality Analysis of SVPWM Inverter Output Voltage.	CSSE (4)	2008	DBLP DOI BibTeX RDF
30	Zhangcai Huang, Hong Yu 0013, Atsushi Kurokawa, Yasuaki Inoue	Modeling the Overshooting Effect for CMOS Inverter in Nanometer Technologies.	ASP-DAC	2007	DBLP DOI BibTeX RDF
30	Chua-Chin Wang, Gang-Neng Sung, Kuan-Wen Fang, Sheng-Lun Tseng	A Low-power Sensorless Inverter Controller of Brushless DC Motors.	ISCAS	2007	DBLP DOI BibTeX RDF
30	Yngvar Berg, Omid Mirmotahari, Snorre Aunet	Pseudo Floating-Gate Inverter with Feedback Control.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
30	Hirotaka Koizumi, Kosuke Kurokawa, Shinsaku Mori	A comparison of output envelope waveforms of the delta-sigma modulated class D series resonant inverter.	ISCAS	2006	DBLP DOI BibTeX RDF
30	Satoshi Akatsu, Hiroyuki Torikai, Toshimichi Saito	Current-mode instantaneous state setting method and its application to an H-bridge inverter.	ISCAS	2006	DBLP DOI BibTeX RDF
30	Shih-Ming Chen, Tsorng-Juu Liang, Jiann-Fuh Chen	Single DC/AC CCFL Inverter for Large Size LCD TV with Burst Control.	APCCAS	2006	DBLP DOI BibTeX RDF
30	Dan Sun, Jun Meng, Zongyuan He	Diagnosis of Inverter Faults in PMSM DTC Drive Using Time-Series Data Mining Technique.	ADMA	2006	DBLP DOI BibTeX RDF
30	Mariam Momenzadeh, Jing Huang 0001, Mehdi Baradaran Tahoori, Fabrizio Lombardi	Characterization, test, and logic synthesis of and-or-inverter (AOI) gate design for QCA implementation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
30	Jing Huang 0001, Mariam Momenzadeh, Mehdi Baradaran Tahoori, Fabrizio Lombardi	Design and characterization of an and-or-inverter (AOI) gate for QCA implementation.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	defect characterization, test, QCA
30	Yarallah Koolivand, Ali Zahabi, Nasser Masoumi	Modeling of polysilicide gate resistance effect on inverter delay and power consumption using distributed RC method and branching technique.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	polysilicide gate resistance, short circuit power, performance degradation, propagation delay
30	S. Bumrungkeeree, Itsda Boonyaroonate	Push-pull dc/ac inverter for large electroluminescent lamp.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
30	Ramdan Razali, V. Subbiah, M. A. Choudhury, Rahimi Yusof	Performance analysis of online dual slope delta modulated PWM inverter.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
30	A. B. Bhattacharyya, Shrutin Ulman	PREDICTMOS MOSFET Model and its Application to Submicron CMOS Inverter Delay Analysis.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
30	V. Vongmanee	The vector control inverter for a PV motor drive system implemented by a single chip DSP controller ADMC331.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
30	Rui Wang, Kaushik Roy 0001, Cheng-Kok Koh	Short-circuit power analysis of an inverter driving an RLC load.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
30	Daisuke Kawamoto, Hiroo Sekiya, Hirotaka Koizumi, Iwao Sasase	Design of a generalized phase-controlled class E inverter.	ISCAS (3)	2001	DBLP DOI BibTeX RDF
30	C. M. Wu, Wing Hong Lau, Henry Shu-Hung Chung	Generic analytical solution for calculating the harmonic characteristics of multilevel sinusoidal PWM inverter.	ISCAS (5)	1999	DBLP DOI BibTeX RDF
30	Abdolreza Nabavi-Lishi, Nicholas C. Rumin	Inverter models of CMOS gates for supply current and delay evaluation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
30	James B. Kuo, Tsen-Shau Yang, Robert W. Dutton, Bruce A. Wooley	Two-dimensional transient analysis of a collector-up ECL inverter.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
30	Pramod V. Argade	Sizing an inverter with a precise delay: generation of complementary signals with minimal skew and pulsewidth distortion in CMOS.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
30	Vivek R. S, Tutan Debnath, K. Gopakumar 0001, Loganathan Umanand, Dariusz Zielinski	A 5 Level Inverter Using a 3 Level Inverter and a Capacitor Fed 2 Level Inverter Feeding an IM Drive from Both Sides with Extended Linear Modulation Range Till Full Base Speed.	IECON	2023	DBLP DOI BibTeX RDF
22	Feng Lv, Hua Zhao, Wenxia Du, Huilong Jin	Electromagnetic Interference and Electromagnetic Compatibility Test Technology.	MVHI	2010	DBLP DOI BibTeX RDF	ElectromagneticInterference, Electromagnetic Compatibility, Microwave oven, Inverter
22	Ramen Dutta, Tarun Kanti Bhattacharyya, Xiang Gao 0002, Eric A. M. Klumperink	Optimized Stage Ratio of Tapered CMOS Inverters for Minimum Power and Mismatch Jitter Product.	VLSI Design	2010	DBLP DOI BibTeX RDF	tapering factor, stage ratio, CMOS inverter, mismatch jitter, multiphase clock, low power, figure of merit
22	Praveen Kumar 0001, Pavol Bauer	Progressive design methodology for complex engineering systems based on multiobjective genetic algorithms and linguistic decision making.	Soft Comput.	2009	DBLP DOI BibTeX RDF	BLDC motors, Voltage source inverter, Multi-objective optimization (MOOP), Genetic algorithms, PDM, Linguistic variables, Multi attribute decision making
22	Lixin Pang, Hui Wang, Yuxia Li, Jian Wang, Ziyu Wang	Analysis of Photovoltaic Charging System Based on MPPT.	PACIIA (2)	2008	DBLP DOI BibTeX RDF	Photovoltaic Charging, Asymmetric Control, Inverter, MPPT
22	Jan Jerabek, Kamil Vrba	RF Pure Current-Mode Filters using Current Mirrors and Inverters. (PDF / PS)	PWC	2007	DBLP DOI BibTeX RDF	pure current mode, current mirror, current inverter, CMI, GCMI, frequency filter
22	Christoph Bartoschek, Stephan Held, Dieter Rautenbach, Jens Vygen	Efficient generation of short and fast repeater tree topologies.	ISPD	2006	DBLP DOI BibTeX RDF	inverter tree, repeater tree, buffering, tree topology, rectilinear Steiner tree
22	Jin S. Zhang, Alan Mishchenko, Robert K. Brayton, Malgorzata Chrzanowska-Jeske	Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability.	DAC	2006	DBLP DOI BibTeX RDF	and-inverter graphs, classical symmetries, simulation, boolean functions, boolean satisfiability
22	Stanislaw J. Piestrak	Design Method of a Class of Embedded Combinational Self-Testing Checkers for Two-Rail Codes.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	embedded circuit, inverter-free circuit, totally self-testing circuit, concurrent error detection, Berger code, self-testing checker, two-rail code
22	Motoi Inaba, Koichi Tanno, Okihiko Ishizuka	Multi-Valued Flip-Flop with Neuron-CMOS NMIN Circuits.	ISMVL	2002	DBLP DOI BibTeX RDF	Multi-valued flip-flop, Down literal circuit, Analog inverter, Voltage comparator, NMIN circuit
22	Jincheol Yoo, Daegyu Lee, Kyusun Choi, Jongsoo Kim	A power and resolution adaptive flash analog-to-digital converter.	ISLPED	2002	DBLP DOI BibTeX RDF	TIQ comparator, flash ADC, inverter quantization, adaptive, threshold, analog-to-digital converter
22	Richard Martel, V. Derycke, Jörg Appenzeller, Shalom J. Wind, Phaedon Avouris	Carbon nanotube field-effect transistors and logic circuits.	DAC	2002	DBLP DOI BibTeX RDF	FET, SWNT, Schottky barrier, field-effect transistor, circuits, carbon nanotube, nanoelectronics, logic gate, inverter, semiconductor
20	Yngvar Berg, Omid Mirmotahari	Low voltage precharge CMOS logic.	DDECS	2009	DBLP DOI BibTeX RDF
20	Jeremy R. Tolbert, Saibal Mukhopadhyay	Accurate buffer modeling with slew propagation in subthreshold circuits.	ISQED	2009	DBLP DOI BibTeX RDF
20	Md. Arifujjaman, Mohammad Tariq Iqbal, John E. Quaicoe	A comparative study of the reliability of the power electronics in grid connected small wind turbine systems.	CCECE	2009	DBLP DOI BibTeX RDF
20	Nishant Chandra, Apoorva Kumar Yati, A. B. Bhattacharyya	Extended-Sakurai-Newton MOSFET Model for Ultra-Deep-Submicrometer CMOS Digital Design.	VLSI Design	2009	DBLP DOI BibTeX RDF
20	S. Ramasamy, B. Venkataramani, R. Niranjini, K. Suganya	100KHz-20MHz Programmable Subthreshold Gm-C Low-Pass Filter in 0.18µ-m CMOS.	VLSI Design	2009	DBLP DOI BibTeX RDF
20	Taro Niiyama, Piao Zhe, Koichi Ishida, Masami Murakata, Makoto Takamiya, Takayasu Sakurai	Dependence of Minimum Operating Voltage (VDDmin) on Block Size of 90-nm CMOS Ring Oscillators and its Implications in Low Power DFM.	ISQED	2008	DBLP DOI BibTeX RDF
20	S. Ramasamy, B. Venkataramani, K. Anbugeetha	VLSI Implementation of a Digitally Tunable Gm-C Filter with Double CMOS Pair.	VLSI Design	2008	DBLP DOI BibTeX RDF
20	Gabriel Schulhof, Konrad Walus, Graham A. Jullien	Simulation of random cell displacements in QCA.	ACM J. Emerg. Technol. Comput. Syst.	2007	DBLP DOI BibTeX RDF	fabrication variances, fault tolerance, QCA, Quantum-dot cellular automata
20	T. Satish, Krushna K. Mohapatra, Ned Mohan	Carrier-based control of matrix converter in linear and over-modulation modes.	SCSC	2007	DBLP BibTeX RDF	over-modulation, matrix converter, pulse-width modulation
20	Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi 0001, Masahiko Yoshimoto	A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing.	ISVLSI	2007	DBLP DOI BibTeX RDF
20	Tadayoshi Enomoto, Suguru Nagayama, Nobuaki Kobayashi	Low-Power High-Speed 180-nm CMOS Clock Drivers.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.640 ns, CMOS clock drivers, register array, delay flip-flops, 251 muW, CMOS technology, power dissipation, delay time, 0.18 micron
20	Yongkui Man, Wenyan Li	A Novel Method of Energy Saving for Nodding Donkey Oil Pump.	ICIC (1)	2007	DBLP DOI BibTeX RDF	Nodding Donkey oil pump, oil-pumping units, Fuzzy PD Controller, Asynchronous Motor, beam pumping units, energy saving
20	Ali Ahmed Adam, Kayhan Gulez, Nuh Erdogan	Minimum Torque Ripple Algorithm with Fuzzy Logic Controller for DTC of PMSM.	ICIC (1)	2007	DBLP DOI BibTeX RDF	Interior Permanent Magnet Synchronous Motor, Torque Ripple, Fuzzy Logic, Direct Torque Control
20	Nishant Patil, Jie Deng, H.-S. Philip Wong, Subhasish Mitra	Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits.	DAC	2007	DBLP DOI BibTeX RDF
20	Yajun Ran, Malgorzata Marek-Sadowska	Designing via-configurable logic blocks for regular fabric.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF