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1988-2001 (18) 2002 (23) 2003 (34) 2004 (50) 2005 (29) 2006 (38) 2007 (15) 2008 (17) 2009-2011 (15) 2012-2018 (3)
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article(46) inproceedings(194) phdthesis(2)
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Found 242 publication records. Showing 242 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
95Lisa Higham, LillAnne Jackson, Jalal Kawash Capturing Register and Control Dependence in Memory Consistency Models with Applications to the Itanium Architecture. Search on Bibsonomy DISC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Multiprocessor memory consistency, register and control dependency, process coordination, Itanium
95Lisa Higham, LillAnne Jackson Translating between itanium and sparc memory consistency models. Search on Bibsonomy SPAA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF multiprocessors, program transformations, memory consistency models, sparc, itanium
84Lisa Higham, LillAnne Jackson, Jalal Kawash Programmer-Centric Conditions for Itanium Memory Consistency. Search on Bibsonomy ICDCN The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Programmer-centric memory consistency, Itanium multiprocessor
84Bruce Greer, John Harrison 0001, Greg Henry, Wei Wayne Li, Ping Tak Peter Tang Scientific computing on the Itanium processor. Search on Bibsonomy SC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF fused multiply-add, itanium (TM) processor, linear algebra, Intel, EPIC, transcendental functions
83Tatiana Shpeisman, Guei-Yuan Lueh, Ali-Reza Adl-Tabatabai Just-In-Time Java? Compilation for the Itanium® Processor. Search on Bibsonomy IEEE PACT The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
72Perry H. Wang, Jamison D. Collins, Hong Wang 0003, Dongkeun Kim, Bill Greene, Kai-Ming Chan, Aamir B. Yunus, Terry Sych, Stephen F. Moore, John Paul Shen Helper threads via virtual multithreading on an experimental itanium® 2 processor-based platform. Search on Bibsonomy ASPLOS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF DB2 database, cache miss prefetching, itanium processor, switch-on-event, multithreading, helper thread, PAL
71Chih Jeng Kenneth Tan, David Hagan, Matthew F. Dixon A Performance Comparison of Matrix Solvers on Compaq Alpha, Intel Itanium, and Intel Itanium II Processors. Search on Bibsonomy ICCSA (1) The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Systems of linear algebraic equations, Architecture specific tuning, Linear solver
71Kazuyoshi Furukawa, Masahiko Takenaka, Kouichi Itoh A Fast RSA Implementation on Itanium 2 Processor. Search on Bibsonomy ICICS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Ita- 2, RSA, Montgomery multiplication, software implementation
71Leonid Baraz, Tevi Devor, Orna Etzion, Shalom Goldenberg, Alex Skaletsky, Yun Wang, Yigel Zemach IA-32 Execution Layer: a two-phase dynamic translator designed to support IA-32 applications on Itanium-based systems. Search on Bibsonomy MICRO The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Intel
71Alex Settle, Daniel A. Connors, Gerolf Hoflehner, Daniel M. Lavery Optimization for the Intel® Itanium ®Architectur Register Stack. Search on Bibsonomy CGO The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
60Gerrit Saylor, Badriddine Khessib Large scale Itanium® 2 processor OLTP workload characterization and optimization. Search on Bibsonomy DaMoN The full citation details ... 2006 DBLP  DOI  BibTeX  RDF cache coherency, data partitioning, performance characterization, profile guided optimization, OLTP, software optimization, Itanium, ccNUMA
60Harish Patil, Robert S. Cohn, Mark Charney, Rajiv Kapoor, Andrew Sun, Anand Karunanidhi Pinpointing Representative Portions of Large Intel® Itanium® Programs with Dynamic Instrumentation. Search on Bibsonomy MICRO The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
60Wenlong Li, Haibo Lin, Yu Chen, Zhizhong Tang Increasing Software-Pipelined Loops in the Itanium-Like Architecture. Search on Bibsonomy ISPA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
60Perry H. Wang, Hong Wang 0003, Jamison D. Collins, Ed Grochowski, Ralph-Michael Kling, John Paul Shen Memory Latency-Tolerance Approaches for Itanium Processors: Out-of-Order Execution vs. Speculative Precomputation. Search on Bibsonomy HPCA The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
60Terry Lyon, Eric Delano, Cameron McNairy, Dean Mulla Data Cache Design Considerations for the Itanium® 2 Processor. Search on Bibsonomy ICCD The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
60Alban Douillet, José Nelson Amaral, Guang R. Gao Fine-Grain Stacked Register Allocation for the Itanium Architecture. Search on Bibsonomy LCPC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
60John Crawford Guest Editor's Introduction: Introducing the Itanium Processors. Search on Bibsonomy IEEE Micro The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
48Utpal Desai, Simon M. Tam, Robert Kim, Ji Zhang, Stefan Rusu Itanium processor clock design. Search on Bibsonomy ISPD The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Itanium processor, deskew, on-die-clock-shrink, clock distribution, IA-64
48Noah Snavely, Saumya K. Debray, Gregory R. Andrews Unpredication, Unscheduling, Unspeculation: Reverse Engineering Itanium Executables. Search on Bibsonomy IEEE Trans. Software Eng. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF EPIC architectures, Reverse engineering, speculation, code optimization, predication
48Roland E. Wunderlich, James C. Hoe In-system FPGA prototyping of an itanium microarchitecture. Search on Bibsonomy FPGA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
48Gerolf Hoflehner, Knud Kirkegaard, Rod Skinner, Daniel M. Lavery, Yong-Fong Lee, Wei Li 0015 Compiler Optimizations for Transaction Processing Workloads on Itanium® Linux Systems. Search on Bibsonomy MICRO The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
48Chi-Keung Luk, Robert Muth, Harish Patil, Robert S. Cohn, P. Geoffrey Lowney Ispike: A Post-link Optimizer for the Intel®Itanium®Architecture. Search on Bibsonomy CGO The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
48Roland E. Wunderlich, James C. Hoe In-System FPGA Prototyping of an Itanium Microarchitecture. Search on Bibsonomy ICCD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
48Cameron McNairy, Don Soltis Itanium 2 Processor Microarchitecture. Search on Bibsonomy IEEE Micro The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
48Jean-Francois Collard, Daniel M. Lavery Optimizations to Prevent Cache Penalties for the Intel ® Itanium 2 Processor. Search on Bibsonomy CGO The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
48Noah Snavely, Saumya K. Debray, Gregory R. Andrews Unscheduling, Unpredication, Unspeculation: Reverse Engineering Itanium Executables. Search on Bibsonomy WCRE The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
48Haibo Lin, Wenlong Li, Zhizhong Tang Overcoming Static Register Pressure for Software Pipelining in the Itanium Architecture. Search on Bibsonomy APPT The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
48R. David Weldon, Steven S. Chang, Hong Wang 0003, Gerolf Hoflehner, Perry H. Wang, Daniel M. Lavery, John Paul Shen Quantitative Evaluation of the Register Stack Engine and Optimizations for Future Itanium Processors. Search on Bibsonomy Interaction between Compilers and Computer Architectures The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
48Kazuhisa Ishizaka, Takamichi Miyamoto, Jun Shirako, Motoki Obata, Keiji Kimura, Hironori Kasahara Performance of OSCAR Multigrain Parallelizing Compiler on SMP Servers. Search on Bibsonomy LCPC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
36Sebastian Winkel, Rakesh Krishnaiyer, Robyn Sampson Latency-tolerant software pipelining in a production compiler. Search on Bibsonomy CGO The full citation details ... 2008 DBLP  DOI  BibTeX  RDF latency-tolerant scheduling, load clustering, compiler, code generation, prefetching, software pipelining, modulo scheduling, memory latency, memory-level parallelism, itanium, epic
36Eric S. Fetzer Using Adaptive Circuits to Mitigate Process Variations in a Microprocessor Design. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF dual core, Itanium microprocessor, Montecito, adaptive circuits, cache safe technology, active clock deskew, process variation, power measurement
36Ivan D. Baev, Richard E. Hank, David H. Gross Prematerialization: reducing register pressure for free. Search on Bibsonomy PACT The full citation details ... 2006 DBLP  DOI  BibTeX  RDF rematerialization, register allocation, VLIW, Itanium, register pressure
36Wei-Chung Hsu, Howard Chen 0002, Pen-Chung Yew, Dong-yuan Chen On the Predictability of Program Behavior Using Different Input Data Sets. Search on Bibsonomy Interaction between Compilers and Computer Architectures The full citation details ... 2002 DBLP  DOI  BibTeX  RDF SPEC2000int, profiles, performance simulation, Itanium, profile-based optimization
36Darshan Desai, Gerolf Hoflehner, Arun Kejariwal, Daniel M. Lavery, Alexandru Nicolau, Alexander V. Veidenbaum, Cameron McNairy Performance Characterization of Itanium® 2-Based Montecito Processor. Search on Bibsonomy SPEC Benchmark Workshop The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
36Jiangjiang Liu 0002, Brian Bell, Tan Truong Analysis and Characterization of Intel Itanium Instruction Bundles for Improving VLIW Processor Performance. Search on Bibsonomy IMSCCS (1) The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
36Cameron McNairy, Rohit Bhatia Montecito: A Dual-Core, Dual-Thread Itanium Processor. Search on Bibsonomy IEEE Micro The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Reliability, Power Management, Cache memories, Multithreaded processors, Testing and Fault-Tolerance
36Stefan Rusu, Harry Muljono, Brian S. Cherkauer Itanium 2 Processor 6M: Higher Frequency and Larger L3 Cache. Search on Bibsonomy IEEE Micro The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
36Carl Scafidi, J. Douglas Gibson, Rohit Bhatia Validating the Itanium 2 Exception Control Unit: A Unit-Level Approach. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
36Sebastian Winkel Exploring the Performance Potential of Itanium® Processors with ILP-based Scheduling. Search on Bibsonomy CGO The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
36Kuang-Kuo Lin, Sudhakar Kale, Aditi Nigam Methodology for Automated Layout Migration for 90 nm Itanium®2 Processor Design. Search on Bibsonomy ISQED The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
36John W. Sias, Sain-Zee Ueng, Geoff A. Kent, Ian M. Steiner, Erik M. Nystrom, Wen-mei W. Hwu Field-testing IMPACT EPIC research results in Itanium 2. Search on Bibsonomy ISCA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
36James W. Thomas Inlining of Mathematical Functions in HP-UX for Itanium ® 2. Search on Bibsonomy CGO The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
36Xinmin Tian, Milind Girkar, Sanjiv Shah, Douglas Armstrong, Ernesto Su, Paul Petersen Compiler and Runtime Support for Running OpenMP Programs on Pentium-and Itanium-Architectures. Search on Bibsonomy HIPS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Hyper-Threading technology, Parallelization, OpenMP, compiler optimization, shared-memory multiprocessor, thread-level parallelism
36Xinmin Tian, Milind Girkar, Sanjiv Shah, Douglas Armstrong, Ernesto Su, Paul Petersen Compiler and Runtime Support for Running OpenMP Programs on Pentium- and Itanium-Architectures. Search on Bibsonomy IPDPS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Hyper-Threading technology, Parallelization, OpenMP, compiler optimization, shared-memory multiprocessor, thread-level parallelism
36Yue Yang, Ganesh Gopalakrishnan, Gary Lindstrom, Konrad Slind Analyzing the Intel Itanium Memory Ordering Rules Using Logic Programming and SAT. Search on Bibsonomy CHARME The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
36Liu Yang, Sun Chan, Guang R. Gao, Roy Ju, Guei-Yuan Lueh, Zhaoqing Zhang Inter-procedural stacked register allocation for itanium® like architecture. Search on Bibsonomy ICS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF hot region, inter-procedural stacked register allocation, quota assignment, register allocation, hotspot
36Jason Stinson, Stefan Rusu A 1.5GHz third generation itanium® 2 processor. Search on Bibsonomy DAC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF on-die cache, reliability, test, design methodology, processor
36William A. Samaras, Naveen Cherukuri, Srinivas Venkataraman The IA-64 Itanium Processor Cartridge. Search on Bibsonomy IEEE Micro The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
36Youngsoo Choi, Allan D. Knies, Luke Gerke, Tin-Fook Ngai The impact of if-conversion and branch prediction on program execution on the Intel Itanium processor. Search on Bibsonomy MICRO The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
36Harsh Sharangpani, Ken Arora Itanium Processor Microarchitecture. Search on Bibsonomy IEEE Micro The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
36Nhon T. Quach High Availability and Reliability in the Itanium Processor. Search on Bibsonomy IEEE Micro The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
36Somnath Ghosh, Abhay Kanhere, Rakesh Krishnaiyer, Dattatraya Kulkarni, Wei Li 0015, Chu-Cheow Lim, John Ng Integrating High-Level Optimizations in a Production Compiler: Design and Implementation Experience. Search on Bibsonomy CC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
24Richard Uhlig, Gil Neiger, Dion Rodgers, Amy L. Santoni, Fernando C. M. Martins, Andrew V. Anderson, Steven M. Bennett, Alain Kägi, Felix H. Leung, Larry Smith 0001 Intel Virtualization Technology. Search on Bibsonomy Computer The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Itanium architecture, IA-32 architecture, virtual machines, computer architectures, software systems, virtualization technology
24Patrick Carribault, Albert Cohen 0001 Applications of storage mapping optimization to register promotion. Search on Bibsonomy ICS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF array contraction, array folding, scheduling, pattern matching, string matching, tiling, blocking, itanium, register promotion
24Branimir Malnar, Goran Zelic Timing closure of clock enable signals on a 32 nm Intel Itanium processor. Search on Bibsonomy MIPRO The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
24Anys Bacha, Radu Teodorescu Dynamic reduction of voltage margins by leveraging on-chip ECC in Itanium II processors. Search on Bibsonomy ISCA The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
24Reid J. Riedlinger, Ron Arnold, Larry Biro, William J. Bowhill, Jason Crop, Kevin Duda, Eric S. Fetzer, Olivier Franza, Tom Grutkowski, Casey Little, Charles Morganti, Gary Moyer, Ashley O. Munch, Mahalingam Nagarajan, Cheolmin Park, Christopher Poirier, Bill Repasky, Edi Roytman, Tejpal Singh, Matthew W. Stefaniw A 32 nm, 3.1 Billion Transistor, 12 Wide Issue Itanium® Processor for Mission-Critical Servers. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
24Steven R. Undy Poulson: An 8 core 32 nm next generation Intel® Itanium® processor. Search on Bibsonomy Hot Chips Symposium The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
24Steve Richfield Dealing with the "itanium effect" (abstract only). Search on Bibsonomy FPGA The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
24Reid J. Riedlinger, Rohit Bhatia, Larry Biro, William J. Bowhill, Eric S. Fetzer, Paul E. Gronowski, Tom Grutkowski A 32nm 3.1 billion transistor 12-wide-issue Itanium® processor for mission-critical servers. Search on Bibsonomy ISSCC The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
24Dilip K. Bhavsar, Steve Poehlman Test access and the testability features of the Poulson multi-core Intel Itanium® processor. Search on Bibsonomy ITC The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
24Pankaj Pant, Joshua Zelman, Glenn Colón-Bonet, Jennifer Flint, Steve Yurash Lessons from at-speed scan deployment on an Intel® Itanium® microprocessor. Search on Bibsonomy ITC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
24Blaine A. Stackhouse, Sal Bhimji, Chris Bostak, Dave Bradley, Brian S. Cherkauer, Jayen Desai, Erin Francom, Mike Gowan, Paul E. Gronowski, Dan Krueger, Charles Morganti, Steve Troyer A 65 nm 2-Billion Transistor Quad-Core Itanium Processor. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
24Andrew Allen, Jay Desai, Frank Verdico, Ferd Anderson, David Mulvihill, Dan Krueger Dynamic frequency-switching clock system on a quad-core Itanium® processor. Search on Bibsonomy ISSCC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
24Blaine A. Stackhouse, Brian S. Cherkauer, Michael K. Gowan, Paul E. Gronowski, Chris Lyles A 65nm 2-Billion-Transistor Quad-Core Itanium® Processor. Search on Bibsonomy ISSCC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
24Dan Krueger, Erin Francom, Jack Langsdorf Circuit Design for Voltage Scaling and SER Immunity on a Quad-Core Itanium® Processor. Search on Bibsonomy ISSCC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
24Jamel Tayeb Optimisation des performances et de la consommation de puissance électrique pour architecture Intel ltanium/EPIC. (Performance and Energy Optimization for Intel Itanium/EPIC architecture for Virtual Machine Support). Search on Bibsonomy 2008   RDF
24Arun Kejariwal, Gerolf Hoflehner, Darshan Desai, Daniel M. Lavery, Alexandru Nicolau, Alexander V. Veidenbaum Comparative characterization of SPEC CPU2000 and CPU2006 on Itanium architecture. Search on Bibsonomy SIGMETRICS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF SPEC CPU benchmarks, performance evaluation, caches, branch prediction
24Eric S. Fetzer, David M. Dahle, Casey Little, Kevin Safford The Parity protected, multithreaded register files on the 90-nm itanium microprocessor. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
24Rich McGowen, Christopher Poirier, Chris Bostak, Jim Ignowski, Mark Millican, Warren H. Parks, Samuel Naffziger Power and temperature control on a 90-nm Itanium family processor. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
24Samuel Naffziger, Blaine A. Stackhouse, Tom Grutkowski, Doug Josephson, Jayen Desai, Elad Alon, Mark Horowitz The implementation of a 2-core, multi-threaded itanium family processor. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
24Tim C. Fischer, Jayen Desai, Bruce Andrew Doyle, Samuel Naffziger, Ben Patella A 90-nm variable frequency clock system for a power-managed itanium architecture processor. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
24Lisa Higham, LillAnne Jackson, Jalal Kawash What is Itanium Memory Consistency from the Programmer's Point of View? Search on Bibsonomy TV@FLoC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
24William Jalby, Christophe Lemuet, Sid Ahmed Ali Touati An efficient memory operations optimization technique for vector loops on Itanium 2 processors. Search on Bibsonomy Concurr. Comput. Pract. Exp. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
24Jonathan Chang, Stefan Rusu, Jonathan Shoemaker, Simon Tam 0001, Ming Huang, Mizan Haque, Siufu Chiu, Kevin Truong, Mesbah Karim, Gloria Leong, Kiran Desai, Richard Goe, Sandhya Kulkarni A 130-nm triple-Vt 9-MB third-level on-die cache for the 1.7-GHz Itanium® 2 processor. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
24Markus Mock, Ricardo Villamarín-Salomón, José Baiocchi An empirical study of data speculation use on the Intel Itanium 2 processor. Search on Bibsonomy Interaction between Compilers and Computer Architectures The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
24Charles Gray, Matthew Chapman, Peter Chubb, David Mosberger, Gernot Heiser Itanium - A System Implementor's Tale(Awarded General Track Best Student Paper Award!). Search on Bibsonomy USENIX Annual Technical Conference, General Track The full citation details ... 2005 DBLP  BibTeX  RDF
24Simon Tam 0001, Rahul Dilip Limaye, Utpal Nagarji Desai Clock generation and distribution for the 130-nm Itanium® 2 processor with 6-MB on-die L3 cache. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
24Dong-yuan Chen, Lixia Liu, Roy Dz-Ching Ju, Chen Fu, Shuxin Yang, Chengyong Wu Efficient Modeling of Itanium Architecture during Instruction Scheduling using Extended Finite State Automata. Search on Bibsonomy J. Instr. Level Parallelism The full citation details ... 2004 DBLP  BibTeX  RDF
24Daniel J. Magenheimer, Thomas W. Christian vBlades: Optimized Paravirtualization for the Itanium Processor Family. Search on Bibsonomy Virtual Machine Research and Technology Symposium The full citation details ... 2004 DBLP  BibTeX  RDF
24Wilfredo E. Lugo-Beauchamp, Kennie Cruz, Carmen L. Carvajal-Jiménez, Wilson Rivera Performance of hyperspectral imaging algorithms using itanium architecture. Search on Bibsonomy Circuits, Signals, and Systems The full citation details ... 2004 DBLP  BibTeX  RDF
24Marius Cornea Software implementations of division and square root operations for Intel® Itanium® processors. Search on Bibsonomy WCAE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
24Sebastian Winkel Optimal global instruction scheduling for the Itanium processor architecture. Search on Bibsonomy 2004   RDF
24Stefan Rusu, Jason Stinson, Simon Tam 0001, Justin Leung, Harry Muljono, Brian S. Cherkauer A 1.5-GHz 130-nm Itanium® 2 Processor with 6-MB on-die L3 cache. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
24U. Andersson, P. Ekman, Per Öster Performance and performance counters on the Itanium 2 - A benchmarking case study. Search on Bibsonomy PARCO The full citation details ... 2003 DBLP  BibTeX  RDF
24Marius Cornea, John Harrison 0001, Ping Tak Peter Tang Intel® Itanium® floating-point architecture. Search on Bibsonomy WCAE The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
24Samuel D. Naffziger, Glenn Colón-Bonet, Timothy C. Fischer, Reid J. Riedlinger, Thomas J. Sullivan, Tom Grutkowski The implementation of the Itanium 2 microprocessor. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
24Don Weiss, John J. Wuu, Victor Chin The on-chip 3-MB subarray-based third-level cache on an Itanium microprocessor. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
24Eric S. Fetzer, Mark Gibson, Anthony Klein, Naomi Calick, Chengyu Zhu, Eric Busta, Baker Mohammad A fully bypassed six-issue integer datapath and register file on the Itanium-2 microprocessor. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
24Bruce Greer, John Harrison 0001, Greg Henry, Wei Wayne Li, Ping Tak Peter Tang Scientific computing on the Itanium® processor. Search on Bibsonomy Sci. Program. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
24Chih Jeng Kenneth Tan Performance Evaluation of Matrix Solvers on Compaq Alpha and Intel Itanium Processors. Search on Bibsonomy PDPTA The full citation details ... 2002 DBLP  BibTeX  RDF
24Vladik Kreinovich Itanium's new basic operation of fused multiply-add: theoretical explanation and theoretical challenge. Search on Bibsonomy SIGACT News The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
24Fumio Aono, Masayuki Kimura The AzusA 16-Way Itanium Server. Search on Bibsonomy IEEE Micro The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
24Rory McInerney, Kurt Leeper, Troy Hill, Heming Chan, Bulent Basaran, Lance McQuiddy Methodology for repeater insertion management in the RTL, layout, floorplan and fullchip timing databases of the Itanium microprocessor. Search on Bibsonomy ISPD The full citation details ... 2000 DBLP  DOI  BibTeX  RDF RC delay, routing, timing, estimation, microprocessors, floorplan, repeaters
24Yoshiyuki Yamashita, Masato Tsuru Implementing Fast Packet Filters by Software Pipelining on x86 Processors. Search on Bibsonomy APPT The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
24Karl Fürlinger, Daniel Terpstra, Haihang You, Philip Mucci, Shirley Moore Enabling Data Structure Oriented Performance Analysis with Hardware Performance Counter Support. Search on Bibsonomy Euro-Par Workshops The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
24Dawei Liu, Shan Wang 0001, Biao Qin, Weiwei Gong Characterizing DSS Workloads from the Processor Perspective. Search on Bibsonomy APWeb/WAIM Workshops The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
24Youfeng Wu, Yong-Fong Lee Hardware-Software Collaborative Techniques for Runtime Profiling and Phase Transition Detection. Search on Bibsonomy J. Comput. Sci. Technol. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF runtime profiling, phase transition detection, hardware-software collaboration, dynamic optimizations
24David Bernick, Bill Bruckert, Paul Del Vigna, David García, Robert Jardine, Jim Klecka, Jim Smullen NonStop® Advanced Architecture. Search on Bibsonomy DSN The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
24Xinmin Tian, Rakesh Krishnaiyer, Hideki Saito 0001, Milind Girkar, Wei Li 0015 Impact of Compiler-based Data-Prefetching Techniques on SPEC OMP Application Performance. Search on Bibsonomy IPDPS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
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