Search results for "micro-bump"

Found 13 publication records. Showing 13 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
76	Vassilios Gerousis	Physical design implementation for 3D IC: methodology and tools.	ISPD	2010	DBLP DOI BibTeX RDF	3D IC stack, micro-bump, physical design tools, silicon interposer, methodology, tsv
27	Mitsuhito Ando, Ryusuke Tokumine, Toshinobu Takei, Hiromi Mochiyama	Tactile Scanning for Detecting Micro Bump by Strain-Sensitive Artificial Skin.	IEEE Robotics Autom. Lett.	2021	DBLP DOI BibTeX RDF
27	Makoto Motoyoshi, Kohki Yanagimura, Taikoh Fushimi, Shunta Endo	Stacked Pixel Sensor/Detector Technology using Au Micro-Bump Junction.	3DIC	2019	DBLP DOI BibTeX RDF
27	Lay Wai Kong, Osborne A. Martin	Known void size micro-bump, a novel standard of 3D X-ray computed tomography in-line metrology for accuracy assessment and monitoring.	I2MTC	2018	DBLP DOI BibTeX RDF
27	Erik Jan Marinissen, Ferenc Fodor, Bart De Wachter, Jorg Kiesewetter, Eric Hill, Ken Smith	A fully automatic test system for characterizing large-array fine-pitch micro-bump probe cards.	ITC-Asia	2017	DBLP DOI BibTeX RDF
27	Kuan-Te Wu, Jin-Fu Li 0001, Yun-Chao Yu, Chih-Sheng Hou, Chi-Chun Yang, Ding-Ming Kwai, Yung-Fa Chou, Chih-Yen Lo	Intra-channel Reconfigurable Interface for TSV and Micro Bump Fault Tolerance in 3-D RAMs.	ATS	2014	DBLP DOI BibTeX RDF
27	Jin-Tai Yan, Yu-Jen Tseng, Chia-Heng Yen	Efficient micro-bump assignment for RDL routing in 3DICs.	ICECS	2014	DBLP DOI BibTeX RDF
27	Ta-Yu Kuan, Yi-Chun Chang, Tai-Chen Chen	Micro-bump assignment for 3D ICs using order relation.	ASP-DAC	2012	DBLP DOI BibTeX RDF
27	Cheng-Ta Ko, Zhi-Cheng Hsiao, Y. J. Chang, Peng-Shu Chen, J. H. Huang, Hsin-Chia Fu, Y. J. Huang, C. W. Chiang, W. L. Tsat, Y. H. Chen, Wei-Chung Lo, Kuan-Neng Chen	Wafer-level 3D integration with Cu TSV and micro-bump/adhesive hybrid bonding technologies.	3DIC	2011	DBLP DOI BibTeX RDF
27	Myeong-Hyeok Jeong, Jae-Won Kim, Byung-Hyun Kwak, Young-Bae Park, Byoung-Joon Kim, Young-Chang Joo	Electrical Reliability of Cu/Sn Micro-bump in Wafer Level Packaging for BioMEMS Devices.	BIODEVICES	2011	DBLP BibTeX RDF
27	Ken Smith, Peter Hanaway, Mike Jolley, Reed Gleason, Eric Strid, Tom Daenen, Luc Dupas, Bruno Knuts, Erik Jan Marinissen, Marc Van Dievel	Evaluation of TSV and micro-bump probing for wide I/O testing.	ITC	2011	DBLP DOI BibTeX RDF
27	Nobuaki Miyakawa, Eiri Hashimoto, Takanori Maebashi, Natsuo Nakamura, Yutaka Sacho, Shigeto Nakayama, Shinjiro Toyoda	Stacking technology based on 8-inch wafers using direct connection between TSV and micro-bump.	CICC	2008	DBLP DOI BibTeX RDF
19	Nobuaki Miyakawa	A 3D prototyping chip based on a wafer-level stacking technology.	ASP-DAC	2009	DBLP DOI BibTeX RDF