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Found 19 publication records. Showing 19 according to the selection in the facets
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Authors |
Title |
Venue |
Year |
Link |
Author keywords |
118 | Jeegar Tilak Shah, Marius Evers, Jeff Trull, Alper Halbutogullari |
Circuit optimization for leakage power reduction using multi-threshold voltages for high performance microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2007 International Symposium on Physical Design, ISPD 2007, Austin, Texas, USA, March 18-21, 2007, pp. 67-74, 2007, ACM, 978-1-59593-613-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
multi-VTH, optimization, timing, low-power design, microprocessor, EDA, leakage power, sizing |
43 | Takayasu Sakurai |
Reducing Power Consumption of CMOS VLSI's through VDD and VTH Control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 417-424, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
VDD, VTH, VLSI, Low-power, CMOS |
43 | Sherif A. Tawfik, Volkan Kursun |
Multi-Vth Level Conversion Circuits for Multi-VDD Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1397-1400, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Lih-Yih Chiou, Shien-Chun Luo |
An Energy-Efficient Dual-Edge Triggered Level-Converting Flip-Flop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1157-1160, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Vazgen Melikyan, Tigran Hakhverdyan, Sergey Manukyan, Aram Gevorgyan, Davit Babayan |
Low power OpenRISC processor with power gating, multi-VTH and multi-voltage techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EWDTS ![In: 2016 IEEE East-West Design & Test Symposium, EWDTS 2016, Yerevan, Armenia, October 14-17, 2016, pp. 1-4, 2016, IEEE Computer Society, 978-1-5090-0693-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
23 | Theodor Hillebrand, Ludwig Karsthof, Steffen Paul, Dagmar Peters-Drolshagen |
Reliability-Aware Multi-Vth Domain Digital Design Assessment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2018, Budapest, Hungary, April 25-27, 2018, pp. 1-4, 2018, IEEE, 978-1-5386-5754-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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23 | Hao Luo, Mehrdad Heydarzadeh, Mehrdad Nourani |
Aging-Leakage Tradeoffs Using Multi-Vth Cell Library. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 25th IEEE Asian Test Symposium, ATS 2016, Hiroshima, Japan, November 21-24, 2016, pp. 298-303, 2016, IEEE Computer Society, 978-1-5090-3809-1. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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23 | Pavan Kumar Bikki, P. Karuppanan |
Low power and high performance multi-Vth dual mode logic design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIIS ![In: 11th International Conference on Industrial and Information Systems, ICIIS 2016, Roorkee, India, December 3-4, 2016, pp. 463-468, 2016, IEEE, 978-1-5090-3818-3. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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23 | Chua-Chin Wang, Chia-Lung Hsieh |
Disturb-free 5T loadless SRAM cell design with multi-vth transistors using 28 nm CMOS process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: International SoC Design Conference, ISOCC 2016, Jeju, South Korea, October 23-26, 2016, pp. 103-104, 2016, IEEE, 978-1-5090-3219-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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23 | Bo Wang 0020, Jun Zhou 0017, Tony Tae-Hyoung Kim |
SRAM devices and circuits optimization toward energy efficiency in multi-Vth CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 46(3), pp. 265-272, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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23 | Vazgen Melikyan, Eduard Babayan, Anush Melikyan, Davit Babayan, Poghos Petrosyan, Edvard Mkrtchyan |
Clock gating and multi-VTH low power design methods based on 32/28 nm ORCA processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EWDTS ![In: 2015 IEEE East-West Design & Test Symposium, EWDTS 2015, Batumi, Georgia, September 26-29, 2015, pp. 1-4, 2015, IEEE Computer Society, 978-1-4673-7776-8. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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23 | Ramesh Nair, Ranga Vemuri |
MITH-Dyn: A multi Vth dynamic logic design style using mixed mode FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 27th IEEE International System-on-Chip Conference, SOCC 2014, Las Vegas, NV, USA, September 2-5, 2014, pp. 140-145, 2014, IEEE, 978-1-4799-3378-5. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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23 | Yibo Chen, Yu Wang 0002, Yuan Xie 0001, Andrés Takach |
Parametric Yield-Driven Resource Binding in High-Level Synthesis with Multi-Vth/Vdd Library and Device Sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electr. Comput. Eng. ![In: J. Electr. Comput. Eng. 2012, pp. 105250:1-105250:14, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
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23 | Yibo Chen, Yuan Xie 0001, Yu Wang 0002, Andrés Takach |
Parametric yield driven resource binding in behavioral synthesis with multi-Vth/Vdd library. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 15th Asia South Pacific Design Automation Conference, ASP-DAC 2010, Taipei, Taiwan, January 18-21, 2010, pp. 781-786, 2010, IEEE, 978-1-60558-837-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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23 | Yibo Chen, Yuan Xie 0001, Yu Wang 0002, Andrés Takach |
Minimizing leakage power in aging-bounded high-level synthesis with design time multi-Vth assignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 15th Asia South Pacific Design Automation Conference, ASP-DAC 2010, Taipei, Taiwan, January 18-21, 2010, pp. 689-694, 2010, IEEE, 978-1-60558-837-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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23 | Abdoul Rjoub, Hassan Almanasrah |
Low leakage multi-Vth technique for sequential circuits at transistor level in nanotechnology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 17th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010, Athens, Greece, 12-15 December, 2010, pp. 974-977, 2010, IEEE, 978-1-4244-8155-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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23 | Sherif A. Tawfik, Volkan Kursun |
Multi-Vth FinFET sequential circuits with independent-gate bias and work-function engineering for reduced power consumption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2008, Macao, China, November 30 2008 - December 3, 2008, pp. 348-351, 2008, IEEE, 978-1-4244-2342-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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23 | Tsuneaki Fuse, Masako Ohta, Motoki Tokumasu, Hiroshige Fujii, Shigeru Kawanaka, Atsushi Kameyama |
A 0.5-V power-supply scheme for low-power system LSIs using multi-Vth SOI CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 38(2), pp. 303-311, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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15 | Andrea Calimera, Enrico Macii, Massimo Poncino, R. Iris Bahar |
Temperature-insensitive synthesis using multi-vt libraries. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 5-10, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
multi-threshold voltage, temperature-aware, logic synthesis |
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