Search results for "multicycle"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
127	Salvatore Cavalieri, Salvatore Monforte, Angelo Corsaro, Giovanni Scapellato	Multicycle Polling Scheduling Algorithms for FieldBus Networks.	Real Time Syst.	2003	DBLP DOI BibTeX RDF	FieldBus communication networks, hard real-time scheduling, priority scheduling algorithm, earliest deadline first algorithm, rate monotonic algorithm
76	Miroslav N. Velev	Automatic Formal Verification of Liveness for Pipelined Processors with Multicycle Functional Units.	CHARME	2005	DBLP DOI BibTeX RDF
59	Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang	Architecture and synthesis for on-chip multicycle communication.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
58	Irith Pomeranz	On Transition Fault Diagnosis Using Multicycle At-Speed Broadside Tests.	ETS	2011	DBLP DOI BibTeX RDF	Broadside tests, multicycle tests, fault diagnosis, transition faults
42	Yu-Ju Hong, Ya-Shih Huang, Juinn-Dar Huang	Simultaneous data transfer routing and scheduling for interconnect minimization in multicycle communication architecture.	ASP-DAC	2009	DBLP DOI BibTeX RDF
42	Chia-I Chen, Juinn-Dar Huang	CriAS: a performance-driven criticality-aware synthesis flow for on-chip multicycle communication architecture.	ASP-DAC	2009	DBLP DOI BibTeX RDF
42	Wei-Sheng Huang, Yu-Ru Hong, Juinn-Dar Huang, Ya-Shih Huang	A multicycle communication architecture and synthesis flow for Global interconnect Resource Sharing.	ASP-DAC	2008	DBLP DOI BibTeX RDF
42	Vlado Vorisek, Bruce Swanson, Kun-Han Tsai, Dhiraj Goswami	Improved Handling of False and Multicycle Paths in ATPG.	VTS	2006	DBLP DOI BibTeX RDF
42	Prabhat Mishra 0001, Nikil D. Dutt, Alexandru Nicolau, Hiroyuki Tomiyama	Automatic Verification of In-Order Execution In Microprocessors with Fragmented Pipelines and Multicycle Functional Units.	DATE	2002	DBLP DOI BibTeX RDF
42	Miroslav N. Velev, Randal E. Bryant	Formal verification of superscale microprocessors with multicycle functional units, exception, and branch prediction.	DAC	2000	DBLP DOI BibTeX RDF
42	Vladimir B. Dmitriev-Zdorov	Multicycle generalization. A new way to improve the convergence of waveform relaxation for circuit simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
42	Pranav Ashar, Sujit Dey, Sharad Malik	Exploiting multicycle false paths in the performance optimization of sequential logic circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
34	Jianjun Chen, Zoltan Safar, John Aasted Sørensen	Multimodal Wireless Networks: Communication and Surveillance on the Same Infrastructure.	IEEE Trans. Inf. Forensics Secur.	2007	DBLP DOI BibTeX RDF
34	Cheng-Tsung Hwang, Jiahn-Humg Lee, Yu-Chin Hsu	A formal approach to the scheduling problem in high level synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
33	Mike Hutton, David Karchmer, Bryan Archell, Jason Govig	Efficient static timing analysis and applications using edge masks.	FPGA	2005	DBLP DOI BibTeX RDF	cut-path, multicycle, thru-x, FPGA, placement, timing analysis
25	Tong Gao, Hao Chen 0014	Multicycle disassembly-based decomposition algorithm to train multiclass support vector machines.	Pattern Recognit.	2023	DBLP DOI BibTeX RDF
25	Irith Pomeranz	Functionally Possible Scan-Based Test Set as a Dual of a Compressed Multicycle Test Set.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
25	Cristina G. Fernandes, Carla Negri Lintzmayer, Phablo F. S. Moura	Approximations for the Steiner Multicycle Problem.	CoRR	2023	DBLP DOI BibTeX RDF
25	Ahmed M. Hamed, M. Watheq El-Kharashi, Ashraf Salem, Mona Safar	A Multicycle Pipelined GCM-Based AUTOSAR Communication ASIP.	IEEE Access	2022	DBLP DOI BibTeX RDF
25	Irith Pomeranz	Multicycle Tests With Fault Detection Test Data for Improved Logic Diagnosis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2022	DBLP DOI BibTeX RDF
25	Irith Pomeranz	Storage-Based Logic Built-in Self-Test With Multicycle Tests.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2022	DBLP DOI BibTeX RDF
25	Yadi Zhong, Ujjwal Guin	Fault-Injection Based Chosen-Plaintext Attacks on Multicycle AES Implementations.	ACM Great Lakes Symposium on VLSI	2022	DBLP DOI BibTeX RDF
25	Cristina G. Fernandes, Carla Negri Lintzmayer, Phablo F. S. Moura	Approximations for the Steiner Multicycle Problem.	LATIN	2022	DBLP DOI BibTeX RDF
25	James W. Evans, Bernard Kim, Seiya Ono, Ana C. Arias, Paul K. Wright	Multicycle Testing of Commercial Coin Cells for Buffering of Harvested Energy for the IoT.	IEEE Internet Things J.	2021	DBLP DOI BibTeX RDF
25	Irith Pomeranz	Test Compaction by Backward and Forward Extension of Multicycle Tests.	IEEE Trans. Very Large Scale Integr. Syst.	2021	DBLP DOI BibTeX RDF
25	Irith Pomeranz	Partitioning Functional Test Sequences Into Multicycle Functional Broadside Tests.	IEEE Trans. Very Large Scale Integr. Syst.	2021	DBLP DOI BibTeX RDF
25	Zhiliang Wei, Ning Fu, Liyan Qiao	A multicycle sub-Nyquist sampling system for pulse streams with Doppler shift.	Signal Process.	2020	DBLP DOI BibTeX RDF
25	Irith Pomeranz	Selection of Primary Output Vectors to Observe Under Multicycle Tests.	IEEE Trans. Very Large Scale Integr. Syst.	2020	DBLP DOI BibTeX RDF
25	Irith Pomeranz	Multicycle Broadside and Skewed-Load Tests for Test Compaction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2020	DBLP DOI BibTeX RDF
25	Irith Pomeranz	Target Faults for Test Compaction Based on Multicycle Tests.	ACM Trans. Design Autom. Electr. Syst.	2020	DBLP DOI BibTeX RDF
25	Irith Pomeranz	Padding of Multicycle Broadside and Skewed-Load Tests.	IEEE Trans. Very Large Scale Integr. Syst.	2019	DBLP DOI BibTeX RDF
25	Irith Pomeranz	Extracting a Close-to-Minimum Multicycle Functional Broadside Test Set From a Functional Test Sequence.	IEEE Trans. Very Large Scale Integr. Syst.	2019	DBLP DOI BibTeX RDF
25	Cheol-Won Jo, Kwang-Yeob Lee	Design of multicycle path accelerator for neural network.	ISOCC	2019	DBLP DOI BibTeX RDF
25	Irith Pomeranz	Observation Points on State Variables for the Compaction of Multicycle Tests.	IEEE Trans. Very Large Scale Integr. Syst.	2018	DBLP DOI BibTeX RDF
25	Irith Pomeranz	Static test compaction procedure for large pools of multicycle functional broadside tests.	IET Comput. Digit. Tech.	2018	DBLP DOI BibTeX RDF
25	Irith Pomeranz	On-chip generation of primary input sequences for multicycle functional broadside tests.	IET Comput. Digit. Tech.	2018	DBLP DOI BibTeX RDF
25	Irith Pomeranz	Autonomous Multicycle Tests With Low Storage and Test Application Time Overheads.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2018	DBLP DOI BibTeX RDF
25	Guoqing Fu, Sameer R. Sonkusale	A CMOS Luminescence Intensity and Lifetime Dual Sensor Based on Multicycle Charge Modulation.	IEEE Trans. Biomed. Circuits Syst.	2018	DBLP DOI BibTeX RDF
25	Irith Pomeranz	Covering undetected transition fault sites with optimistic unspecified transition faults under multicycle tests.	ETS	2018	DBLP DOI BibTeX RDF
25	Irith Pomeranz	LFSR-Based Generation of Multicycle Tests.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2017	DBLP DOI BibTeX RDF
25	Guoqing Fu, Sameer Sonkusale	CMOS sensor for dual fluorescence intensity and lifetime sensing using multicycle charge modulation.	CICC	2017	DBLP DOI BibTeX RDF
25	Yang Liu 0140, Bin Li 0007, Mo Huang, Zhaoquan Chen	Backscattering in multicycle Q-modulation for bio-implants wireless power transfer.	ASICON	2017	DBLP DOI BibTeX RDF
25	Byunghun Lee, Pyungwoo Yeon, Maysam Ghovanloo	A Multicycle Q-Modulation for Dynamic Optimization of Inductive Links.	IEEE Trans. Ind. Electron.	2016	DBLP DOI BibTeX RDF
25	Haiyong Zheng, Lin Chang, Tengda Wei, Xinxin Qiu, Ping Lin, Yangfan Wang	Registering Retinal Vessel Images from Local to Global via Multiscale and Multicycle Features.	CVPR Workshops	2016	DBLP DOI BibTeX RDF
25	Irith Pomeranz	A Multicycle Test Set Based on a Two-Cycle Test Set With Constant Primary Input Vectors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2015	DBLP DOI BibTeX RDF
25	Irith Pomeranz	Enhanced Test Compaction for Multicycle Broadside Tests by Using State Complementation.	ACM Trans. Design Autom. Electr. Syst.	2015	DBLP DOI BibTeX RDF
25	Hector Sarnago, Oscar Lucía, Arturo Mediano, José M. Burdio	A Class-E Direct AC-AC Converter With Multicycle Modulation for Induction Heating Systems.	IEEE Trans. Ind. Electron.	2014	DBLP DOI BibTeX RDF
25	Florian Rohart, Magali San Cristobal, Béatrice Laurent	Selection of fixed effects in high dimensional linear mixed models using a multicycle ECM algorithm.	Comput. Stat. Data Anal.	2014	DBLP DOI BibTeX RDF
25	Jun Wang 0048, Jiwei Huang, Minghui Fan, Hongjun Wang	Nonparametric Multicycle Spectrum Sensing Method by Segmented Data Processing for Cognitive Radio.	Circuits Syst. Signal Process.	2014	DBLP DOI BibTeX RDF
25	Hongbin Zheng, Swathi T. Gurumani, Liwei Yang, Deming Chen, Kyle Rupnow	High-Level Synthesis With Behavioral-Level Multicycle Path Analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2014	DBLP DOI BibTeX RDF
25	Honghua Xu, Ke Liu 0003, Xin-Ping Guan	Time Slots Allocating and Multicycle Scheduling in IWSN for Narrow Process Automation.	Int. J. Distributed Sens. Networks	2014	DBLP DOI BibTeX RDF
25	John M. Batikian, Michael Liebling	Multicycle non-local means denoising of cardiac image sequences.	ISBI	2014	DBLP DOI BibTeX RDF
25	Daniel Belega, Dario Petri	Accuracy Analysis of the Multicycle Synchrophasor Estimator Provided by the Interpolated DFT Algorithm.	IEEE Trans. Instrum. Meas.	2013	DBLP DOI BibTeX RDF
25	Irith Pomeranz	Built-in generation of multicycle functional broadside tests with observation points.	ACM Trans. Design Autom. Electr. Syst.	2013	DBLP DOI BibTeX RDF
25	Kun-Han Tsai, Xijiang Lin	Multicycle-aware At-speed Test Methodology.	Asian Test Symposium	2013	DBLP DOI BibTeX RDF
25	Irith Pomeranz	On the Switching Activity and Static Test Compaction of Multicycle Scan-Based Tests.	IEEE Trans. Computers	2012	DBLP DOI BibTeX RDF
25	Irith Pomeranz	Multicycle Tests With Constant Primary Input Vectors for Increased Fault Coverage.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2012	DBLP DOI BibTeX RDF
25	Chia-I Chen, Juinn-Dar Huang	A Hierarchical Criticality-Aware Architectural Synthesis Framework for Multicycle Communication.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2010	DBLP DOI BibTeX RDF
25	Ya-Shih Huang, Yu-Ju Hong, Juinn-Dar Huang	Communication Synthesis for Interconnect Minimization in Multicycle Communication Architecture.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2009	DBLP DOI BibTeX RDF
25	Takayuki Ubukata, Shinya Kotosaka, Hideyuki Ohtaki	Trajectory Generation for Adaptive Motion by Phase Feedback - Synchronization of Multicycle Human Movement -.	J. Robotics Mechatronics	2009	DBLP DOI BibTeX RDF
25	Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De	SSMCB: Low-Power Variation-Tolerant Source-Synchronous Multicycle Bus.	IEEE Trans. Circuits Syst. I Regul. Pap.	2009	DBLP DOI BibTeX RDF
25	Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De	Variation-Tolerant and Low-Power Source-Synchronous Multicycle On-Chip Interconnect Scheme.	VLSI Design	2007	DBLP DOI BibTeX RDF
25	Peter Caputa, Christer Svensson	An on-chip delay- and skew-insensitive multicycle communication scheme.	ISSCC	2006	DBLP DOI BibTeX RDF
25	Anupama Kalyan, Srividya Gopalan, Sridhar Varadarajan	A Multicycle Context Model using Oracles and Microsituations for Contact Centers.	IMSA	2005	DBLP BibTeX RDF
25	Haijiang Ou, K. K. Chin	Theory of gated multicycle integration (GMCI) for repetitive imaging of focal plane array.	IEEE Trans. Circuits Syst. II Express Briefs	2003	DBLP DOI BibTeX RDF
25	Gilad Shechter, Galit Naveh, Ami Altman, Roland M. Proksa, Michael Grass 0001	Cardiac image reconstruction on a 16-slice CT scanner using a retrospectively ECG-gated multicycle 3D back-projection algorithm.	Medical Imaging: Image Processing	2003	DBLP DOI BibTeX RDF
25	Alberto Ferreira de Souza, Peter Rounce	Effect of Multicycle Intructions on the Integer Performance of the Dynamixcally Trace Scheduled VLIW Architecture.	HPCN	1999	DBLP DOI BibTeX RDF
25	Vladimir B. Dmitriev-Zdorov	Multicycle generalization of relaxation-based algorithms for circuit and system simulation.		1997	RDF
17	Ajay Kumar Verma, Philip Brisk, Paolo Ienne	Fast, quasi-optimal, and pipelined instruction-set extensions.	ASP-DAC	2008	DBLP DOI BibTeX RDF
17	Qiaoyan Yu, Paul Ampadu	Adaptive error control for reliable systems-on-chip.	ISCAS	2008	DBLP DOI BibTeX RDF
17	Ahmad Zmily, Christos Kozyrakis	Block-aware instruction set architecture.	ACM Trans. Archit. Code Optim.	2006	DBLP DOI BibTeX RDF	basic block, software hints, branch prediction, Instruction set architecture, instruction fetch, decoupled architecture
17	Vidyasagar Nookala, David J. Lilja, Sachin S. Sapatnekar	Temperature-aware floorplanning of microarchitecture blocks with IPC-power dependence modeling and transient analysis.	ISLPED	2006	DBLP DOI BibTeX RDF	floorplanning, microarchitecture, transient analysis
17	Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi	Instruction-level test methodology for CPU core self-testing.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	CPU core testing, Instruction level testing, test instruction set, BIST, pipelined processor, software-based self testing
17	Katherine Barabash, Ori Ben-Yitzhak, Irit Goft, Elliot K. Kolodner, Victor Leikehman, Yoav Ossia, Avi Owshanko, Erez Petrank	A parallel, incremental, mostly concurrent garbage collector for servers.	ACM Trans. Program. Lang. Syst.	2005	DBLP DOI BibTeX RDF	Garbage collection, JVM, concurrent garbage collection
17	Manan Syal, Michael S. Hsiao, Suriyaprakash Natarajan, Sreejit Chakravarty	Untestable Multi-Cycle Path Delay Faults in Industrial Designs.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
17	John A. Nestor	Teaching Computer Organization with HDLs: An Incremental Approach.	MSE	2005	DBLP DOI BibTeX RDF
17	Vidyasagar Nookala, Ying Chen, David J. Lilja, Sachin S. Sapatnekar	Microarchitecture-aware floorplanning using a statistical design of experiments approach.	DAC	2005	DBLP DOI BibTeX RDF	floorplanning, microarchitecture, wire pipelining
17	Peter G. Sassone, D. Scott Wills	Dynamic Strands: Collapsing Speculative Dependence Chains for Reducing Pipeline Communication.	MICRO	2004	DBLP DOI BibTeX RDF
17	Mikko H. Lipasti, Brian R. Mestan, Erika Gunadi	Physical Register Inlining.	ISCA	2004	DBLP DOI BibTeX RDF
17	Stephen Pateras	Achieving At-Speed Structural Test.	IEEE Des. Test Comput.	2003	DBLP DOI BibTeX RDF
17	Shi-Zheng Eric Lin, Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai	Optimal time borrowing analysis and timing budgeting optimization for latch-based designs.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	latch-based design, time borrowing, timing budgeting, static timing analysis, Cycle stealing
17	Ilhyun Kim, Mikko H. Lipasti	Implementing Optimizations at Decode Time.	ISCA	2002	DBLP DOI BibTeX RDF	speculative scheduling, speculative decode, silent store, reference combining, confidence prediction, runtime optimizations
17	Mauro Olivieri	Design of synchronous and asynchronous variable-latency pipelined multipliers.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
17	Kenneth M. Wilson, Kunle Olukotun	High Bandwidth On-Chip Cache Design.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Dynamic superscalar, banked cache, dual-ported cache, SPEC95, memory bandwidth
17	Krzysztof Kuchcinski, Christophe Wolinski	Synthesis of Conditional Behaviors Using Hierarchical Conditional Dependency Graphs and Constraint Logic Programming.	DSD	2001	DBLP DOI BibTeX RDF
17	Miroslav N. Velev	Automatic Abstraction of Memories in the Formal Verification of Superscalar Microprocessors.	TACAS	2001	DBLP DOI BibTeX RDF
17	Mehrdad Nourani, Christos A. Papachristou	Stability-based algorithms for high-level synthesis of digital ASICs.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
17	M. Balakrishnan, Heman Khanna	Allocation of FIFO structures in RTL data paths.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	synthesis, RTL, ILP, FIFO, data path
17	Christopher A. Healy, Robert D. Arnold, Frank Mueller 0001, David B. Whalley, Marion G. Harmon	Bounding Pipeline and Instruction Cache Performance.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	best case execution time, Real-time systems, pipelining, timing analysis, worst case execution time, instruction cache
17	François Pêcheux, Yannick Hervé	DIPS for MIPS: An Instrumented VHDL/Corba Kernel for Distributed Learning in EECS.	MSE	1999	DBLP DOI BibTeX RDF
17	Giri Tiruvuri, Moon Chung	Estimation of lower bounds in scheduling algorithms for high-level synthesis.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	lower-bound estimated, scheduling, dynamic programming, high-level synthesis
17	Samit Chaudhuri, S. A. Blthye, Robert A. Walker 0001	A solution methodology for exact design space exploration in a three-dimensional design space.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
17	Babette van Antwerpen-de Fluiter, Emile H. L. Aarts, Jan H. M. Korst, Wim F. J. Verhaegh, Albert van der Werf	The complexity of generalized retiming problems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
17	Muhammad K. Dhodhi, Frank H. Hielscher, Robert H. Storer, Jayaram Bhasker	Datapath synthesis using a problem-space genetic algorithm.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
17	Tsing-Fa Lee, Allen C.-H. Wu, Youn-Long Lin, Daniel D. Gajski	A transformation-based method for loop folding.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
17	Prasad Raja, Guevara Noubir	Static and Dynamic Polling Mechanisms for Fieldbus Networks.	ACM SIGOPS Oper. Syst. Rev.	1993	DBLP DOI BibTeX RDF
17	Roni Potasman, Joseph Lis, Alexandru Nicolau, Daniel Gajski	Percolation Based Synthesis.	DAC	1990	DBLP DOI BibTeX RDF
17	Pierre G. Paulin, John P. Knight	Force-directed scheduling for the behavioral synthesis of ASICs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF