Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
127 | Salvatore Cavalieri, Salvatore Monforte, Angelo Corsaro, Giovanni Scapellato |
Multicycle Polling Scheduling Algorithms for FieldBus Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Real Time Syst. ![In: Real Time Syst. 25(2-3), pp. 157-185, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
FieldBus communication networks, hard real-time scheduling, priority scheduling algorithm, earliest deadline first algorithm, rate monotonic algorithm |
76 | Miroslav N. Velev |
Automatic Formal Verification of Liveness for Pipelined Processors with Multicycle Functional Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHARME ![In: Correct Hardware Design and Verification Methods, 13th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005, Proceedings, pp. 97-113, 2005, Springer, 3-540-29105-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
59 | Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang |
Architecture and synthesis for on-chip multicycle communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(4), pp. 550-564, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
58 | Irith Pomeranz |
On Transition Fault Diagnosis Using Multicycle At-Speed Broadside Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 16th European Test Symposium, ETS 2011, Trondheim, Norway, May 23-27, 2011, pp. 189-194, 2011, IEEE Computer Society, 978-0-7695-4433-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
Broadside tests, multicycle tests, fault diagnosis, transition faults |
42 | Yu-Ju Hong, Ya-Shih Huang, Juinn-Dar Huang |
Simultaneous data transfer routing and scheduling for interconnect minimization in multicycle communication architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 19-24, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
42 | Chia-I Chen, Juinn-Dar Huang |
CriAS: a performance-driven criticality-aware synthesis flow for on-chip multicycle communication architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 67-72, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
42 | Wei-Sheng Huang, Yu-Ru Hong, Juinn-Dar Huang, Ya-Shih Huang |
A multicycle communication architecture and synthesis flow for Global interconnect Resource Sharing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 16-21, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
42 | Vlado Vorisek, Bruce Swanson, Kun-Han Tsai, Dhiraj Goswami |
Improved Handling of False and Multicycle Paths in ATPG. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 24th IEEE VLSI Test Symposium (VTS 2006), 30 April - 4 May 2006, Berkeley, California, USA, pp. 160-165, 2006, IEEE Computer Society, 0-7695-2514-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
42 | Prabhat Mishra 0001, Nikil D. Dutt, Alexandru Nicolau, Hiroyuki Tomiyama |
Automatic Verification of In-Order Execution In Microprocessors with Fragmented Pipelines and Multicycle Functional Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 36-43, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
42 | Miroslav N. Velev, Randal E. Bryant |
Formal verification of superscale microprocessors with multicycle functional units, exception, and branch prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 112-117, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
42 | Vladimir B. Dmitriev-Zdorov |
Multicycle generalization. A new way to improve the convergence of waveform relaxation for circuit simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(5), pp. 435-443, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
42 | Pranav Ashar, Sujit Dey, Sharad Malik |
Exploiting multicycle false paths in the performance optimization of sequential logic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(9), pp. 1067-1075, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
34 | Jianjun Chen, Zoltan Safar, John Aasted Sørensen |
Multimodal Wireless Networks: Communication and Surveillance on the Same Infrastructure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Inf. Forensics Secur. ![In: IEEE Trans. Inf. Forensics Secur. 2(3-1), pp. 468-484, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
34 | Cheng-Tsung Hwang, Jiahn-Humg Lee, Yu-Chin Hsu |
A formal approach to the scheduling problem in high level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(4), pp. 464-475, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
33 | Mike Hutton, David Karchmer, Bryan Archell, Jason Govig |
Efficient static timing analysis and applications using edge masks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005, pp. 174-183, 2005, ACM, 1-59593-029-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
cut-path, multicycle, thru-x, FPGA, placement, timing analysis |
25 | Tong Gao, Hao Chen 0014 |
Multicycle disassembly-based decomposition algorithm to train multiclass support vector machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Pattern Recognit. ![In: Pattern Recognit. 140, pp. 109479, August 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
25 | Irith Pomeranz |
Functionally Possible Scan-Based Test Set as a Dual of a Compressed Multicycle Test Set. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(4), pp. 1336-1345, April 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
25 | Cristina G. Fernandes, Carla Negri Lintzmayer, Phablo F. S. Moura |
Approximations for the Steiner Multicycle Problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2308.07471, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
25 | Ahmed M. Hamed, M. Watheq El-Kharashi, Ashraf Salem, Mona Safar |
A Multicycle Pipelined GCM-Based AUTOSAR Communication ASIP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 10, pp. 46312-46329, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
25 | Irith Pomeranz |
Multicycle Tests With Fault Detection Test Data for Improved Logic Diagnosis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(5), pp. 1587-1591, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
25 | Irith Pomeranz |
Storage-Based Logic Built-in Self-Test With Multicycle Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(10), pp. 3553-3557, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
25 | Yadi Zhong, Ujjwal Guin |
Fault-Injection Based Chosen-Plaintext Attacks on Multicycle AES Implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6 - 8, 2022, pp. 443-448, 2022, ACM, 978-1-4503-9322-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
25 | Cristina G. Fernandes, Carla Negri Lintzmayer, Phablo F. S. Moura |
Approximations for the Steiner Multicycle Problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATIN ![In: LATIN 2022: Theoretical Informatics - 15th Latin American Symposium, Guanajuato, Mexico, November 7-11, 2022, Proceedings, pp. 188-203, 2022, Springer, 978-3-031-20623-8. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
25 | James W. Evans, Bernard Kim, Seiya Ono, Ana C. Arias, Paul K. Wright |
Multicycle Testing of Commercial Coin Cells for Buffering of Harvested Energy for the IoT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Internet Things J. ![In: IEEE Internet Things J. 8(12), pp. 10047-10051, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
25 | Irith Pomeranz |
Test Compaction by Backward and Forward Extension of Multicycle Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 29(1), pp. 242-246, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
25 | Irith Pomeranz |
Partitioning Functional Test Sequences Into Multicycle Functional Broadside Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 29(1), pp. 89-99, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
25 | Zhiliang Wei, Ning Fu, Liyan Qiao |
A multicycle sub-Nyquist sampling system for pulse streams with Doppler shift. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Signal Process. ![In: Signal Process. 176, pp. 107705, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
25 | Irith Pomeranz |
Selection of Primary Output Vectors to Observe Under Multicycle Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 28(1), pp. 156-162, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
25 | Irith Pomeranz |
Multicycle Broadside and Skewed-Load Tests for Test Compaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(1), pp. 262-266, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
25 | Irith Pomeranz |
Target Faults for Test Compaction Based on Multicycle Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 25(2), pp. 18:1-18:14, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
25 | Irith Pomeranz |
Padding of Multicycle Broadside and Skewed-Load Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 27(11), pp. 2587-2595, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
25 | Irith Pomeranz |
Extracting a Close-to-Minimum Multicycle Functional Broadside Test Set From a Functional Test Sequence. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 27(6), pp. 1428-1437, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
25 | Cheol-Won Jo, Kwang-Yeob Lee |
Design of multicycle path accelerator for neural network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: 2019 International SoC Design Conference, ISOCC 2019, Jeju, Korea (South), October 6-9, 2019, pp. 221-224, 2019, IEEE, 978-1-7281-2478-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
25 | Irith Pomeranz |
Observation Points on State Variables for the Compaction of Multicycle Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 26(11), pp. 2567-2571, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
25 | Irith Pomeranz |
Static test compaction procedure for large pools of multicycle functional broadside tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Comput. Digit. Tech. ![In: IET Comput. Digit. Tech. 12(5), pp. 233-240, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
25 | Irith Pomeranz |
On-chip generation of primary input sequences for multicycle functional broadside tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Comput. Digit. Tech. ![In: IET Comput. Digit. Tech. 12(3), pp. 80-86, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
25 | Irith Pomeranz |
Autonomous Multicycle Tests With Low Storage and Test Application Time Overheads. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(9), pp. 1881-1892, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
25 | Guoqing Fu, Sameer R. Sonkusale |
A CMOS Luminescence Intensity and Lifetime Dual Sensor Based on Multicycle Charge Modulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Biomed. Circuits Syst. ![In: IEEE Trans. Biomed. Circuits Syst. 12(3), pp. 677-688, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
25 | Irith Pomeranz |
Covering undetected transition fault sites with optimistic unspecified transition faults under multicycle tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 23rd IEEE European Test Symposium, ETS 2018, Bremen, Germany, May 28 - June 1, 2018, pp. 1-2, 2018, IEEE, 978-1-5386-3728-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
25 | Irith Pomeranz |
LFSR-Based Generation of Multicycle Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(3), pp. 503-507, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
25 | Guoqing Fu, Sameer Sonkusale |
CMOS sensor for dual fluorescence intensity and lifetime sensing using multicycle charge modulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: 2017 IEEE Custom Integrated Circuits Conference, CICC 2017, Austin, TX, USA, April 30 - May 3, 2017, pp. 1-4, 2017, IEEE, 978-1-5090-5191-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
25 | Yang Liu 0140, Bin Li 0007, Mo Huang, Zhaoquan Chen |
Backscattering in multicycle Q-modulation for bio-implants wireless power transfer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 12th IEEE International Conference on ASIC, ASICON 2017, Guiyang, China, October 25-28, 2017, pp. 936-939, 2017, IEEE, 978-1-5090-6625-4. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
25 | Byunghun Lee, Pyungwoo Yeon, Maysam Ghovanloo |
A Multicycle Q-Modulation for Dynamic Optimization of Inductive Links. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Ind. Electron. ![In: IEEE Trans. Ind. Electron. 63(8), pp. 5091-5100, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
25 | Haiyong Zheng, Lin Chang, Tengda Wei, Xinxin Qiu, Ping Lin, Yangfan Wang |
Registering Retinal Vessel Images from Local to Global via Multiscale and Multicycle Features. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CVPR Workshops ![In: 2016 IEEE Conference on Computer Vision and Pattern Recognition Workshops, CVPR Workshops 2016, Las Vegas, NV, USA, June 26 - July 1, 2016, pp. 490-497, 2016, IEEE Computer Society, 978-1-5090-1437-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
25 | Irith Pomeranz |
A Multicycle Test Set Based on a Two-Cycle Test Set With Constant Primary Input Vectors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(7), pp. 1124-1132, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
25 | Irith Pomeranz |
Enhanced Test Compaction for Multicycle Broadside Tests by Using State Complementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 21(1), pp. 13:1-13:20, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
25 | Hector Sarnago, Oscar Lucía, Arturo Mediano, José M. Burdio |
A Class-E Direct AC-AC Converter With Multicycle Modulation for Induction Heating Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Ind. Electron. ![In: IEEE Trans. Ind. Electron. 61(5), pp. 2521-2530, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
25 | Florian Rohart, Magali San Cristobal, Béatrice Laurent |
Selection of fixed effects in high dimensional linear mixed models using a multicycle ECM algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Stat. Data Anal. ![In: Comput. Stat. Data Anal. 80, pp. 209-222, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
25 | Jun Wang 0048, Jiwei Huang, Minghui Fan, Hongjun Wang |
Nonparametric Multicycle Spectrum Sensing Method by Segmented Data Processing for Cognitive Radio. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 33(1), pp. 299-307, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
25 | Hongbin Zheng, Swathi T. Gurumani, Liwei Yang, Deming Chen, Kyle Rupnow |
High-Level Synthesis With Behavioral-Level Multicycle Path Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12), pp. 1832-1845, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
25 | Honghua Xu, Ke Liu 0003, Xin-Ping Guan |
Time Slots Allocating and Multicycle Scheduling in IWSN for Narrow Process Automation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Distributed Sens. Networks ![In: Int. J. Distributed Sens. Networks 10, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
25 | John M. Batikian, Michael Liebling |
Multicycle non-local means denoising of cardiac image sequences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISBI ![In: IEEE 11th International Symposium on Biomedical Imaging, ISBI 2014, April 29 - May 2, 2014, Beijing, Chin, Beijing, China, pp. 1071-1074, 2014, IEEE, 978-1-4673-1961-4. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
25 | Daniel Belega, Dario Petri |
Accuracy Analysis of the Multicycle Synchrophasor Estimator Provided by the Interpolated DFT Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Instrum. Meas. ![In: IEEE Trans. Instrum. Meas. 62(5), pp. 942-953, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
25 | Irith Pomeranz |
Built-in generation of multicycle functional broadside tests with observation points. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 19(1), pp. 8:1-8:17, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
25 | Kun-Han Tsai, Xijiang Lin |
Multicycle-aware At-speed Test Methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 22nd Asian Test Symposium, ATS 2013, Yilan County, Taiwan, November 18-21, 2013, pp. 49, 2013, IEEE Computer Society, 978-0-7695-5080-0. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
25 | Irith Pomeranz |
On the Switching Activity and Static Test Compaction of Multicycle Scan-Based Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 61(8), pp. 1179-1188, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
25 | Irith Pomeranz |
Multicycle Tests With Constant Primary Input Vectors for Increased Fault Coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(9), pp. 1428-1438, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
25 | Chia-I Chen, Juinn-Dar Huang |
A Hierarchical Criticality-Aware Architectural Synthesis Framework for Multicycle Communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(7), pp. 1300-1308, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
25 | Ya-Shih Huang, Yu-Ju Hong, Juinn-Dar Huang |
Communication Synthesis for Interconnect Minimization in Multicycle Communication Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12), pp. 3143-3150, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
25 | Takayuki Ubukata, Shinya Kotosaka, Hideyuki Ohtaki |
Trajectory Generation for Adaptive Motion by Phase Feedback - Synchronization of Multicycle Human Movement -. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Robotics Mechatronics ![In: J. Robotics Mechatronics 21(3), pp. 342-352, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
25 | Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De |
SSMCB: Low-Power Variation-Tolerant Source-Synchronous Multicycle Bus. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(2), pp. 384-394, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
25 | Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De |
Variation-Tolerant and Low-Power Source-Synchronous Multicycle On-Chip Interconnect Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2007, pp. 95402:1-95402:12, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Peter Caputa, Christer Svensson |
An on-chip delay- and skew-insensitive multicycle communication scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2006 IEEE International Solid State Circuits Conference, ISSCC 2006, Digest of Technical Papers, an Francisco, CA, USA, February 6-9, 2006, pp. 1765-1774, 2006, IEEE, 1-4244-0079-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Anupama Kalyan, Srividya Gopalan, Sridhar Varadarajan |
A Multicycle Context Model using Oracles and Microsituations for Contact Centers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IMSA ![In: Proceedings of the Ninth IASTED International Conference on Internet and Multimedia Systems and Applications (IMSA 2005), Honolulu, Hawaii, USA, August 15-17, 2005, pp. 191-196, 2005, IASTED/ACTA Press, 0-88986-510-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP BibTeX RDF |
|
25 | Haijiang Ou, K. K. Chin |
Theory of gated multicycle integration (GMCI) for repetitive imaging of focal plane array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 50(7), pp. 378-383, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
25 | Gilad Shechter, Galit Naveh, Ami Altman, Roland M. Proksa, Michael Grass 0001 |
Cardiac image reconstruction on a 16-slice CT scanner using a retrospectively ECG-gated multicycle 3D back-projection algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Medical Imaging: Image Processing ![In: Medical Imaging 2003: Image Processing, San Diego, California, United States, 15-20 February 2003, 2003, SPIE, 9780819448330. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
25 | Alberto Ferreira de Souza, Peter Rounce |
Effect of Multicycle Intructions on the Integer Performance of the Dynamixcally Trace Scheduled VLIW Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCN ![In: High-Performance Computing and Networking, 7th International Conference, HPCN Europe 1999, Amsterdam, The Netherlands, April 12-14, 1999, Proceedings, pp. 1203-1206, 1999, Springer, 3-540-65821-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
25 | Vladimir B. Dmitriev-Zdorov |
Multicycle generalization of relaxation-based algorithms for circuit and system simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1997 |
RDF |
|
17 | Ajay Kumar Verma, Philip Brisk, Paolo Ienne |
Fast, quasi-optimal, and pipelined instruction-set extensions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 334-339, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Qiaoyan Yu, Paul Ampadu |
Adaptive error control for reliable systems-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 832-835, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Ahmad Zmily, Christos Kozyrakis |
Block-aware instruction set architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 3(3), pp. 327-357, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
basic block, software hints, branch prediction, Instruction set architecture, instruction fetch, decoupled architecture |
17 | Vidyasagar Nookala, David J. Lilja, Sachin S. Sapatnekar |
Temperature-aware floorplanning of microarchitecture blocks with IPC-power dependence modeling and transient analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 298-303, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
floorplanning, microarchitecture, transient analysis |
17 | Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi |
Instruction-level test methodology for CPU core self-testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 10(4), pp. 673-689, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
CPU core testing, Instruction level testing, test instruction set, BIST, pipelined processor, software-based self testing |
17 | Katherine Barabash, Ori Ben-Yitzhak, Irit Goft, Elliot K. Kolodner, Victor Leikehman, Yoav Ossia, Avi Owshanko, Erez Petrank |
A parallel, incremental, mostly concurrent garbage collector for servers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 27(6), pp. 1097-1146, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Garbage collection, JVM, concurrent garbage collection |
17 | Manan Syal, Michael S. Hsiao, Suriyaprakash Natarajan, Sreejit Chakravarty |
Untestable Multi-Cycle Path Delay Faults in Industrial Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 194-201, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | John A. Nestor |
Teaching Computer Organization with HDLs: An Incremental Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: 2005 International Conference on Microelectronics Systems Education, MSE 2005, Anaheim, CA, USA, June 12-13, 2005, pp. 77-78, 2005, IEEE Computer Society, 0-7695-2374-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Vidyasagar Nookala, Ying Chen, David J. Lilja, Sachin S. Sapatnekar |
Microarchitecture-aware floorplanning using a statistical design of experiments approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 579-584, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
floorplanning, microarchitecture, wire pipelining |
17 | Peter G. Sassone, D. Scott Wills |
Dynamic Strands: Collapsing Speculative Dependence Chains for Reducing Pipeline Communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 4-8 December 2004, Portland, OR, USA, pp. 7-17, 2004, IEEE Computer Society, 0-7695-2126-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Mikko H. Lipasti, Brian R. Mestan, Erika Gunadi |
Physical Register Inlining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 31st International Symposium on Computer Architecture (ISCA 2004), 19-23 June 2004, Munich, Germany, pp. 325-337, 2004, IEEE Computer Society, 0-7695-2143-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Stephen Pateras |
Achieving At-Speed Structural Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 20(5), pp. 26-33, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Shi-Zheng Eric Lin, Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai |
Optimal time borrowing analysis and timing budgeting optimization for latch-based designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 7(1), pp. 217-230, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
latch-based design, time borrowing, timing budgeting, static timing analysis, Cycle stealing |
17 | Ilhyun Kim, Mikko H. Lipasti |
Implementing Optimizations at Decode Time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 29th International Symposium on Computer Architecture (ISCA 2002), 25-29 May 2002, Anchorage, AK, USA, pp. 221-232, 2002, IEEE Computer Society, 0-7695-1605-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
speculative scheduling, speculative decode, silent store, reference combining, confidence prediction, runtime optimizations |
17 | Mauro Olivieri |
Design of synchronous and asynchronous variable-latency pipelined multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(2), pp. 365-376, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Kenneth M. Wilson, Kunle Olukotun |
High Bandwidth On-Chip Cache Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(4), pp. 292-307, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Dynamic superscalar, banked cache, dual-ported cache, SPEC95, memory bandwidth |
17 | Krzysztof Kuchcinski, Christophe Wolinski |
Synthesis of Conditional Behaviors Using Hierarchical Conditional Dependency Graphs and Constraint Logic Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 4-6 September 2001, Warsaw, Poland, pp. 220-227, 2001, IEEE Computer Society, 0-7695-1239-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Miroslav N. Velev |
Automatic Abstraction of Memories in the Formal Verification of Superscalar Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TACAS ![In: Tools and Algorithms for the Construction and Analysis of Systems, 7th International Conference, TACAS 2001 Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2001 Genova, Italy, April 2-6, 2001, Proceedings, pp. 252-267, 2001, Springer, 3-540-41865-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Mehrdad Nourani, Christos A. Papachristou |
Stability-based algorithms for high-level synthesis of digital ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(4), pp. 431-435, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
17 | M. Balakrishnan, Heman Khanna |
Allocation of FIFO structures in RTL data paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 5(3), pp. 294-310, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
synthesis, RTL, ILP, FIFO, data path |
17 | Christopher A. Healy, Robert D. Arnold, Frank Mueller 0001, David B. Whalley, Marion G. Harmon |
Bounding Pipeline and Instruction Cache Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 48(1), pp. 53-70, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
best case execution time, Real-time systems, pipelining, timing analysis, worst case execution time, instruction cache |
17 | François Pêcheux, Yannick Hervé |
DIPS for MIPS: An Instrumented VHDL/Corba Kernel for Distributed Learning in EECS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: IEEE International Conference on Microelectronic Systems Education, MSE 1999, Arlington, Virginia, USA, July 19-21, 1999, pp. 30-31, 1999, IEEE Computer Society, 0-7695-0312-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
17 | Giri Tiruvuri, Moon Chung |
Estimation of lower bounds in scheduling algorithms for high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 3(2), pp. 162-180, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
lower-bound estimated, scheduling, dynamic programming, high-level synthesis |
17 | Samit Chaudhuri, S. A. Blthye, Robert A. Walker 0001 |
A solution methodology for exact design space exploration in a three-dimensional design space. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 5(1), pp. 69-81, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
17 | Babette van Antwerpen-de Fluiter, Emile H. L. Aarts, Jan H. M. Korst, Wim F. J. Verhaegh, Albert van der Werf |
The complexity of generalized retiming problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(11), pp. 1340-1353, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
17 | Muhammad K. Dhodhi, Frank H. Hielscher, Robert H. Storer, Jayaram Bhasker |
Datapath synthesis using a problem-space genetic algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(8), pp. 934-944, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
17 | Tsing-Fa Lee, Allen C.-H. Wu, Youn-Long Lin, Daniel D. Gajski |
A transformation-based method for loop folding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(4), pp. 439-450, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
17 | Prasad Raja, Guevara Noubir |
Static and Dynamic Polling Mechanisms for Fieldbus Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGOPS Oper. Syst. Rev. ![In: ACM SIGOPS Oper. Syst. Rev. 27(3), pp. 34-45, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
17 | Roni Potasman, Joseph Lis, Alexandru Nicolau, Daniel Gajski |
Percolation Based Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, Florida, USA, June 24-28, 1990., pp. 444-449, 1990, IEEE Computer Society Press, 0-89791-363-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
17 | Pierre G. Paulin, John P. Knight |
Force-directed scheduling for the behavioral synthesis of ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(6), pp. 661-679, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|