Search results for "multiplicand"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
58	Chia-Long Wu, Der-Chyuan Lou, Te-Jen Chang	An efficient Montgomery exponentiation algorithm for public-key cryptosystems.	ISI	2008	DBLP DOI BibTeX RDF
58	Ali Jalali, Hamid Sarbazi-Azad	The Edge Product of Networks.	PDCAT	2007	DBLP DOI BibTeX RDF
53	Chin-Chen Chang 0001, Ying-Tse Kuo, Chu-Hsing Lin	Fast Algorithms for Common-Multiplicand Multiplication and Exponentiation by Performing Complements.	AINA	2003	DBLP DOI BibTeX RDF
38	Marcelo E. Kaihara, Naofumi Takagi	Bipartite Modular Multiplication Method.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Algorithms, Computer arithmetic
38	Mark A. Erle, Michael J. Schulte	Decimal Multiplication Via Carry-Save Addition.	ASAP	2003	DBLP DOI BibTeX RDF
36	Louis P. Rubinfield	A Proof of the Modified Booth's Algorithm for Multiplication.	IEEE Trans. Computers	1975	DBLP DOI BibTeX RDF	Modified Booth's algorithm, multiplicand, multiplier, partial product
34	Jungjoo Seo, Kunsoo Park	Fast batch modular exponentiation with common-multiplicand multiplication.	Inf. Process. Lett.	2018	DBLP DOI BibTeX RDF
34	Da-Zhi Sun, Jin-Peng Huai, Zhen-Fu Cao	A comment on "An efficient common-multiplicand-multiplication method to the Montgomery algorithm for speeding up exponentiation".	Inf. Sci.	2013	DBLP DOI BibTeX RDF
34	Tao Wu, Shuguo Li, Litian Liu	Fast, compact and symmetric modular exponentiation architecture by common-multiplicand Montgomery modular multiplications.	Integr.	2013	DBLP DOI BibTeX RDF
34	Abdalhossein Rezai, Parviz Keshavarzi	High-performance modular exponentiation algorithm by using a new modified modular multiplication algorithm and common-multiplicand-multiplication method.	WorldCIS	2011	DBLP BibTeX RDF
34	Chia-Long Wu	An efficient common-multiplicand-multiplication method to the Montgomery algorithm for speeding up exponentiation.	Inf. Sci.	2009	DBLP DOI BibTeX RDF
34	Chia-Long Wu	Fast exponentiation based on common-multiplicand-multiplication and minimal-signed-digit techniques.	Int. J. Comput. Math.	2007	DBLP DOI BibTeX RDF
34	Sung-Ming Yen, Wei-Chih Lien, Sang-Jae Moon	Inefficiency of common-multiplicand multiplication and exponentiation algorithms by performing binary complements.	Appl. Math. Comput.	2007	DBLP DOI BibTeX RDF
34	Der-Chyuan Lou, Chia-Long Wu	Parallel exponentiation using common-multiplicand-multiplication and signed-digit-folding techniques.	Int. J. Comput. Math.	2004	DBLP DOI BibTeX RDF
34	JaeCheol Ha, Sang-Jae Moon	A Common-Multiplicand Method to the Montgomery Algorithm for Speeding up Exponentiation.	Inf. Process. Lett.	1998	DBLP DOI BibTeX RDF
19	Chia-Long Wu	Fast Parallel Montgomery Binary Exponentiation Algorithm Using Canonical- Signed-Digit Recoding Technique.	ICA3PP	2009	DBLP DOI BibTeX RDF	Montgomery reduction algorithm, cryptography, complexity analysis, number theory, algorithm design
19	Anding Wang, Yier Jin, Shiju Li	Dual-Residue Montgomery Multiplication.	NPC	2007	DBLP DOI BibTeX RDF	Dual residue system, Montgomery algorithm, Parallelism
19	Rui Rodrigues 0004, João M. P. Cardoso, Pedro C. Diniz	A Data-Driven Approach for Pipelining Sequences of Data-Dependent Loops.	FCCM	2007	DBLP DOI BibTeX RDF
19	Ronen Goldberg, Guy Even, Peter-Michael Seidel	An FPGA implementation of pipelined multiplicative division with IEEE Rounding.	FCCM	2007	DBLP DOI BibTeX RDF
19	Sanjiv Kumar Mangal, Raghavendra B. Deshmukh, Rahul M. Badghare, Rajendra M. Patrikar	FPGA Implementation of Low Power Parallel Multiplier.	VLSI Design	2007	DBLP DOI BibTeX RDF
19	Jun-Cheol Jeon, Kee-Won Kim, Jai-Boo Oh, Kee-Young Yoo	Modular Divider for Elliptic Curve Cryptographic Hardware Based on Programmable CA.	International Conference on Computational Science (4)	2006	DBLP DOI BibTeX RDF
19	Jun-Cheol Jeon, Kee-Won Kim, Byung-Heon Kang, Kee-Young Yoo	Cellular Automata Architecture for Elliptic Curve Cryptographic Hardware.	International Conference on Computational Science (3)	2006	DBLP DOI BibTeX RDF
19	Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu, Chia-Jen Sheu	Low Power Multiplier Designs Based on Improved Column Bypassing Schemes.	APCCAS	2006	DBLP DOI BibTeX RDF
19	Peter-Michael Seidel, Lee D. McFearin, David W. Matula	Secondary Radix Recodings for Higher Radix Multipliers.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	recoding, high radix, digit set, mixed radix representation, partial product reduction, Booth recoding, Binary multiplication
19	Jun-Cheol Jeon, Kee-Won Kim, Kee-Young Yoo	Evolutionary Hardware Architecture for Division in Elliptic Curve Cryptosystems over GF(2n).	ICNC (3)	2005	DBLP DOI BibTeX RDF
19	David Guevorkian, Petri Liuha, Aki Launiainen, Ville Lappalainen	A Family of Accelerators for Matrix-Vector Arithmetics Based on High-Radix Multiplier Structures.	SAMOS	2004	DBLP DOI BibTeX RDF
19	Kyo-Min Ku, Kyeoung Ju Ha, Wi Hyun Yoo, Kee-Young Yoo	Parallel Montgomery Multiplication and Squaring over GF(2m) Based on Cellular Automata.	ICCSA (4)	2004	DBLP DOI BibTeX RDF
19	Hao-Yung Lo, Hsiu-Feng Lin, Chichyang Chen, Jenshiuh Liu, Chia-Cheng Liu	Built-in Test with Modified-Booth High-Speed Pipelined Multipliers and Dividers.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	generator, BIST, computer arithmetic, polynomials, VLSI design, multiplication, division
19	Alexander Taubin, Karl Fant, John McCardle	Design of Delay-Insensitive Three Dimension Pipeline Array Multiplier for Image Processing.	ICCD	2002	DBLP DOI BibTeX RDF
19	Peter-Michael Seidel, Lee D. McFearin, David W. Matula	Binary Multiplication Radix-32 and Radix-256.	IEEE Symposium on Computer Arithmetic	2001	DBLP DOI BibTeX RDF
19	Takahiro Miomo, Koichi Yasuoka, Masanori Kanazawa	The Fastest Multiplier on FPGAs with Redundant Binary Representation.	FPL	2000	DBLP DOI BibTeX RDF
19	Menghui Zheng, Alexander Albicki	Low power and high speed multiplication design through mixed number representations.	ICCD	1995	DBLP DOI BibTeX RDF	high speed multiplication, mixed number representations, low power multiplication, reduced switching, Sign-Magnitude, Redundant Binary adder, Booth decoder, Carry-Propagation-Free, digital arithmetic, VLSI architecture, redundant number systems, Partial Products
19	Todd C. Marek	A new simulator workbench for comparing SIMD processing element architectures.	ACM Southeast Regional Conference	1992	DBLP DOI BibTeX RDF