Search results for "multiplying"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
60	Dan Zuras	More On Squaring and Multiplying Large Integers.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	large integers, FFT multipliers, digital arithmetic, multiplying, multiplying circuits, squaring, data handling
57	Lelia Festila, Lorant Andras Szolga, Mihaela Cirlugea, Robert Groza	Analog Multiplying/Weighting VLSI Cells for SVM Classifiers.	KES (3)	2008	DBLP DOI BibTeX RDF	weighting circuits, th domain, square-root domain, current controlled amplifiers, analog multipliers
48	Amit Khetan, Ning Song, Ron Goldman 0002	Sylvester-resultants for bivariate polynomials with planar newton polygons.	ISSAC	2004	DBLP DOI BibTeX RDF
48	Keqin Li, Victor Y. Pan	Parallel Matrix Multiplication on a Linear Array with a Reconfigurable Pipelined Bus System.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Bilinear algorithm, optical pipelined bus, distributed memory system, matrix multiplication, speedup, PRAM, reconfigurable system, linear array, cost-optimality
46	Ben J. M. Smeets	On the Use of the Binary Multiplying Channel in a Private Communication System.	EUROCRYPT	1984	DBLP DOI BibTeX RDF
43	Davis W. Blalock, John V. Guttag	Multiplying Matrices Without Multiplying.	CoRR	2021	DBLP BibTeX RDF
43	Davis W. Blalock, John V. Guttag	Multiplying Matrices Without Multiplying.	ICML	2021	DBLP BibTeX RDF
36	Shih-Wei Liao, Shih-Hao Hung, Chia-Heng Tu, Jen-Hao Chen	Scalable Lossless High Definition Image Coding on Multicore Platforms.	EUC	2007	DBLP DOI BibTeX RDF	Multicore SoC, Image Decompress, Embedded System, Parallelization, Image Compress, JPEG2000, Lossless, Digital Cinema
34	Loïc Maisonnasse, Éric Gaussier, Jean-Pierre Chevallet	Multiplying Concept Sources for Graph Modeling.	CLEF	2007	DBLP DOI BibTeX RDF
34	Vivek Sharma, Un-Ku Moon, Gabor C. Temes	A generic multilevel multiplying D/A converter for pipelined ADCs.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
31	Robert Michael Owens, Raminder Singh Bajwa, Mary Jane Irwin	Reducing the number of counters needed for integer multiplication.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	counting circuits, reasonably small integers, partial product accumulation, aperiodic convolution, convolution algorithms, partial product formulation, fairly large integers, digital arithmetic, multiplying circuits, counters, integer multiplication
24	Manish Kumar Shukla, A. Yavuz Oruç	On Matrix Multiplication Using Programmable Graph Architecture.	CISS	2007	DBLP DOI BibTeX RDF
24	Gábor Hetyei	The Stirling Polynomial of a Simplicial Complex.	Discret. Comput. Geom.	2006	DBLP DOI BibTeX RDF
24	Dan Tsafrir, Dror G. Feitelson	The Dynamics of Backfilling: Solving the Mystery of Why Increased Inaccuracy May Help.	IISWC	2006	DBLP DOI BibTeX RDF
24	Peter Bürgisser, Martin Lotz	Lower bounds on the bounded coefficient complexity of bilinear maps.	J. ACM	2004	DBLP DOI BibTeX RDF	bilinear circuits, lower bounds, Algebraic complexity, singular values
24	Keqin Li, Victor Y. Pan	Parallel Matrix Multiplication on a Linear Array with a Reconfigurable Pipelined Bus System.	IPPS/SPDP	1999	DBLP DOI BibTeX RDF
24	René J. van der Vleuten	New Methods for Multiplication-Free Arithmetic Coding.	Data Compression Conference	1999	DBLP DOI BibTeX RDF
24	Jennifer Seberry, Xian-Mo Zhang, Yuliang Zheng 0001	Nonlinearly Balanced Boolean Functions and Their Propagation Characteristics (Extended Abstract).	CRYPTO	1993	DBLP DOI BibTeX RDF
24	W. E. Mattis	A Hybrid Architecture for Neurocomputing (Abstract).	ACM Conference on Computer Science	1990	DBLP DOI BibTeX RDF
24	George I. Davida, Gilbert G. Walter	A Public Key Analog Cryptosystem.	EUROCRYPT	1987	DBLP DOI BibTeX RDF
22	José Joaquín Bernal, Diana H. Bueno-Carreño, Juan Jacobo Simón	Constructions of Abelian Codes multiplying dimension of cyclic codes.	CoRR	2024	DBLP DOI BibTeX RDF
22	Munir Ali, Afshan Khaliq, Muhammad Abid Anwar, Jianhang Lv, Muhammad Malik, Tian Feng, Srikrishna Chanakya Bodepudi, Hongwei Guo, Khurram Shehzad, Zongwen Li, Yunfan Dong, Wei Liu, Huan Hu, Yuda Zhao, Bin Yu, Yang Xu 0035	Graphene Channel Electron-Multiplying Charge-Coupled Pixel.	IEEE Access	2023	DBLP DOI BibTeX RDF
22	Hieu Minh Nguyen, Feifei Zhang, Ivan John O'Connell, Robert Bogdan Staszewski, Jeffrey Sean Walling	An Edge-Combining Frequency-Multiplying Class-D Power Amplifier.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
22	Hazem M. Bahig, Khaled A. Fathy	Sequential and parallel sliding window algorithms for multiplying large integers.	J. King Saud Univ. Comput. Inf. Sci.	2023	DBLP DOI BibTeX RDF
22	Hugo Daniel Macedo	Multiplying matrices using n arithmetic operations.	CoRR	2023	DBLP DOI BibTeX RDF
22	Jean-Guillaume Dumas, Clément Pernet, Alexandre Sedoglavic	Some fast algorithms multiplying a matrix by its adjoint.	J. Symb. Comput.	2023	DBLP DOI BibTeX RDF
22	Andres Asprilla, Andreia Cathelin, Yann Deval	0.45-mW 2.35-3.0 GHz Multiplying DLL with Calibration Loop in 28nm CMOS FD-SOI.	ESSCIRC	2023	DBLP DOI BibTeX RDF
22	Jianxiong Xu, José B. Sales Filho, Sudip Nag, Liam Long, Camilo Tejeiro, Eugene Hwang, Gerard O'Leary, Yu Huang, Mustafa A. Kanchwala, Mohammad Abdolrazzaghi, Chenxi Tang, Patty Liu, Yuan Sui, Xilin Liu, George V. Eleftheriades, José Zariffa, Roman Genov	Fascicle-Selective Bidirectional Peripheral Nerve Interface IC with 173dB FOM Noise-Shaping SAR ADCs and 1.38pJ/b Frequency-Multiplying Current-Ripple Radio Transmitter.	ISSCC	2023	DBLP DOI BibTeX RDF
22	Jin Sun, Jiahao Hu, Ziqi Song, Qing Li, Dian He, Hujun Jia	A Low Jitter Current-Mode Multiplying Delay-Locked Loop Applied to High-Precision TDC.	ASICON	2023	DBLP DOI BibTeX RDF
22	Shinichi Ikeda, Akira Iwata, Goichi Otomo, Tomoaki Suzuki, Hiroaki Iijima, Mikio Shiraishi, Shinya Kawakami, Masatomo Eimitsu, Yoshiki Matsuoka, Kiyohito Sato, Shigehiro Tsuchiya, Yoshinori Shigeta, Takuma Aoyama	A 6.4Gbps/pin NAND Flash Memory Multi-Chip Package Employing a Frequency Multiplying Bridge Chip for Scalable Performance and Capacity Storage Systems.	A-SSCC	2023	DBLP DOI BibTeX RDF
22	Yoav Moran, Oded Schwartz	Multiplying 2 × 2 Sub-Blocks Using 4 Multiplications.	SPAA	2023	DBLP DOI BibTeX RDF
22	Mohammad Mohsenzadeh, Mohammad Rezanejad, Jafar Adabi	Marxiplier: An Innovative Marx-Based Single-Source Multilevel Inverter With Voltage Multiplying Capability.	IEEE Trans. Ind. Electron.	2022	DBLP DOI BibTeX RDF
22	Yueduo Liu, Rongxin Bao, Zihao Zhu, Shiheng Yang, Xiong Zhou, Jun Yin 0001, Pui-In Mak, Qiang Li 0021	Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
22	Jiahao Hu, Zhongxian Huang, Baoxing Duan, Qing Li, Ziqi Song, Dian He	A Multiplying Delay-Locked Loop design with low jitter and high linearity.	ICTA	2022	DBLP DOI BibTeX RDF
22	Shanzhen Gao, Olumide Malomo, Ephrem Eyob, Weizheng Gao	Running Time Comparison and Applications of Multiplying $\mathbf{2} \times \mathbf{2}$ Matrices Using the Strassen Algorithm.	CSCI	2022	DBLP DOI BibTeX RDF
22	Amandeep Kaur 0005	A Multiplying Digital to Analog Converter Insensitive to Component Mismatch.	ISCAS	2022	DBLP DOI BibTeX RDF
22	Émilie Charlier, Célia Cisternino, Adeline Massuir	Minimal Automaton for Multiplying and Translating the Thue-Morse Set.	Electron. J. Comb.	2021	DBLP DOI BibTeX RDF
22	Sigang Ryu, Chan Young Park, Wooryeol Kim, Seuk Son, Jaeha Kim	A Time-Based Pipelined ADC Using Integrate-and-Fire Multiplying-DAC.	IEEE Trans. Circuits Syst. I Regul. Pap.	2021	DBLP DOI BibTeX RDF
22	Kyu-Jin Choi, Hong Goo Yeo, Hongsoo Choi, Dong-Woo Jee	A 28.7V Modular Supply Multiplying Pulser With 75.4% Power Reduction Relative to CV2f.	IEEE Trans. Circuits Syst. II Express Briefs	2021	DBLP DOI BibTeX RDF
22	Jean-Guillaume Dumas, Clément Pernet, Alexandre Sedoglavic	Some fast algorithms multiplying a matrix by its adjoint.	CoRR	2021	DBLP BibTeX RDF
22	Toshiharu Obara, Tsubasa Shobudani, Mamoru Sawahashi, Yoshihisa Kishiyama	BLER of Turbo SIC Multiplying Weighting Factor to Symbol Estimates for OFDM Using FTN Signaling.	APWCS	2021	DBLP DOI BibTeX RDF
22	Tetsuya Asakawa, Riku Tsuneda, Masaki Aono	Visual Sentiment Analysis Multiplying Deep learning and Vision Transformers.	MediaEval	2021	DBLP BibTeX RDF
22	Ho Won Kim 0004, Kang-Yoon Lee	Design of Multiplying Delay Locked Loop that prevents Harmonic Lock and is insensitive to PVT Variation.	ISOCC	2021	DBLP DOI BibTeX RDF
22	Jin Wu, Shuang Chen, Kang Hu, Lixia Zheng, Weifeng Sun	A low jitter multiplying delay-locked loop with static phase offset elimination applied to time-to-digital converter.	Microelectron. J.	2020	DBLP DOI BibTeX RDF
22	José Joaquín Bernal, Diana H. Bueno-Carreño, Juan Jacobo Simón	Constructions of Abelian Codes Multiplying Dimension of Cyclic Codes.	Math. Comput. Sci.	2020	DBLP DOI BibTeX RDF
22	Bahar Asgari, Ramyad Hadidi, Hyesoon Kim	MEISSA: Multiplying Matrices Efficiently in a Scalable Systolic Architecture.	ICCD	2020	DBLP DOI BibTeX RDF
22	Muhammad Abrar Akram, Myeong-Ho Lee, Dong-Hyeok Cho, In-Chul Hwang	A 0.012mm2, 0.96-mW All-Digital Multiplying Delay-Locked Loop Based Frequency Synthesizer for GPS-L4 band.	ICCE	2020	DBLP DOI BibTeX RDF
22	Marijn Heule, Manuel Kauers, Martina Seidl	A family of schemes for multiplying 3 × 3 matrices with 23 coefficient multiplications.	ACM Commun. Comput. Algebra	2019	DBLP DOI BibTeX RDF
22	Ryszard Rybski, Janusz Kaczmarek, Miroslaw Koziol, Marian Kampik	Errors of Multiplying D/A Converters Used for Precise AC Voltage Division.	IEEE Trans. Instrum. Meas.	2019	DBLP DOI BibTeX RDF
22	Émilie Charlier, Célia Cisternino, Adeline Massuir	Minimal automaton for multiplying and translating the Thue-Morse set.	CoRR	2019	DBLP BibTeX RDF
22	G. Shanmugaraj, N. Kalaiarasi	Hearing aid speech signal enhancement via N-parallel FIR-multiplying polynomials for Tamil language dialect syllable ripple and transition variation.	Clust. Comput.	2019	DBLP DOI BibTeX RDF
22	Alessio Santiccioli, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino	Time-Variant Modeling and Analysis of Multiplying Delay-Locked Loops.	IEEE Trans. Circuits Syst. I Regul. Pap.	2019	DBLP DOI BibTeX RDF
22	Siddharth Joshi, Chul Kim, Chris M. Thomas, Gert Cauwenberghs	Digitally Adaptive High-Fidelity Analog Array Signal Processing Resilient to Capacitive Multiplying DAC Inter-Stage Gain Error.	IEEE Trans. Circuits Syst. I Regul. Pap.	2019	DBLP DOI BibTeX RDF
22	Dusan Obradovic, Milos Cabrilo, Ivan Milosavljevic, Dusan Krcum, Veljko Mihajlovic	A 250 - 800-MHz Multiplying DLL for Reference Frequency Generation with Improved Phase Noise.	EUROCON	2019	DBLP DOI BibTeX RDF
22	Koji Orikawa, Satoshi Ogasawara, Masatsugu Takemoto, Jun-ichi Itoh	A Frequency Multiplying Circuit Containing a High-frequency Output Inverter and an Impedance Matching Transformer.	IECON	2019	DBLP DOI BibTeX RDF
22	Ming-Shing Chen, Chen-Mou Cheng, Po-Chun Kuo, Wen-Ding Li, Bo-Yin Yang	Multiplying boolean Polynomials with Frobenius Partitions in Additive Fast Fourier Transform.	CoRR	2018	DBLP BibTeX RDF
22	Gilbert Strang	Multiplying and Factoring Matrices.	Am. Math. Mon.	2018	DBLP DOI BibTeX RDF
22	Fernando Ortega-Ojeda, Matías Calcerrada, Alejandro Ferrero, Joaquín Campos 0001, Carmen Garcia-Ruiz	Measuring the Human Ultra-Weak Photon Emission Distribution Using an Electron-Multiplying, Charge-Coupled Device as a Sensor.	Sensors	2018	DBLP DOI BibTeX RDF
22	Jongsun Kim, Sangwoo Han	A Fast-Locking All-Digital Multiplying DLL for Fractional-Ratio Dynamic Frequency Scaling.	IEEE Trans. Circuits Syst. II Express Briefs	2018	DBLP DOI BibTeX RDF
22	Conghui Zhang, Ruiying He, Xiaoyu Zhang, Yongfeng Wei	Photonic Generation of Millimeter-Wave Signals With Frequency-Multiplying and Tunable Phase Shift.	ICFSP	2018	DBLP DOI BibTeX RDF
22	Hyunik Kim, Yongjo Kim, Taeik Kim, Hyung Jong Ko, SeongHwan Cho	A 2.4-GHz 1.5-mW Digital Multiplying Delay-Locked Loop Using Pulsewidth Comparator and Double Injection Technique.	IEEE J. Solid State Circuits	2017	DBLP DOI BibTeX RDF
22	Aleksandr Cariow, Galina Cariowa, Marina Chicheva	Hardware-Efficient Schemes of Quaternion Multiplying Units for 2D Discrete Quaternion Fourier Transform Processors.	CoRR	2017	DBLP BibTeX RDF
22	Alexandre Sedoglavic	A non-commutative algorithm for multiplying 5 $\times$ 5 matrices using 99 multiplications.	CoRR	2017	DBLP BibTeX RDF
22	Alexandre Sedoglavic	A non-commutative algorithm for multiplying (7×7) matrices using 250 multiplications.	CoRR	2017	DBLP BibTeX RDF
22	Eric G. Stevens, Jeffrey A. Clayhold, Hung Doan, Robert P. Fabinski, Jaroslav Hynecek, Stephen L. Kosman, Christopher Parks	Recent Enhancements to Interline and Electron Multiplying CCD Image Sensors.	Sensors	2017	DBLP DOI BibTeX RDF
22	Jongsun Kim, Bongho Bae	A 2-4 GHz fast-locking frequency multiplying delay-locked loop.	IEICE Electron. Express	2017	DBLP DOI BibTeX RDF
22	Farinoush Saffar, Mitra Mirhassani, Majid Ahmadi	A neural network architecture using high resolution multiplying digital to analog converters.	MWSCAS	2017	DBLP DOI BibTeX RDF
22	Vivek Mangal, Peter R. Kinget	An ultra-low-power wake-up receiver with voltage-multiplying self-mixer and interferer-enhanced sensitivity.	CICC	2017	DBLP DOI BibTeX RDF
22	Amaravati Anvesha, Arijit Raychowdhury	A 65nm 376nA 0.4V linear classifier using time-based matrix-multiplying ADC with non-linearity aware training.	A-SSCC	2017	DBLP DOI BibTeX RDF
22	Nikolaus Lee Wasmoen	Multiplying Access: the Marianne Moore Digital Archive's Tools and Methods for Collaboration.	DH	2017	DBLP BibTeX RDF
22	Marek Parfieniuk, Sang Yoon Park	Sparse-Iteration 4D CORDIC Algorithms for Multiplying Quaternions.	IEEE Trans. Computers	2016	DBLP DOI BibTeX RDF
22	Xinjie Wang, Tadeusz Kwasniewski	A reduced reference spur multiplying delay-locked loop.	Int. J. Circuit Theory Appl.	2016	DBLP DOI BibTeX RDF
22	Igor S. Sergeev	On the circuit complexity of the standard and the Karatsuba methods of multiplying integers.	CoRR	2016	DBLP BibTeX RDF
22	Ehab Belal, Hassan Mostafa, Yehea Ismail, M. Sameh Said	A voltage multiplying AC/DC converter for energy harvesting applications.	ICM	2016	DBLP DOI BibTeX RDF
22	Nick A. Petrovsky, Andrew V. Stankevich, Alexander A. Petrovsky	Pipelined block-lifting-based embedded processor for multiplying quaternions using distributed arithmetic.	MECO	2016	DBLP DOI BibTeX RDF
22	Jongsun Kim, Bongho Bae	A fast-locking clock multiplying DLL.	ISOCC	2016	DBLP DOI BibTeX RDF
22	Chao Qi, Yanling Chen, A. J. Han Vinck, Xiaohu Tang	Secrecy coding for the binary multiplying wiretap channel.	ISITA	2016	DBLP BibTeX RDF
22	Salvatore Levantino, Giovanni Marucci, Giovanni Marzin, Andrea Fenaroli, Carlo Samori, Andrea L. Lacaita	A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop.	IEEE J. Solid State Circuits	2015	DBLP DOI BibTeX RDF
22	Aleksandr Cariow, Galina Cariowa, Jaroslaw Knapinski	Derivation of a low multiplicative complexity algorithm for multiplying hyperbolic octonions.	CoRR	2015	DBLP BibTeX RDF
22	Aleksandr Cariow, Galina Cariowa	A new algorithm for multiplying two Dirac numbers.	CoRR	2015	DBLP BibTeX RDF
22	Elke E. Reinhuber	Multiplying the Narrative.	Culture Computing	2015	DBLP DOI BibTeX RDF
22	Kiran Raj Ramamoorthy, Dip Sankar Banerjee, Kannan Srinathan, Kishore Kothapalli	A Novel Heterogeneous Algorithm for Multiplying Scale-Free Sparse Matrices.	IPDPS Workshops	2015	DBLP DOI BibTeX RDF
22	Jintao Zhang, Zhuo Wang 0001, Naveen Verma	18.4 A matrix-multiplying ADC implementing a machine-learning classifier directly with data conversion.	ISSCC	2015	DBLP DOI BibTeX RDF
22	Zhe Zhao 0003, Yongxiong Ren, Guodong Xie, Long Li 0001, Yan Yan 0010, Nisar Ahmed, Zhe Wang 0020, Nima Ashrafi, Solyman Ashrafi, Roger D. Linquist, Alan E. Willner	Dividing and multiplying the mode order for orbital-angular-momentum beams.	ECOC	2015	DBLP DOI BibTeX RDF
22	Jeremy A. Roberts, Benoit Forget	Multigroup diffusion preconditioners for multiplying fixed-source transport problems.	J. Comput. Phys.	2014	DBLP DOI BibTeX RDF
22	Chorng-Sii Hwang, Ting-Li Chu, Wen-Cheng Chen	A clock generator based on multiplying delay-locked loop.	SoCC	2014	DBLP DOI BibTeX RDF
22	Laurent Beaudou, César Hernández-Vélez, Gelasio Salazar	Making a Graph Crossing-Critical by Multiplying its Edges.	Electron. J. Comb.	2013	DBLP DOI BibTeX RDF
22	Youjiao Zou, Wenping Ma, Zhanjun Ran, Shangping Wang	Newmultivariate hash function quadratic polynomials multiplying linear polynomials.	IET Inf. Secur.	2013	DBLP DOI BibTeX RDF
22	Amr Elshazly, Rajesh Inti, Brian Young, Pavan Kumar Hanumolu	Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops.	IEEE J. Solid State Circuits	2013	DBLP DOI BibTeX RDF
22	Sounak Roy, Hiranmoy Basak, Swapna Banerjee	Foreground calibration technique of a pipeline ADC using capacitor ratio of Multiplying Digital-to-Analog Converter (MDAC).	Microelectron. J.	2013	DBLP DOI BibTeX RDF
22	Hao Hua	Multiplying Architectural Layouts and 3D Forms: Interplay of Necessity and Contingency in Architectural Modeling.	CAAD Futures	2013	DBLP DOI BibTeX RDF
22	Dong-Woo Jee, Dennis Sylvester, David T. Blaauw, Jae-Yoon Sim	A 0.45V 423nW 3.2MHz multiplying DLL with leakage-based oscillator for ultra-low-power sensor platforms.	ISSCC	2013	DBLP DOI BibTeX RDF
22	Jerry Chao, Sally E. Ward, Raimund J. Ober	Fisher information matrix for branching processes with application to electron-multiplying charge-coupled devices.	Multidimens. Syst. Signal Process.	2012	DBLP DOI BibTeX RDF
22	Hamed Mazhab-Jafari, Leyla Soleymani, Roman Genov	16-Channel CMOS Impedance Spectroscopy DNA Analyzer With Dual-Slope Multiplying ADCs.	IEEE Trans. Biomed. Circuits Syst.	2012	DBLP DOI BibTeX RDF
22	Hyeong-Keon An	Optimal Design of Multiplying and Dividing Circuit for Reed-Solomon ECC Codec Processor.	ICHIT (1)	2012	DBLP DOI BibTeX RDF
22	Virginia Vassilevska Williams	Multiplying matrices faster than coppersmith-winograd.	STOC	2012	DBLP DOI BibTeX RDF
22	Yoshifumi Sakai	A fast algorithm for multiplying min-sum permutations.	Discret. Appl. Math.	2011	DBLP DOI BibTeX RDF
22	Adham Atyabi, Sean P. Fitzgibbon, David M. W. Powers	Multiplying the Mileage of Your Dataset with Subwindowing.	Brain Informatics	2011	DBLP DOI BibTeX RDF
22	Tsz-Wo Sze	Schönhage-Strassen algorithm with MapReduce for multiplying terabit integers.	SNC	2011	DBLP DOI BibTeX RDF
22	Chiou-Bang Chen, Horng-Yuan Shih	A 400 MHz 0.934ps rms jitter multiplying delay lock loop in 90-nm CMOS process.	ICECS	2010	DBLP DOI BibTeX RDF