Search results for "observabilities"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
52	Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas	Statistical path delay fault coverage estimation for synchronous sequential circuits.	VLSI Design	1996	DBLP DOI BibTeX RDF	path delay fault coverage estimation, multi-valued algebra, signal statistics, latch updating, fault diagnosis, logic testing, delays, probability, controllability, controllability, statistical analysis, sequential circuits, observability, observabilities, logic simulation, synchronous sequential circuits, statistical estimation
52	Zaifu Zhang, Robert D. McLeod, Gregory E. Bridges	Statistical estimation of delay fault detectabilities and fault grading.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	delay fault detectabilities, fault grading, STAFAN, transition observabilities, fanout stems, fanout free region, gate line transition controllabilities, VLSI, fault diagnosis, logic testing, logic testing, statistical analysis, fault coverage, benchmark circuits, statistical estimation
52	Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell	Statistical methods for delay fault coverage analysis.	VLSI Design	1995	DBLP DOI BibTeX RDF	delay fault coverage analysis, true value simulation, multi-value logic system, implicit random path sampling procedure, linear-time estimate, fault coverage estimates, longest path theorem, fanout branches, fault diagnosis, logic testing, delays, probability, statistical analysis, observabilities, multivalued logic, propagation delay, detection probabilities, statistical techniques, transition probabilities
46		Convergence of P!=NP Toward P=NP in Higher Order of Observabilities.	CoRR	2017	DBLP BibTeX RDF
43	Vishal J. Mehta, Kunal K. Dave, Vishwani D. Agrawal, Michael L. Bushnell	A Fault-Independent Transitive Closure Algorithm for Redundancy Identification.	VLSI Design	2003	DBLP DOI BibTeX RDF
43	Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas	Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	statistical fault analysis, fault simulation, delay test, path-delay faults, transition faults
43	Zaifu Zhang, Robert D. McLeod, Gregory E. Bridges	Statistical estimation of delay fault detectabilities and fault grading.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	transition delay and path delay faults, statistical delay fault analysis, fault detectabilities, fault coverage, random patterns
21	Smita Krishnaswamy, Stephen Plaza, Igor L. Markov, John P. Hayes	Signature-Based SER Analysis and Design of Logic Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
21	Cédric Pralet, Thomas Schiex, Gérard Verfaillie	Decomposition of Multi-operator Queries on Semiring-Based Graphical Models.	CP	2006	DBLP DOI BibTeX RDF
21	Cristian Sminchisescu, Bill Triggs	Kinematic Jump Processes For Monocular 3D Human Tracking.	CVPR (1)	2003	DBLP DOI BibTeX RDF	Monocular 3D human body tracking, kinematic ambiguity, Covariance Scaled Sampling, high-dimensional search, particle filtering, constrained optimization, inverse kinematics
21	Sandhya Seshadri, Michael S. Hsiao	Behavioral-Level DFT via Formal Operator Testability Measures.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	behavioral level, operator testability, value range, SSA representation, DFT
21	Huan-Chih Tsai, Sudipta Bhawmik, Kwang-Ting Cheng	An almost full-scan BIST solution-higher fault coverage and shorter test application time.	ITC	1998	DBLP DOI BibTeX RDF
21	Valery A. Vardanian	Exact probabilistic analysis of error detection for parity checkers.	VTS	1997	DBLP DOI BibTeX RDF	circuit under check, multi-output supergate, combinational CUC, restricted observability, restricted detectability, concurrent checker, latency, error detection, combinational circuits, probabilistic analysis, single stuck-at fault, parity checker
21	Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell	Fault coverage estimation by test vector sampling.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF