Search results for "opamp"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
90	George Jie Yuan, Nabil H. Farhat	A compensation-based optimization methodology for gain-boosted opamp.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
82	Vincent S. L. Cheung, Howard C. Luong, Mansun Chan	A 0.9-V 0.2-μW CMOS single-opamp-based switched-opamp ΣΔ modulator for pacemaker applications.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
78	M. Ali-Bakhshian, K. Sadeghi	A novel continuous-time common-mode feedback for low-voltage switched-OPAMP.	ISLPED	2004	DBLP DOI BibTeX RDF	CMFB, delta-sigma, switched-OPAMP, low-voltage, continuous-time
76	Teemu Salo, Saska Lindfors, Kari Halonen	A low-voltage single-Opamp 4th-order band-pass Sigma-Delta-modulator.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
70	Nagendra Krishnapura, Shanthi Pavan	Negative Feedback System and Circuit Design.	VLSI Design	2009	DBLP DOI BibTeX RDF
62	Edward K. F. Lee, Anthony Lam, Taihu Li	A 0.65V rail-to-rail constant gm opamp for biomedical applications.	ISCAS	2008	DBLP DOI BibTeX RDF
62	Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins	A novel low-voltage finite-gain compensation technique for high-speed reset- and switched-opamp circuits.	ISCAS	2006	DBLP DOI BibTeX RDF
62	Tahereh Kahookar Toosi, Ehsan Zhian Tabasy, Hassan Sarbishaei, Reza Lotfi	ISECAD: an iterative simulation-equation-based opamp-design CAD tool.	ISCAS	2006	DBLP DOI BibTeX RDF
56	Mohammad Taherzadeh-Sani, Anas A. Hamoui	Digital background calibration of interstage-gain and capacitor-mismatch errors in pipelined ADCs.	ISCAS	2006	DBLP DOI BibTeX RDF
56	Amorn Jiraseree-amornkun, Apisak Worapishet, Eric A. M. Klumperink, Bram Nauta, Wanlop Surakampontorn	Slew rate induced distortion in switched-resistor integrators.	ISCAS	2006	DBLP DOI BibTeX RDF
48	Weixun Yan, Robert Kolm, Horst Zimmermann	A low-voltage low-power fully differential rail-to-rail input/output opamp in 65-nm CMOS.	ISCAS	2008	DBLP DOI BibTeX RDF
48	Amal Kumar Kundu, Subho Chatterjee, Tarun Kanti Bhattacharyya	A Fast Settling 100dB OPAMP in 180nm CMOS Process with Compensation Based Optimisation.	VLSI Design	2008	DBLP DOI BibTeX RDF
48	Anas A. Hamoui, T. Alhajj, Mohammad Taherzadeh-Sani	Behavioral modeling of Opamp gain and dynamic effectsfor power optimization of Delta-Sigma modulators and pipelined ADCs.	ISLPED	2006	DBLP DOI BibTeX RDF	sigma-delta (??) modulation, synthesis, behavioral modeling, discrete-time systems, analog-to-digital conversion
48	Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins	A novel very low-voltage SC-CMFB technique for fully-differential reset-opamp circuits.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
48	Bjørnar Hernes, Øystein Moldsvor, Trond Sæther	A -80 dB HD3 opamp in 3.3 V CMOS technology using tail current compensation.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
45	Ram Suryanarayan, Anubhav Gupta, Travis N. Blalock	A slew rate enhancement technique for operational amplifiers based on a tunable active Gm-based capacitance multiplication circuit.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	opamp, feedback, CMOS, compensation, operational amplifier, slew rate
42	Edward K. Lee 0002, Eusebiu Matei, Ravi S. Ananth	A 0.9 V rail-to-rail constant gm amplifier for implantable biomedical applications.	ISCAS	2006	DBLP DOI BibTeX RDF
42	Drazen Jurisic, Neven Mijat, George S. Moschytz	Low-sensitivity active-RC filters using impedance tapering of symmetrical bridged-T and twin-T networks.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
42	Volney C. Vincence, Carlos Galup-Montoro, Márcio C. Schneider	A low-voltage CMOS class-AB operational amplifier.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
42	Jipeng Li, Un-Ku Moon	High-speed pipelined A/D converter using time-shifted CDS technique.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
42	José Vicente Calvano, Vladimir Castro Alves, Marcelo Lubaszewski	Testing a PWM circuit using functional fault models and compact test vectors for operational amplifiers.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	PWM circuit, compact test vectors, analog VLSI technology, functional fault macromodels, compact test vector construction, open loop gain, CMMR, analog circuit simulation complexity, VLSI, integrated circuit testing, design for testability, automatic test pattern generation, fault modeling, fault simulation, fault simulation, operational amplifiers, operational amplifiers, test pattern, functional fault models, analogue circuits, fault dictionary, pulse width modulation, slew-rate
39	Kai Xing, Wei Wang 0177, Yan Zhu 0001, Chi-Hang Chan, Rui Paulo Martins	A Single-Opamp Third Order CT ΔΣ Modulator With SAB-ELD-Merged Integrator and Three-Stage Hybrid Compensation Opamp.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
39	Kai Xing, Wei Wang 0177, Yan Zhu 0001, Chi-Hang Chan, Rui Paulo Martins	A 10.4mW 50MHz-BW 80dB-DR Single-Opamp Third-Order CTSDM with SAB-ELD-Merged Integrator and 3-Stage Opamp.	VLSI Circuits	2020	DBLP DOI BibTeX RDF
39	Benjamin P. Hershberg, Skyler Weaver, Un-Ku Moon	A 1.4V signal swing hybrid CLS-opamp/ZCBC pipelined ADC using a 300mV output swing opamp.	ISSCC	2010	DBLP DOI BibTeX RDF
39	Hsin-Hung Ou, Bin-Da Liu	A 1-v 9-bit, 2.5-Msample/s pipelined ADC with merged switched-opamp and opamp-sharing techniques.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
34	Massoud Momeni, Petru Bogdan Bacinschi, Manfred Glesner	Comparison of Opamp-Based and Comparator-Based Delta-Sigma Modulation.	DATE	2008	DBLP DOI BibTeX RDF
34	Jen-Shiun Chiang, Hsueh-Ping Chen, Cheng-Ming Ying	A 1V 0.54µW fourth order switched capacitor filter with switched opamp technique for cardiac pacemaker sensing channel.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
34	Chon-In Lao, Ho-leng Leong, Kuoi-Fok Au, Kuok-Hang Mok, Seng-Pan U., Rui Paulo Martins	A 10.7-MHz bandpass sigma-delta modulator using double-delay single-opamp SC resonator with double-sampling.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
34	José Vicente Calvano, Antonio Carneiro de Mesquita Filho, Vladimir Castro Alves, Marcelo Lubaszewski	Fault Models and Test Generation for OpAmp Circuits - The FFM.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	test generation, fault model, analog test, operational amplifiers
34	Vijay Rentala, Saroj Rout, Edward Lee, Robert J. Weber	A constant GM rail-to-rail opamp with a novel input stage for BiCMOS process.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
31	Samiran DasGupta, Pradip Mandal	An Improvised MOS Transistor Model Suitable for Geometric Program Based Analog Circuit Sizing in Sub-micron Technology.	VLSI Design	2010	DBLP DOI BibTeX RDF	opamp, submicron sizing, design automation, geometric program
28	Ying Wei 0002, Alex Doboli	Structural Macromodeling of Analog Circuits Through Model Decoupling and Transformation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
28	Marcello De Matteis, Stefano D'Amico, Andrea Baschirotto	A 600mV 3.6mW 68dB DR 4th Order Analog Base Band Filter for WLAN Receivers.	ISCAS	2007	DBLP DOI BibTeX RDF
28	Mohammad Maymandi-Nejad, Manoj Sachdev	DTMOS Technique for Low-Voltage Analog Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
28	Shu-Chuan Huang, Min-Hsiung Liao, Chih-Sheng Hsu	A low-distortion fourth-order bandpass delta-sigma modulator.	ISCAS	2006	DBLP DOI BibTeX RDF
28	Peter R. Kinget, Aurel A. Lazar, László T. Tóth	On the robustness of an analog VLSI implementation of a time encoding machine.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
28	Joan Font, J. Ginard, Rodrigo Picos, Eugeni Isern 0001, Jaume Segura 0001, Miquel Roca 0001, Eugenio García	A BICS for CMOS OpAmps by Monitoring the Supply Current Peak.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	oscillation test, analog test, Built-In Current Sensor, current test
28	Reza Lotfi, Mohammad Taherzadeh-Sani, M. Yaser Azizi, Omid Shoaei	A low-power design methodology for high-resolution pipelined analog-to-digital converters.	ISLPED	2003	DBLP DOI BibTeX RDF	low-power design, operational amplifiers, pipelined analog-to-digital converters
28	Varun Aggarwal	Evolving Sinusoidal Oscillators Using Genetic Algorithms.	Evolvable Hardware	2003	DBLP DOI BibTeX RDF
28	Joan Font, J. Ginard, Eugeni Isern 0001, Miquel Roca 0001, Jaume Segura 0001, Eugenio García	A BICS for CMOS Opamps by Monitoring the Supply Current Peak.	IOLTW	2002	DBLP DOI BibTeX RDF
28	Adrian Maxim, Danielle Andreu, Marc Cousineau, Jacques Boucher	A novel SPICE behavioral macromodel of operational amplifiers including a high accuracy description of frequency characteristics.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
28	Chen-Yang Pan, Kwang-Ting Cheng, Sandeep Gupta 0001	Fault macromodeling and a testing strategy for opamps.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	catastrophic fault model, operational amplifier design for testability, analog test, macromodeling, parametric faults
28	Mehrdad Negahban, Daniel Gajski	Silicon compilation of switched: capacitor networks.	EURO-DAC	1990	DBLP DOI BibTeX RDF
20	P. V. Ananda Mohan	New Generalized Impedance Converter (GIC)-Based Two-Opamp Active RC Biquads.	Circuits Syst. Signal Process.	2024	DBLP DOI BibTeX RDF
20	Sukju Yun, Jaegeun Cho, Sengjun Jo, In-Chul Hwang, Youngjin Kim, Seongheon Jeong, Jungeun Lee, Sanghoon Lee, Keontae Kim, Seungyup Yoo, Sangwoo Han, Kuduck Kwon	A 2.4/5 GHz Dual-Band Low-Noise and Highly Linear Receiver With a New Power-Efficient Feedforward OPAMP for WiFi-6 Applications.	IEEE Access	2023	DBLP DOI BibTeX RDF
20	Sayan Banerjee, Ankesh Jain	Modified Gm-Free Assisted Opamp Technique in Continuous Time Delta Sigma Modulators.	APCCAS	2023	DBLP DOI BibTeX RDF
20	Shuenn-Yuh Lee, Hao-Yun Lee, Chia-Ho Kung, Po-Han Su, Ju-Yi Chen	A 0.8-μW and 74-dB High-Pass Sigma-Delta Modulator With OPAMP Sharing and Noise-Coupling Techniques for Biomedical Signal Acquisition.	IEEE Trans. Biomed. Circuits Syst.	2022	DBLP DOI BibTeX RDF
20	António Gusmão 0001, Ricardo Póvoa, Nuno Horta, Nuno Lourenço 0003, Ricardo Martins 0003	DeepPlacer: A custom integrated OpAmp placement tool using deep models.	Appl. Soft Comput.	2022	DBLP DOI BibTeX RDF
20	Salvatore Pennisi, Francesco Pulvirenti, Katia Samperi	Frequency Compensation Scheme for a Full GaN OpAmp driving 1-nF load.	ISCAS	2022	DBLP DOI BibTeX RDF
20	Ömer T. Keles, Metin Yazgi	Design of an Opamp-RC Lowpass Filter in 22nm FDSOI Technology.	SIU	2022	DBLP DOI BibTeX RDF
20	Maged ElAnsary, Jianxiong Xu, José B. Sales Filho, Gairik Dutta, Liam Long, Camilo Tejeiro, Aly Shoukry, Chenxi Tang, Enver Kilinc, Jaimin Joshi, Parisa Sabetian, Samantha Unger, José Zariffa, Paul B. Yoo, Roman Genov	Bidirectional Peripheral Nerve Interface With 64 Second-Order Opamp-Less ΔΣ ADCs and Fully Integrated Wireless Power/Data Transmission.	IEEE J. Solid State Circuits	2021	DBLP DOI BibTeX RDF
20	Anoop Narayan Bhat, Ronan A. R. van der Zee, Bram Nauta	A Baseband-Matching-Resistor Noise-Canceling Receiver With a Three-Stage Inverter-Only OpAmp for High In-Band IIP3 and Wide IF Applications.	IEEE J. Solid State Circuits	2021	DBLP DOI BibTeX RDF
20	Mohammad Reza Pazhouhandeh, Hossein Kassiri, Aly Shoukry, Iliya Weisspapir, Peter L. Carlen, Roman Genov	Opamp-Less Sub-μW/Channel Δ-Modulated Neural-ADC With Super-GΩ Input Impedance.	IEEE J. Solid State Circuits	2021	DBLP DOI BibTeX RDF
20	Shih-Che Kuo, Jia-Sheng Huang, Yu-Cheng Huang, Chia-Wei Kao, Che-Wei Hsu, Chia-Hung Chen	A Multi-Step Incremental Analog-to-Digital Converter With a Single Opamp and Two- Capacitor SAR Extended Counting.	IEEE Trans. Circuits Syst. I Regul. Pap.	2021	DBLP DOI BibTeX RDF
20	Mohsen Padash, Mostafa Yargholi, Maryam Shojaei Baghini	An Opamp-Less PVT Compensation Structure for Ramp Generator Circuit.	J. Circuits Syst. Comput.	2021	DBLP DOI BibTeX RDF
20	Toprak Kayanselçuk, Ertan Zencir	Ultra-Wide Bandwidth Fully Differential CMOS Opamp with a Novel Bandwidth Extension Technique for SoC Active Filter Applications.	J. Circuits Syst. Comput.	2021	DBLP DOI BibTeX RDF
20	Fernando Cardes, Nikhita Baladari, Jihyun Lee, Andreas Hierlemann	A Low-Power Opamp-Less Second-Order Delta-Sigma Modulator for Bioelectrical Signals in 0.18 µm CMOS.	Sensors	2021	DBLP DOI BibTeX RDF
20	Johannes Wagner 0003, Takashi Miki, Maurits Ortmanns	Compensation of Finite GBW in CT Bandpass SDMs based on Single-OpAmp Resonators with Positive-Feedback.	MWSCAS	2021	DBLP DOI BibTeX RDF
20	Mohamed A. Mokhtar, Martin Merkle, John G. Kauffman, Maurits Ortmanns	A Comparative Study of Noise Behavior in Single-Opamp Resonators in Delta-Sigma Modulators.	ICECS	2021	DBLP DOI BibTeX RDF
20	Maged ElAnsary, Jianxiong Xu, José B. Sales Filho, Gairik Dutta, Liam Long, Aly Shoukry, Camilo Tejeiro, Chenxi Tang, Enver Kilinc, Jaimin Joshi, Parisa Sabetian, Samantha Unger, José Zariffa, Paul B. Yoo, Roman Genov	28.8 Multi-Modal Peripheral Nerve Active Probe and Microstimulator with On-Chip Dual-Coil Power/Data Transmission and 64 2nd-Order Opamp-Less ΔΣ ADCs.	ISSCC	2021	DBLP DOI BibTeX RDF
20	Maged ElAnsary, Nima Soltani, Hossein Kassiri, Ruben Machado, Suzie Dufour, Peter L. Carlen, Michael Thompson, Roman Genov	50nW Opamp-Less ΔΣ-Modulated Bioimpedance Spectrum Analyzer for Electrochemical Brain Interfacing.	IEEE J. Solid State Circuits	2020	DBLP DOI BibTeX RDF
20	Guoyong Shi	Automatic Stage-form Circuit Reduction for Multistage Opamp Design Equation Generation.	ACM Trans. Design Autom. Electr. Syst.	2020	DBLP DOI BibTeX RDF
20	Susie Kim, Cyuyeol Rhee, Suhwan Kim	A Wide Dynamic Range Multi-Mode Band-Pass Continuous-Time Delta-Sigma Modulator Employing Single-Opamp Resonator With Positive Resistor-Feedback.	IEEE Trans. Circuits Syst. II Express Briefs	2020	DBLP DOI BibTeX RDF
20	Alexander Meyer, Ralf Wunderlich, Stefan Heinen	Analysis of Opamp Non-Idealities in Quadrature Bandpass Sigma-Delta Modulators.	ICECS	2020	DBLP DOI BibTeX RDF
20	Rajasekhar Nagulapalli, Khaled Hayatleh, Steve Barker, B. Naresh Kumar Reddy	A two-stage opamp frequency Compensation technique by splitting the 2nd stage.	ICCCNT	2020	DBLP DOI BibTeX RDF
20	Sung-En Hsieh, Chih-Cheng Hsieh	A 0.4-V 13-bit 270-kS/s SAR-ISDM ADC With Opamp-Less Time-Domain Integrator.	IEEE J. Solid State Circuits	2019	DBLP DOI BibTeX RDF
20	Tsung-Chih Hung, Tai-Haur Kuo	A 75.3-dB SNDR 24-MS/s Ring Amplifier-Based Pipelined ADC Using Averaging Correlated Level Shifting and Reference Swapping for Reducing Errors From Finite Opamp Gain and Capacitor Mismatch.	IEEE J. Solid State Circuits	2019	DBLP DOI BibTeX RDF
20	Rajasekhar Nagulapalli, Khaled Hayatleh, Steve Barker, Bilal Yassine, Saddam Zourob, Sumathi Raparthy, Nabil Yassine	A Start-up Assisted Fully Differential Folded Cascode Opamp.	J. Circuits Syst. Comput.	2019	DBLP DOI BibTeX RDF
20	Jingyu Wang 0003, Yongyuan Li, Zhangming Zhu	A 0.6-V pseudo-differential OTA with switched-opamp technique for low power applications.	Microelectron. J.	2019	DBLP DOI BibTeX RDF
20	Mahmoud Sadollahi, Gabor C. Temes	A 10-MHz BW 77.9 dB SNDR DT MASH Δ!Σ ADC With NC-VCO-Based Quantizer and OPAMP Sharing.	IEEE Trans. Circuits Syst. I Regul. Pap.	2019	DBLP DOI BibTeX RDF
20	Jiye Lim, Jintae Kim	A 20-kHz~16-MHz Programmable-Bandwidth 4th Order Active Filter Using Gain-Boosted Opamp With Negative Resistance in 65-nm CMOS.	IEEE Trans. Circuits Syst. II Express Briefs	2019	DBLP DOI BibTeX RDF
20	Shuai Li, Jianguo Diao, Yimin Wu, Fan Ye 0001, Junyan Ren	A 20MHz Bandwidth Band-Pass Noise-Shaping SAR ADC With OPAMP Sharing Switched-Capacitor Filter.	MWSCAS	2019	DBLP DOI BibTeX RDF
20	Vikas Aggarwal, Ritabrata Bhattacharya, Ashish Gupta, Taranjit Kukal, Sankaran Aniruddhan	A 1.1V 1.3GHz 4th order filter with feedforward miller compensation OPAMP for 5G applications.	MWSCAS	2019	DBLP DOI BibTeX RDF
20	Bakr Hesham, El-Sayed A. M. Hasaneen, Hesham F. A. Hamed	Design Procedure for Two-Stage CMOS Opamp using gm/ID design Methodology in 16 nm FinFET Technology.	ICM	2019	DBLP DOI BibTeX RDF
20	Nobukazu Takai, Masafumi Fukuda, Masahiro Saruta	Self-improvement of OPAmp parameters using Q-Learning.	SMACD	2019	DBLP DOI BibTeX RDF
20	Yohsuke Shiiki, Hiroki Ishikuro	Interface with Opamp Output-Impedance Calibration Technique for a Large Integrated 2-D Resistive Sensor Array.	ISCAS	2019	DBLP DOI BibTeX RDF
20	Ahmed ElShater, Calvin Y. Lee, Praveen Kumar Venkatachala, Mohamed Dessouky, Un-Ku Moon	Gm-Free Assisted Opamp Technique for Continuous Time Delta-Sigma Modulators.	ISCAS	2019	DBLP DOI BibTeX RDF
20	Wieslaw Kuzmicz	A Simple Ultra-Low Power Opamp in 22 nm FDSOI.	MIXDES	2019	DBLP DOI BibTeX RDF
20	Yohsuke Shiiki, Hiroki Ishikuro	A High Accuracy Opamp-less Interface Circuit for 2-D Cross-Point Resistive Sensor Array with Switch Resistance Calibration.	APCCAS	2019	DBLP DOI BibTeX RDF
20	Wei Wang 0177, Yan Zhu 0001, Chi-Hang Chan, Rui Paulo Martins	A 5.35-mW 10-MHz Single-Opamp Third-Order CT ΔΣ Modulator With CTC Amplifier and Adaptive Latch DAC Driver in 65-nm CMOS.	IEEE J. Solid State Circuits	2018	DBLP DOI BibTeX RDF
20	Jiaji Mao, Mingqiang Guo, Sai-Weng Sin, Rui Paulo Martins	A 14-Bit Split-Pipeline ADC With Self-Adjusted Opamp-Sharing Duty-Cycle and Bias Current.	IEEE Trans. Circuits Syst. II Express Briefs	2018	DBLP DOI BibTeX RDF
20	Andrés Fontana, Sebastián Matías Pazos, Fernando L. Aguirre, Felix Palumbo, Nahuel Vega, Nahuel A. Müller, Emanuel de la Fourniere, Mario Debray	Heavy Ion Microbeam Experimental Study of ASET on a Full-Custom CMOS OpAmp.	SBCCI	2018	DBLP DOI BibTeX RDF
20	Maged ElAnsary, Nima Soltani, Hossein Kassiri, Ruben Machado, Suzie Dufour, Peter L. Carlen, Michael Thompson, Roman Genov	50nW 5kHz-BW opamp-less ΔΣ impedance analyzer for brain neurochemistry monitoring.	ISSCC	2018	DBLP DOI BibTeX RDF
20	Sung-En Hsieh, Chih-Cheng Hsieh	A 0.4V 13b 270kS/S SAR-ISDM ADC with an opamp-less time-domain integrator.	ISSCC	2018	DBLP DOI BibTeX RDF
20	Mohammad Reza Pazhouhandeh, Hossein Kassiri, Aly Shoukry, Iliya Weisspapir, Peter L. Carlen, Roman Genov	Artifact-Tolerant Opamp-Less Delta-Modulated Bidirectional Neuro-Interface.	VLSI Circuits	2018	DBLP DOI BibTeX RDF
20	Rajasekhar Nagulapalli, Khaled Hayatleh, Steve Barker, Saddam Zourob, Nabil Yassine, B. Naresh Kumar Reddy	A Technique to Reduce the Capacitor Size in Two Stage Miller Compensated Opamp.	ICCCNT	2018	DBLP DOI BibTeX RDF
20	Yi Zhang 0023, Chia-Hung Chen, Tao He 0001, Gabor C. Temes	A 16 b Multi-Step Incremental Analog-to-Digital Converter With Single-Opamp Multi-Slope Extended Counting.	IEEE J. Solid State Circuits	2017	DBLP DOI BibTeX RDF
20	I-Jen Chao, Bin-Da Liu, Soon-Jyh Chang, Chun-Yueh Huang, Hsin-Wen Ting	Analyses of Splittable Amplifier Technique and Cancellation of Memory Effect for Opamp Sharing.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
20	Subrahmanyam Boyapati, Jean-Michel Redoute, Maryam Shojaei Baghini	Design of A Novel Highly EMI-Immune CMOS Miller OpAmp Considering Channel Length Modulation.	IEEE Trans. Circuits Syst. I Regul. Pap.	2017	DBLP DOI BibTeX RDF
20	Liang Qi, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, Rui Paulo Martins	A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH Δ Σ Modulator With Multirate Opamp Sharing.	IEEE Trans. Circuits Syst. I Regul. Pap.	2017	DBLP DOI BibTeX RDF
20	Patinya Ketthong, Wimol San-Um, Banlue Srisuchinwong, Masayoshi Tachibana	A simple current-reversible chaotic jerk circuit using inherent tanh(x) of an opamp.	IEICE Electron. Express	2017	DBLP DOI BibTeX RDF
20	Greeshma R, Anoop V. K, B. Venkataramani	A Novel Opamp and Capacitor Sharing 10 Bit 20 MS/s Low Power Pipelined ADC in 0.18µm CMOS Technology.	ISVLSI	2017	DBLP DOI BibTeX RDF
20	Lida Kouhalvandi, Sercan Aygün, Ece Olcay Günes, Mürvet Kirci	An improved 2 stage opamp with rail-to-rai! gain-boosted folded cascode input stage and monticelli rail-to-rail class AB output stage.	ICECS	2017	DBLP DOI BibTeX RDF
20	Marcello De Matteis, Andrea Donno, Stefano Marinaci, Stefano D'Amico, Andrea Baschirotto	A 0.9V 3rd-order single-OPAMP analog filter in 28nm CMOS-bulk.	IWASI	2017	DBLP DOI BibTeX RDF
20	Wei Wang 0177, Yan Zhu 0001, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins	A 5.35 mW 10 MHz bandwidth CT third-order ΔΣ modulator with single Opamp achieving 79.6/84.5 dB SNDR/DR in 65 nm CMOS.	A-SSCC	2017	DBLP DOI BibTeX RDF
20	Yang Xu 0005, Zehong Zhang, Baoyong Chi, Nan Qi, Hualin Cai, Zhihua Wang 0001	A 5-/20-MHz BW Reconfigurable Quadrature Bandpass CT ΔΣ ADC With AntiPole-Splitting Opamp and Digital I/Q Calibration.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
20	Mohsen Tamaddon, Mohammad Yavari	High-performance time-based continuous-time sigma-delta modulators using single-opamp resonator and noise-shaped quantizer.	Microelectron. J.	2016	DBLP DOI BibTeX RDF
20	Johannes Wagner 0003, Stefan Reich, Rudolf Ritter, Jens Anders, Maurits Ortmanns	Finite GBW in single OpAmp CT ΣΔ modulators.	ICECS	2016	DBLP DOI BibTeX RDF
20	Aditya Raj, Shyam Akashe	Power and Area Efficient Capacitor Multiplier Technique for Multi-Fin Two Stage Opamp.	ICTCS	2016	DBLP DOI BibTeX RDF
20	Zhijie Chen, Masaya Miyahara, Akira Matsuzawa	A stability-improved single-opamp third-order ΣΔ modulator by using a fully-passive noise-shaping SAR ADC and passive adder.	ESSCIRC	2016	DBLP DOI BibTeX RDF