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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 23 occurrences of 18 keywords
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Results
Found 17 publication records. Showing 17 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
117 | Hui Liu, Huawei Li 0001, Yu Hu 0001, Xiaowei Li 0001 |
A Scan-Based Delay Test Method for Reduction of Overtesting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 521-526, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
overtesting, SeBoS, delay test, IR drop |
91 | Ilia Polian, Hideo Fujiwara |
Functional Constraints vs. Test Compression in Scan-Based Delay Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 23(5), pp. 445-455, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Overtesting prevention, Scan-based delay test, Test compression, Functional constraints |
91 | Ilia Polian, Hideo Fujiwara |
Functional constraints vs. test compression in scan-based delay testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 1039-1044, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
overtesting prevention, scan-based delay test, test compression, functional constraints |
63 | Yung-Chieh Lin, Feng Lu 0002, Kwang-Ting Cheng |
Pseudofunctional testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(8), pp. 1535-1546, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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63 | Gang Chen 0011, Sudhakar M. Reddy, Irith Pomeranz |
Procedures for Identifying Untestable and Redundant Transition Faults in Synchronous Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings, pp. 36-41, 2003, IEEE Computer Society, 0-7695-2025-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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42 | Irith Pomeranz, Sudhakar M. Reddy |
Improving the Transition Fault Coverage of Functional Broadside Tests by Observation Point Insertion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(7), pp. 931-936, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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28 | Kazuteru Namba, Hideo Ito |
Test Sets for Robust Path Delay Fault Testing on Two-Rail Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 60(10), pp. 1459-1470, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
Two-rail logic circuit, overtesting, testability, monotone function, path delay fault testing |
28 | Irith Pomeranz, Sudhakar M. Reddy |
On Generating Tests that Avoid the Detection of Redundant Faults in Synchronous Sequential Circuits with Full Scan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(4), pp. 491-495, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
overtesting, test generation, Design-for-testability, synchronous sequential circuits, redundant faults, full-scan, fault dominance |
21 | Irith Pomeranz, Sudhakar M. Reddy |
Functional Broadside Tests Under an Expanded Definition of Functional Operation Conditions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(1), pp. 121-129, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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21 | Irith Pomeranz, Sudhakar M. Reddy |
Expanded Definition of Functional Operation Conditions and its Effects on the Computation of Functional Broadside Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, pp. 317-322, 2008, IEEE Computer Society, 978-0-7695-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
functional broadside tests, test generation, transition faults, reachable states, full-scan circuits |
21 | Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu |
On Common-Mode Skewed-Load and Broadside Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 151-156, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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21 | Zahi S. Abuhamdeh, Bob Hannagan, Jeff Remmers, Alfred L. Crouch |
A Production IR-Drop Screen on a Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 24(3), pp. 216-224, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
power-related failures, screen on a chip, power rails, production screen, IR drop |
21 | Irith Pomeranz, Sudhakar M. Reddy |
Scan-Based Delay Fault Tests for Diagnosis of Transition Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 4-6 October 2006, Arlington, Virginia, USA, pp. 419-427, 2006, IEEE Computer Society, 0-7695-2706-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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21 | Xiao Liu 0010, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran |
Efficient techniques for transition testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 10(2), pp. 258-278, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
test chain, test data volume reduction, transition faults, Test application time reduction, yield loss |
21 | Xiao Liu 0010, Michael S. Hsiao |
A Novel Transition Fault ATPG That Reduces Yield Loss. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 22(6), pp. 576-584, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Hardware I Computing Methodologies |
21 | Dirk Niggemeyer, Elizabeth M. Rudnick |
Automatic Generation of Diagnostic Memory Tests Based on Fault Decomposition and Output Tracing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(9), pp. 1134-1146, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
21 | Xiao Liu 0010, Michael S. Hsiao |
Constrained ATPG for Broadside Transition Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 3-5 November 2003, Boston, MA, USA, Proceedings, pp. 175-, 2003, IEEE Computer Society, 0-7695-2042-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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